1 /* $NetBSD: r8a774e1-cpg-mssr.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* R8A774E1 CPG Core Clocks */ 13 #define R8A774E1_CLK_Z 0 14 #define R8A774E1_CLK_Z2 1 15 #define R8A774E1_CLK_ZG 2 16 #define R8A774E1_CLK_ZTR 3 17 #define R8A774E1_CLK_ZTRD2 4 18 #define R8A774E1_CLK_ZT 5 19 #define R8A774E1_CLK_ZX 6 20 #define R8A774E1_CLK_S0D1 7 21 #define R8A774E1_CLK_S0D2 8 22 #define R8A774E1_CLK_S0D3 9 23 #define R8A774E1_CLK_S0D4 10 24 #define R8A774E1_CLK_S0D6 11 25 #define R8A774E1_CLK_S0D8 12 26 #define R8A774E1_CLK_S0D12 13 27 #define R8A774E1_CLK_S1D2 14 28 #define R8A774E1_CLK_S1D4 15 29 #define R8A774E1_CLK_S2D1 16 30 #define R8A774E1_CLK_S2D2 17 31 #define R8A774E1_CLK_S2D4 18 32 #define R8A774E1_CLK_S3D1 19 33 #define R8A774E1_CLK_S3D2 20 34 #define R8A774E1_CLK_S3D4 21 35 #define R8A774E1_CLK_LB 22 36 #define R8A774E1_CLK_CL 23 37 #define R8A774E1_CLK_ZB3 24 38 #define R8A774E1_CLK_ZB3D2 25 39 #define R8A774E1_CLK_ZB3D4 26 40 #define R8A774E1_CLK_CR 27 41 #define R8A774E1_CLK_CRD2 28 42 #define R8A774E1_CLK_SD0H 29 43 #define R8A774E1_CLK_SD0 30 44 #define R8A774E1_CLK_SD1H 31 45 #define R8A774E1_CLK_SD1 32 46 #define R8A774E1_CLK_SD2H 33 47 #define R8A774E1_CLK_SD2 34 48 #define R8A774E1_CLK_SD3H 35 49 #define R8A774E1_CLK_SD3 36 50 #define R8A774E1_CLK_RPC 37 51 #define R8A774E1_CLK_RPCD2 38 52 #define R8A774E1_CLK_MSO 39 53 #define R8A774E1_CLK_HDMI 40 54 #define R8A774E1_CLK_CSI0 41 55 #define R8A774E1_CLK_CP 42 56 #define R8A774E1_CLK_CPEX 43 57 #define R8A774E1_CLK_R 44 58 #define R8A774E1_CLK_OSC 45 59 #define R8A774E1_CLK_CANFD 46 60 61 #endif /* __DT_BINDINGS_CLOCK_R8A774E1_CPG_MSSR_H__ */ 62