1 /* $NetBSD: r8a774c0-cpg-mssr.h,v 1.1.1.2 2019/05/25 11:29:13 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a774c0 CPG Core Clocks */ 13 #define R8A774C0_CLK_Z2 0 14 #define R8A774C0_CLK_ZG 1 15 #define R8A774C0_CLK_ZTR 2 16 #define R8A774C0_CLK_ZT 3 17 #define R8A774C0_CLK_ZX 4 18 #define R8A774C0_CLK_S0D1 5 19 #define R8A774C0_CLK_S0D3 6 20 #define R8A774C0_CLK_S0D6 7 21 #define R8A774C0_CLK_S0D12 8 22 #define R8A774C0_CLK_S0D24 9 23 #define R8A774C0_CLK_S1D1 10 24 #define R8A774C0_CLK_S1D2 11 25 #define R8A774C0_CLK_S1D4 12 26 #define R8A774C0_CLK_S2D1 13 27 #define R8A774C0_CLK_S2D2 14 28 #define R8A774C0_CLK_S2D4 15 29 #define R8A774C0_CLK_S3D1 16 30 #define R8A774C0_CLK_S3D2 17 31 #define R8A774C0_CLK_S3D4 18 32 #define R8A774C0_CLK_S0D6C 19 33 #define R8A774C0_CLK_S3D1C 20 34 #define R8A774C0_CLK_S3D2C 21 35 #define R8A774C0_CLK_S3D4C 22 36 #define R8A774C0_CLK_LB 23 37 #define R8A774C0_CLK_CL 24 38 #define R8A774C0_CLK_ZB3 25 39 #define R8A774C0_CLK_ZB3D2 26 40 #define R8A774C0_CLK_CR 27 41 #define R8A774C0_CLK_CRD2 28 42 #define R8A774C0_CLK_SD0H 29 43 #define R8A774C0_CLK_SD0 30 44 #define R8A774C0_CLK_SD1H 31 45 #define R8A774C0_CLK_SD1 32 46 #define R8A774C0_CLK_SD3H 33 47 #define R8A774C0_CLK_SD3 34 48 #define R8A774C0_CLK_RPC 35 49 #define R8A774C0_CLK_RPCD2 36 50 #define R8A774C0_CLK_ZA2 37 51 #define R8A774C0_CLK_ZA8 38 52 #define R8A774C0_CLK_Z2D 39 53 #define R8A774C0_CLK_MSO 40 54 #define R8A774C0_CLK_R 41 55 #define R8A774C0_CLK_OSC 42 56 #define R8A774C0_CLK_LV0 43 57 #define R8A774C0_CLK_LV1 44 58 #define R8A774C0_CLK_CSI0 45 59 #define R8A774C0_CLK_CP 46 60 #define R8A774C0_CLK_CPEX 47 61 #define R8A774C0_CLK_CANFD 48 62 63 #endif /* __DT_BINDINGS_CLOCK_R8A774C0_CPG_MSSR_H__ */ 64