1 /* $NetBSD: r8a774b1-cpg-mssr.h,v 1.1.1.1 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2019 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a774b1 CPG Core Clocks */ 13 #define R8A774B1_CLK_Z 0 14 #define R8A774B1_CLK_ZG 1 15 #define R8A774B1_CLK_ZTR 2 16 #define R8A774B1_CLK_ZTRD2 3 17 #define R8A774B1_CLK_ZT 4 18 #define R8A774B1_CLK_ZX 5 19 #define R8A774B1_CLK_S0D1 6 20 #define R8A774B1_CLK_S0D2 7 21 #define R8A774B1_CLK_S0D3 8 22 #define R8A774B1_CLK_S0D4 9 23 #define R8A774B1_CLK_S0D6 10 24 #define R8A774B1_CLK_S0D8 11 25 #define R8A774B1_CLK_S0D12 12 26 #define R8A774B1_CLK_S1D2 13 27 #define R8A774B1_CLK_S1D4 14 28 #define R8A774B1_CLK_S2D1 15 29 #define R8A774B1_CLK_S2D2 16 30 #define R8A774B1_CLK_S2D4 17 31 #define R8A774B1_CLK_S3D1 18 32 #define R8A774B1_CLK_S3D2 19 33 #define R8A774B1_CLK_S3D4 20 34 #define R8A774B1_CLK_LB 21 35 #define R8A774B1_CLK_CL 22 36 #define R8A774B1_CLK_ZB3 23 37 #define R8A774B1_CLK_ZB3D2 24 38 #define R8A774B1_CLK_CR 25 39 #define R8A774B1_CLK_DDR 26 40 #define R8A774B1_CLK_SD0H 27 41 #define R8A774B1_CLK_SD0 28 42 #define R8A774B1_CLK_SD1H 29 43 #define R8A774B1_CLK_SD1 30 44 #define R8A774B1_CLK_SD2H 31 45 #define R8A774B1_CLK_SD2 32 46 #define R8A774B1_CLK_SD3H 33 47 #define R8A774B1_CLK_SD3 34 48 #define R8A774B1_CLK_RPC 35 49 #define R8A774B1_CLK_RPCD2 36 50 #define R8A774B1_CLK_MSO 37 51 #define R8A774B1_CLK_HDMI 38 52 #define R8A774B1_CLK_CSI0 39 53 #define R8A774B1_CLK_CP 40 54 #define R8A774B1_CLK_CPEX 41 55 #define R8A774B1_CLK_R 42 56 #define R8A774B1_CLK_OSC 43 57 #define R8A774B1_CLK_CANFD 44 58 59 #endif /* __DT_BINDINGS_CLOCK_R8A774B1_CPG_MSSR_H__ */ 60