1 /* $NetBSD: r8a77470-cpg-mssr.h,v 1.1.1.1 2018/06/27 16:27:08 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a77470 CPG Core Clocks */ 13 #define R8A77470_CLK_Z2 0 14 #define R8A77470_CLK_ZTR 1 15 #define R8A77470_CLK_ZTRD2 2 16 #define R8A77470_CLK_ZT 3 17 #define R8A77470_CLK_ZX 4 18 #define R8A77470_CLK_ZS 5 19 #define R8A77470_CLK_HP 6 20 #define R8A77470_CLK_B 7 21 #define R8A77470_CLK_LB 8 22 #define R8A77470_CLK_P 9 23 #define R8A77470_CLK_CL 10 24 #define R8A77470_CLK_CP 11 25 #define R8A77470_CLK_M2 12 26 #define R8A77470_CLK_ZB3 13 27 #define R8A77470_CLK_SDH 14 28 #define R8A77470_CLK_SD0 15 29 #define R8A77470_CLK_SD1 16 30 #define R8A77470_CLK_SD2 17 31 #define R8A77470_CLK_MP 18 32 #define R8A77470_CLK_QSPI 19 33 #define R8A77470_CLK_CPEX 20 34 #define R8A77470_CLK_RCAN 21 35 #define R8A77470_CLK_R 22 36 #define R8A77470_CLK_OSC 23 37 38 #endif /* __DT_BINDINGS_CLOCK_R8A77470_CPG_MSSR_H__ */ 39