1 /* $NetBSD: r8a7745-cpg-mssr.h,v 1.1.1.2 2019/01/22 14:57:02 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2016 Cogent Embedded Inc. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a7745 CPG Core Clocks */ 13 #define R8A7745_CLK_Z2 0 14 #define R8A7745_CLK_ZG 1 15 #define R8A7745_CLK_ZTR 2 16 #define R8A7745_CLK_ZTRD2 3 17 #define R8A7745_CLK_ZT 4 18 #define R8A7745_CLK_ZX 5 19 #define R8A7745_CLK_ZS 6 20 #define R8A7745_CLK_HP 7 21 #define R8A7745_CLK_B 9 22 #define R8A7745_CLK_LB 10 23 #define R8A7745_CLK_P 11 24 #define R8A7745_CLK_CL 12 25 #define R8A7745_CLK_CP 13 26 #define R8A7745_CLK_M2 14 27 #define R8A7745_CLK_ZB3 16 28 #define R8A7745_CLK_ZB3D2 17 29 #define R8A7745_CLK_DDR 18 30 #define R8A7745_CLK_SDH 19 31 #define R8A7745_CLK_SD0 20 32 #define R8A7745_CLK_SD2 21 33 #define R8A7745_CLK_SD3 22 34 #define R8A7745_CLK_MMC0 23 35 #define R8A7745_CLK_MP 24 36 #define R8A7745_CLK_QSPI 25 37 #define R8A7745_CLK_CPEX 26 38 #define R8A7745_CLK_RCAN 27 39 #define R8A7745_CLK_R 28 40 #define R8A7745_CLK_OSC 29 41 42 #endif /* __DT_BINDINGS_CLOCK_R8A7745_CPG_MSSR_H__ */ 43