1 /* $NetBSD: r8a7744-cpg-mssr.h,v 1.1.1.1 2019/01/22 14:57:01 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a7744 CPG Core Clocks */ 13 #define R8A7744_CLK_Z 0 14 #define R8A7744_CLK_ZG 1 15 #define R8A7744_CLK_ZTR 2 16 #define R8A7744_CLK_ZTRD2 3 17 #define R8A7744_CLK_ZT 4 18 #define R8A7744_CLK_ZX 5 19 #define R8A7744_CLK_ZS 6 20 #define R8A7744_CLK_HP 7 21 #define R8A7744_CLK_B 9 22 #define R8A7744_CLK_LB 10 23 #define R8A7744_CLK_P 11 24 #define R8A7744_CLK_CL 12 25 #define R8A7744_CLK_M2 13 26 #define R8A7744_CLK_ZB3 15 27 #define R8A7744_CLK_ZB3D2 16 28 #define R8A7744_CLK_DDR 17 29 #define R8A7744_CLK_SDH 18 30 #define R8A7744_CLK_SD0 19 31 #define R8A7744_CLK_SD2 20 32 #define R8A7744_CLK_SD3 21 33 #define R8A7744_CLK_MMC0 22 34 #define R8A7744_CLK_MP 23 35 #define R8A7744_CLK_QSPI 26 36 #define R8A7744_CLK_CP 27 37 #define R8A7744_CLK_RCAN 28 38 #define R8A7744_CLK_R 29 39 #define R8A7744_CLK_OSC 30 40 41 #endif /* __DT_BINDINGS_CLOCK_R8A7744_CPG_MSSR_H__ */ 42