1 /* $NetBSD: r8a7742-cpg-mssr.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 #ifndef __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 8 #define __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ 9 10 #include <dt-bindings/clock/renesas-cpg-mssr.h> 11 12 /* r8a7742 CPG Core Clocks */ 13 #define R8A7742_CLK_Z 0 14 #define R8A7742_CLK_Z2 1 15 #define R8A7742_CLK_ZG 2 16 #define R8A7742_CLK_ZTR 3 17 #define R8A7742_CLK_ZTRD2 4 18 #define R8A7742_CLK_ZT 5 19 #define R8A7742_CLK_ZX 6 20 #define R8A7742_CLK_ZS 7 21 #define R8A7742_CLK_HP 8 22 #define R8A7742_CLK_B 9 23 #define R8A7742_CLK_LB 10 24 #define R8A7742_CLK_P 11 25 #define R8A7742_CLK_CL 12 26 #define R8A7742_CLK_M2 13 27 #define R8A7742_CLK_ZB3 14 28 #define R8A7742_CLK_ZB3D2 15 29 #define R8A7742_CLK_DDR 16 30 #define R8A7742_CLK_SDH 17 31 #define R8A7742_CLK_SD0 18 32 #define R8A7742_CLK_SD1 19 33 #define R8A7742_CLK_SD2 20 34 #define R8A7742_CLK_SD3 21 35 #define R8A7742_CLK_MMC0 22 36 #define R8A7742_CLK_MMC1 23 37 #define R8A7742_CLK_MP 24 38 #define R8A7742_CLK_QSPI 25 39 #define R8A7742_CLK_CP 26 40 #define R8A7742_CLK_RCAN 27 41 #define R8A7742_CLK_R 28 42 #define R8A7742_CLK_OSC 29 43 44 #endif /* __DT_BINDINGS_CLOCK_R8A7742_CPG_MSSR_H__ */ 45