xref: /netbsd-src/sys/external/gpl2/dts/dist/include/dt-bindings/clock/qcom,gcc-ipq6018.h (revision 58c3e048f5c2f43ee7e820013e37079f2e0b6ae5)
1 /*	$NetBSD: qcom,gcc-ipq6018.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $	*/
2 
3 /* SPDX-License-Identifier: GPL-2.0 */
4 /*
5  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
6  */
7 
8 #ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
9 #define _DT_BINDINGS_CLOCK_IPQ_GCC_6018_H
10 
11 #define GPLL0					0
12 #define UBI32_PLL				1
13 #define GPLL6					2
14 #define GPLL4					3
15 #define PCNOC_BFDCD_CLK_SRC			4
16 #define GPLL2					5
17 #define NSS_CRYPTO_PLL				6
18 #define NSS_PPE_CLK_SRC				7
19 #define GCC_XO_CLK_SRC				8
20 #define NSS_CE_CLK_SRC				9
21 #define GCC_SLEEP_CLK_SRC			10
22 #define APSS_AHB_CLK_SRC			11
23 #define NSS_PORT5_RX_CLK_SRC			12
24 #define NSS_PORT5_TX_CLK_SRC			13
25 #define PCIE0_AXI_CLK_SRC			14
26 #define USB0_MASTER_CLK_SRC			15
27 #define APSS_AHB_POSTDIV_CLK_SRC		16
28 #define NSS_PORT1_RX_CLK_SRC			17
29 #define NSS_PORT1_TX_CLK_SRC			18
30 #define NSS_PORT2_RX_CLK_SRC			19
31 #define NSS_PORT2_TX_CLK_SRC			20
32 #define NSS_PORT3_RX_CLK_SRC			21
33 #define NSS_PORT3_TX_CLK_SRC			22
34 #define NSS_PORT4_RX_CLK_SRC			23
35 #define NSS_PORT4_TX_CLK_SRC			24
36 #define NSS_PORT5_RX_DIV_CLK_SRC		25
37 #define NSS_PORT5_TX_DIV_CLK_SRC		26
38 #define APSS_AXI_CLK_SRC			27
39 #define NSS_CRYPTO_CLK_SRC			28
40 #define NSS_PORT1_RX_DIV_CLK_SRC		29
41 #define NSS_PORT1_TX_DIV_CLK_SRC		30
42 #define NSS_PORT2_RX_DIV_CLK_SRC		31
43 #define NSS_PORT2_TX_DIV_CLK_SRC		32
44 #define NSS_PORT3_RX_DIV_CLK_SRC		33
45 #define NSS_PORT3_TX_DIV_CLK_SRC		34
46 #define NSS_PORT4_RX_DIV_CLK_SRC		35
47 #define NSS_PORT4_TX_DIV_CLK_SRC		36
48 #define NSS_UBI0_CLK_SRC			37
49 #define BLSP1_QUP1_I2C_APPS_CLK_SRC		38
50 #define BLSP1_QUP1_SPI_APPS_CLK_SRC		39
51 #define BLSP1_QUP2_I2C_APPS_CLK_SRC		40
52 #define BLSP1_QUP2_SPI_APPS_CLK_SRC		41
53 #define BLSP1_QUP3_I2C_APPS_CLK_SRC		42
54 #define BLSP1_QUP3_SPI_APPS_CLK_SRC		43
55 #define BLSP1_QUP4_I2C_APPS_CLK_SRC		44
56 #define BLSP1_QUP4_SPI_APPS_CLK_SRC		45
57 #define BLSP1_QUP5_I2C_APPS_CLK_SRC		46
58 #define BLSP1_QUP5_SPI_APPS_CLK_SRC		47
59 #define BLSP1_QUP6_I2C_APPS_CLK_SRC		48
60 #define BLSP1_QUP6_SPI_APPS_CLK_SRC		49
61 #define BLSP1_UART1_APPS_CLK_SRC		50
62 #define BLSP1_UART2_APPS_CLK_SRC		51
63 #define BLSP1_UART3_APPS_CLK_SRC		52
64 #define BLSP1_UART4_APPS_CLK_SRC		53
65 #define BLSP1_UART5_APPS_CLK_SRC		54
66 #define BLSP1_UART6_APPS_CLK_SRC		55
67 #define CRYPTO_CLK_SRC				56
68 #define NSS_UBI0_DIV_CLK_SRC			57
69 #define PCIE0_AUX_CLK_SRC			58
70 #define PCIE0_PIPE_CLK_SRC			59
71 #define SDCC1_APPS_CLK_SRC			60
72 #define USB0_AUX_CLK_SRC			61
73 #define USB0_MOCK_UTMI_CLK_SRC			62
74 #define USB0_PIPE_CLK_SRC			63
75 #define USB1_MOCK_UTMI_CLK_SRC			64
76 #define GCC_APSS_AHB_CLK			65
77 #define GCC_APSS_AXI_CLK			66
78 #define GCC_BLSP1_AHB_CLK			67
79 #define GCC_BLSP1_QUP1_I2C_APPS_CLK		68
80 #define GCC_BLSP1_QUP1_SPI_APPS_CLK		69
81 #define GCC_BLSP1_QUP2_I2C_APPS_CLK		70
82 #define GCC_BLSP1_QUP2_SPI_APPS_CLK		71
83 #define GCC_BLSP1_QUP3_I2C_APPS_CLK		72
84 #define GCC_BLSP1_QUP3_SPI_APPS_CLK		73
85 #define GCC_BLSP1_QUP4_I2C_APPS_CLK		74
86 #define GCC_BLSP1_QUP4_SPI_APPS_CLK		75
87 #define GCC_BLSP1_QUP5_I2C_APPS_CLK		76
88 #define GCC_BLSP1_QUP5_SPI_APPS_CLK		77
89 #define GCC_BLSP1_QUP6_I2C_APPS_CLK		78
90 #define GCC_BLSP1_QUP6_SPI_APPS_CLK		79
91 #define GCC_BLSP1_UART1_APPS_CLK		80
92 #define GCC_BLSP1_UART2_APPS_CLK		81
93 #define GCC_BLSP1_UART3_APPS_CLK		82
94 #define GCC_BLSP1_UART4_APPS_CLK		83
95 #define GCC_BLSP1_UART5_APPS_CLK		84
96 #define GCC_BLSP1_UART6_APPS_CLK		85
97 #define GCC_CRYPTO_AHB_CLK			86
98 #define GCC_CRYPTO_AXI_CLK			87
99 #define GCC_CRYPTO_CLK				88
100 #define GCC_XO_CLK				89
101 #define GCC_XO_DIV4_CLK				90
102 #define GCC_MDIO_AHB_CLK			91
103 #define GCC_CRYPTO_PPE_CLK			92
104 #define GCC_NSS_CE_APB_CLK			93
105 #define GCC_NSS_CE_AXI_CLK			94
106 #define GCC_NSS_CFG_CLK				95
107 #define GCC_NSS_CRYPTO_CLK			96
108 #define GCC_NSS_CSR_CLK				97
109 #define GCC_NSS_EDMA_CFG_CLK			98
110 #define GCC_NSS_EDMA_CLK			99
111 #define GCC_NSS_NOC_CLK				100
112 #define GCC_NSS_PORT1_RX_CLK			101
113 #define GCC_NSS_PORT1_TX_CLK			102
114 #define GCC_NSS_PORT2_RX_CLK			103
115 #define GCC_NSS_PORT2_TX_CLK			104
116 #define GCC_NSS_PORT3_RX_CLK			105
117 #define GCC_NSS_PORT3_TX_CLK			106
118 #define GCC_NSS_PORT4_RX_CLK			107
119 #define GCC_NSS_PORT4_TX_CLK			108
120 #define GCC_NSS_PORT5_RX_CLK			109
121 #define GCC_NSS_PORT5_TX_CLK			110
122 #define GCC_NSS_PPE_CFG_CLK			111
123 #define GCC_NSS_PPE_CLK				112
124 #define GCC_NSS_PPE_IPE_CLK			113
125 #define GCC_NSS_PTP_REF_CLK			114
126 #define GCC_NSSNOC_CE_APB_CLK			115
127 #define GCC_NSSNOC_CE_AXI_CLK			116
128 #define GCC_NSSNOC_CRYPTO_CLK			117
129 #define GCC_NSSNOC_PPE_CFG_CLK			118
130 #define GCC_NSSNOC_PPE_CLK			119
131 #define GCC_NSSNOC_QOSGEN_REF_CLK		120
132 #define GCC_NSSNOC_TIMEOUT_REF_CLK		121
133 #define GCC_NSSNOC_UBI0_AHB_CLK			122
134 #define GCC_PORT1_MAC_CLK			123
135 #define GCC_PORT2_MAC_CLK			124
136 #define GCC_PORT3_MAC_CLK			125
137 #define GCC_PORT4_MAC_CLK			126
138 #define GCC_PORT5_MAC_CLK			127
139 #define GCC_UBI0_AHB_CLK			128
140 #define GCC_UBI0_AXI_CLK			129
141 #define GCC_UBI0_CORE_CLK			130
142 #define GCC_PCIE0_AHB_CLK			131
143 #define GCC_PCIE0_AUX_CLK			132
144 #define GCC_PCIE0_AXI_M_CLK			133
145 #define GCC_PCIE0_AXI_S_CLK			134
146 #define GCC_PCIE0_PIPE_CLK			135
147 #define GCC_PRNG_AHB_CLK			136
148 #define GCC_QPIC_AHB_CLK			137
149 #define GCC_QPIC_CLK				138
150 #define GCC_SDCC1_AHB_CLK			139
151 #define GCC_SDCC1_APPS_CLK			140
152 #define GCC_UNIPHY0_AHB_CLK			141
153 #define GCC_UNIPHY0_PORT1_RX_CLK		142
154 #define GCC_UNIPHY0_PORT1_TX_CLK		143
155 #define GCC_UNIPHY0_PORT2_RX_CLK		144
156 #define GCC_UNIPHY0_PORT2_TX_CLK		145
157 #define GCC_UNIPHY0_PORT3_RX_CLK		146
158 #define GCC_UNIPHY0_PORT3_TX_CLK		147
159 #define GCC_UNIPHY0_PORT4_RX_CLK		148
160 #define GCC_UNIPHY0_PORT4_TX_CLK		149
161 #define GCC_UNIPHY0_PORT5_RX_CLK		150
162 #define GCC_UNIPHY0_PORT5_TX_CLK		151
163 #define GCC_UNIPHY0_SYS_CLK			152
164 #define GCC_UNIPHY1_AHB_CLK			153
165 #define GCC_UNIPHY1_PORT5_RX_CLK		154
166 #define GCC_UNIPHY1_PORT5_TX_CLK		155
167 #define GCC_UNIPHY1_SYS_CLK			156
168 #define GCC_USB0_AUX_CLK			157
169 #define GCC_USB0_MASTER_CLK			158
170 #define GCC_USB0_MOCK_UTMI_CLK			159
171 #define GCC_USB0_PHY_CFG_AHB_CLK		160
172 #define GCC_USB0_PIPE_CLK			161
173 #define GCC_USB0_SLEEP_CLK			162
174 #define GCC_USB1_MASTER_CLK			163
175 #define GCC_USB1_MOCK_UTMI_CLK			164
176 #define GCC_USB1_PHY_CFG_AHB_CLK		165
177 #define GCC_USB1_SLEEP_CLK			166
178 #define GP1_CLK_SRC				167
179 #define GP2_CLK_SRC				168
180 #define GP3_CLK_SRC				169
181 #define GCC_GP1_CLK				170
182 #define GCC_GP2_CLK				171
183 #define GCC_GP3_CLK				172
184 #define SYSTEM_NOC_BFDCD_CLK_SRC		173
185 #define GCC_NSSNOC_SNOC_CLK			174
186 #define GCC_UBI0_NC_AXI_CLK			175
187 #define GCC_UBI1_NC_AXI_CLK			176
188 #define GPLL0_MAIN				177
189 #define UBI32_PLL_MAIN				178
190 #define GPLL6_MAIN				179
191 #define GPLL4_MAIN				180
192 #define GPLL2_MAIN				181
193 #define NSS_CRYPTO_PLL_MAIN			182
194 #define GCC_CMN_12GPLL_AHB_CLK			183
195 #define GCC_CMN_12GPLL_SYS_CLK			184
196 #define GCC_SNOC_BUS_TIMEOUT2_AHB_CLK		185
197 #define GCC_SYS_NOC_USB0_AXI_CLK		186
198 #define GCC_SYS_NOC_PCIE0_AXI_CLK		187
199 #define QDSS_TSCTR_CLK_SRC			188
200 #define QDSS_AT_CLK_SRC				189
201 #define GCC_QDSS_AT_CLK				190
202 #define GCC_QDSS_DAP_CLK			191
203 #define ADSS_PWM_CLK_SRC			192
204 #define GCC_ADSS_PWM_CLK			193
205 #define SDCC1_ICE_CORE_CLK_SRC			194
206 #define GCC_SDCC1_ICE_CORE_CLK			195
207 #define GCC_DCC_CLK				196
208 #define PCIE0_RCHNG_CLK_SRC			197
209 #define GCC_PCIE0_AXI_S_BRIDGE_CLK		198
210 #define PCIE0_RCHNG_CLK				199
211 #define UBI32_MEM_NOC_BFDCD_CLK_SRC		200
212 #define WCSS_AHB_CLK_SRC			201
213 #define Q6_AXI_CLK_SRC				202
214 #define GCC_Q6SS_PCLKDBG_CLK			203
215 #define GCC_Q6_TSCTR_1TO2_CLK			204
216 #define GCC_WCSS_CORE_TBU_CLK			205
217 #define GCC_WCSS_AXI_M_CLK			206
218 #define GCC_SYS_NOC_WCSS_AHB_CLK		207
219 #define GCC_Q6_AXIM_CLK				208
220 #define GCC_Q6SS_ATBM_CLK			209
221 #define GCC_WCSS_Q6_TBU_CLK			210
222 #define GCC_Q6_AXIM2_CLK			211
223 #define GCC_Q6_AHB_CLK				212
224 #define GCC_Q6_AHB_S_CLK			213
225 #define GCC_WCSS_DBG_IFC_APB_CLK		214
226 #define GCC_WCSS_DBG_IFC_ATB_CLK		215
227 #define GCC_WCSS_DBG_IFC_NTS_CLK		216
228 #define GCC_WCSS_DBG_IFC_DAPBUS_CLK		217
229 #define GCC_WCSS_DBG_IFC_APB_BDG_CLK		218
230 #define GCC_WCSS_DBG_IFC_ATB_BDG_CLK		219
231 #define GCC_WCSS_DBG_IFC_NTS_BDG_CLK		220
232 #define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK		221
233 #define GCC_WCSS_ECAHB_CLK			222
234 #define GCC_WCSS_ACMT_CLK			223
235 #define GCC_WCSS_AHB_S_CLK			224
236 #define GCC_RBCPR_WCSS_CLK			225
237 #define RBCPR_WCSS_CLK_SRC			226
238 #define GCC_RBCPR_WCSS_AHB_CLK			227
239 #define GCC_LPASS_CORE_AXIM_CLK			228
240 #define GCC_LPASS_SNOC_CFG_CLK			229
241 #define GCC_LPASS_Q6_AXIM_CLK			230
242 #define GCC_LPASS_Q6_ATBM_AT_CLK		231
243 #define GCC_LPASS_Q6_PCLKDBG_CLK		232
244 #define GCC_LPASS_Q6SS_TSCTR_1TO2_CLK		233
245 #define GCC_LPASS_Q6SS_TRIG_CLK			234
246 #define GCC_LPASS_TBU_CLK			235
247 #define LPASS_CORE_AXIM_CLK_SRC			236
248 #define LPASS_SNOC_CFG_CLK_SRC			237
249 #define LPASS_Q6_AXIM_CLK_SRC			238
250 #define GCC_PCNOC_LPASS_CLK			239
251 #define GCC_UBI0_UTCM_CLK			240
252 #define SNOC_NSSNOC_BFDCD_CLK_SRC		241
253 #define GCC_SNOC_NSSNOC_CLK			242
254 #define GCC_MEM_NOC_Q6_AXI_CLK			243
255 #define GCC_MEM_NOC_UBI32_CLK			244
256 #define GCC_MEM_NOC_LPASS_CLK			245
257 #define GCC_SNOC_LPASS_CFG_CLK			246
258 #define GCC_SYS_NOC_QDSS_STM_AXI_CLK		247
259 #define GCC_QDSS_STM_CLK			248
260 #define GCC_QDSS_TRACECLKIN_CLK			249
261 #define QDSS_STM_CLK_SRC			250
262 #define QDSS_TRACECLKIN_CLK_SRC			251
263 #define GCC_NSSNOC_ATB_CLK			252
264 #endif
265