1 /* $NetBSD: mt8167-clk.h,v 1.1.1.1 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (c) 2020 MediaTek Inc. 6 * Copyright (c) 2020 BayLibre, SAS. 7 * Author: James Liao <jamesjj.liao@mediatek.com> 8 * Fabien Parent <fparent@baylibre.com> 9 */ 10 11 #ifndef _DT_BINDINGS_CLK_MT8167_H 12 #define _DT_BINDINGS_CLK_MT8167_H 13 14 /* MT8167 is based on MT8516 */ 15 #include <dt-bindings/clock/mt8516-clk.h> 16 17 /* APMIXEDSYS */ 18 19 #define CLK_APMIXED_TVDPLL (CLK_APMIXED_NR_CLK + 0) 20 #define CLK_APMIXED_LVDSPLL (CLK_APMIXED_NR_CLK + 1) 21 #define CLK_APMIXED_HDMI_REF (CLK_APMIXED_NR_CLK + 2) 22 #define MT8167_CLK_APMIXED_NR_CLK (CLK_APMIXED_NR_CLK + 3) 23 24 /* TOPCKGEN */ 25 26 #define CLK_TOP_DSI0_LNTC_DSICK (CLK_TOP_NR_CLK + 0) 27 #define CLK_TOP_VPLL_DPIX (CLK_TOP_NR_CLK + 1) 28 #define CLK_TOP_LVDSTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 2) 29 #define CLK_TOP_HDMTX_CLKDIG_CTS (CLK_TOP_NR_CLK + 3) 30 #define CLK_TOP_LVDSPLL (CLK_TOP_NR_CLK + 4) 31 #define CLK_TOP_LVDSPLL_D2 (CLK_TOP_NR_CLK + 5) 32 #define CLK_TOP_LVDSPLL_D4 (CLK_TOP_NR_CLK + 6) 33 #define CLK_TOP_LVDSPLL_D8 (CLK_TOP_NR_CLK + 7) 34 #define CLK_TOP_MIPI_26M (CLK_TOP_NR_CLK + 8) 35 #define CLK_TOP_TVDPLL (CLK_TOP_NR_CLK + 9) 36 #define CLK_TOP_TVDPLL_D2 (CLK_TOP_NR_CLK + 10) 37 #define CLK_TOP_TVDPLL_D4 (CLK_TOP_NR_CLK + 11) 38 #define CLK_TOP_TVDPLL_D8 (CLK_TOP_NR_CLK + 12) 39 #define CLK_TOP_TVDPLL_D16 (CLK_TOP_NR_CLK + 13) 40 #define CLK_TOP_PWM_MM (CLK_TOP_NR_CLK + 14) 41 #define CLK_TOP_CAM_MM (CLK_TOP_NR_CLK + 15) 42 #define CLK_TOP_MFG_MM (CLK_TOP_NR_CLK + 16) 43 #define CLK_TOP_SPM_52M (CLK_TOP_NR_CLK + 17) 44 #define CLK_TOP_MIPI_26M_DBG (CLK_TOP_NR_CLK + 18) 45 #define CLK_TOP_SCAM_MM (CLK_TOP_NR_CLK + 19) 46 #define CLK_TOP_SMI_MM (CLK_TOP_NR_CLK + 20) 47 #define CLK_TOP_26M_HDMI_SIFM (CLK_TOP_NR_CLK + 21) 48 #define CLK_TOP_26M_CEC (CLK_TOP_NR_CLK + 22) 49 #define CLK_TOP_32K_CEC (CLK_TOP_NR_CLK + 23) 50 #define CLK_TOP_GCPU_B (CLK_TOP_NR_CLK + 24) 51 #define CLK_TOP_RG_VDEC (CLK_TOP_NR_CLK + 25) 52 #define CLK_TOP_RG_FDPI0 (CLK_TOP_NR_CLK + 26) 53 #define CLK_TOP_RG_FDPI1 (CLK_TOP_NR_CLK + 27) 54 #define CLK_TOP_RG_AXI_MFG (CLK_TOP_NR_CLK + 28) 55 #define CLK_TOP_RG_SLOW_MFG (CLK_TOP_NR_CLK + 29) 56 #define CLK_TOP_GFMUX_EMI1X_SEL (CLK_TOP_NR_CLK + 30) 57 #define CLK_TOP_CSW_MUX_MFG_SEL (CLK_TOP_NR_CLK + 31) 58 #define CLK_TOP_CAMTG_MM_SEL (CLK_TOP_NR_CLK + 32) 59 #define CLK_TOP_PWM_MM_SEL (CLK_TOP_NR_CLK + 33) 60 #define CLK_TOP_SPM_52M_SEL (CLK_TOP_NR_CLK + 34) 61 #define CLK_TOP_MFG_MM_SEL (CLK_TOP_NR_CLK + 35) 62 #define CLK_TOP_SMI_MM_SEL (CLK_TOP_NR_CLK + 36) 63 #define CLK_TOP_SCAM_MM_SEL (CLK_TOP_NR_CLK + 37) 64 #define CLK_TOP_VDEC_MM_SEL (CLK_TOP_NR_CLK + 38) 65 #define CLK_TOP_DPI0_MM_SEL (CLK_TOP_NR_CLK + 39) 66 #define CLK_TOP_DPI1_MM_SEL (CLK_TOP_NR_CLK + 40) 67 #define CLK_TOP_AXI_MFG_IN_SEL (CLK_TOP_NR_CLK + 41) 68 #define CLK_TOP_SLOW_MFG_SEL (CLK_TOP_NR_CLK + 42) 69 #define MT8167_CLK_TOP_NR_CLK (CLK_TOP_NR_CLK + 43) 70 71 /* MFGCFG */ 72 73 #define CLK_MFG_BAXI 0 74 #define CLK_MFG_BMEM 1 75 #define CLK_MFG_BG3D 2 76 #define CLK_MFG_B26M 3 77 #define CLK_MFG_NR_CLK 4 78 79 /* MMSYS */ 80 81 #define CLK_MM_SMI_COMMON 0 82 #define CLK_MM_SMI_LARB0 1 83 #define CLK_MM_CAM_MDP 2 84 #define CLK_MM_MDP_RDMA 3 85 #define CLK_MM_MDP_RSZ0 4 86 #define CLK_MM_MDP_RSZ1 5 87 #define CLK_MM_MDP_TDSHP 6 88 #define CLK_MM_MDP_WDMA 7 89 #define CLK_MM_MDP_WROT 8 90 #define CLK_MM_FAKE_ENG 9 91 #define CLK_MM_DISP_OVL0 10 92 #define CLK_MM_DISP_RDMA0 11 93 #define CLK_MM_DISP_RDMA1 12 94 #define CLK_MM_DISP_WDMA 13 95 #define CLK_MM_DISP_COLOR 14 96 #define CLK_MM_DISP_CCORR 15 97 #define CLK_MM_DISP_AAL 16 98 #define CLK_MM_DISP_GAMMA 17 99 #define CLK_MM_DISP_DITHER 18 100 #define CLK_MM_DISP_UFOE 19 101 #define CLK_MM_DISP_PWM_MM 20 102 #define CLK_MM_DISP_PWM_26M 21 103 #define CLK_MM_DSI_ENGINE 22 104 #define CLK_MM_DSI_DIGITAL 23 105 #define CLK_MM_DPI0_ENGINE 24 106 #define CLK_MM_DPI0_PXL 25 107 #define CLK_MM_LVDS_PXL 26 108 #define CLK_MM_LVDS_CTS 27 109 #define CLK_MM_DPI1_ENGINE 28 110 #define CLK_MM_DPI1_PXL 29 111 #define CLK_MM_HDMI_PXL 30 112 #define CLK_MM_HDMI_SPDIF 31 113 #define CLK_MM_HDMI_ADSP_BCK 32 114 #define CLK_MM_HDMI_PLL 33 115 #define CLK_MM_NR_CLK 34 116 117 /* IMGSYS */ 118 119 #define CLK_IMG_LARB1_SMI 0 120 #define CLK_IMG_CAM_SMI 1 121 #define CLK_IMG_CAM_CAM 2 122 #define CLK_IMG_SEN_TG 3 123 #define CLK_IMG_SEN_CAM 4 124 #define CLK_IMG_VENC 5 125 #define CLK_IMG_NR_CLK 6 126 127 /* VDECSYS */ 128 129 #define CLK_VDEC_CKEN 0 130 #define CLK_VDEC_LARB1_CKEN 1 131 #define CLK_VDEC_NR_CLK 2 132 133 #endif /* _DT_BINDINGS_CLK_MT8167_H */ 134