1 /* $NetBSD: mt7622-clk.h,v 1.1.1.2 2018/04/28 18:25:53 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2017 MediaTek Inc. 5 * Author: Chen Zhong <chen.zhong@mediatek.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #ifndef _DT_BINDINGS_CLK_MT7622_H 18 #define _DT_BINDINGS_CLK_MT7622_H 19 20 /* TOPCKGEN */ 21 22 #define CLK_TOP_TO_U2_PHY 0 23 #define CLK_TOP_TO_U2_PHY_1P 1 24 #define CLK_TOP_PCIE0_PIPE_EN 2 25 #define CLK_TOP_PCIE1_PIPE_EN 3 26 #define CLK_TOP_SSUSB_TX250M 4 27 #define CLK_TOP_SSUSB_EQ_RX250M 5 28 #define CLK_TOP_SSUSB_CDR_REF 6 29 #define CLK_TOP_SSUSB_CDR_FB 7 30 #define CLK_TOP_SATA_ASIC 8 31 #define CLK_TOP_SATA_RBC 9 32 #define CLK_TOP_TO_USB3_SYS 10 33 #define CLK_TOP_P1_1MHZ 11 34 #define CLK_TOP_4MHZ 12 35 #define CLK_TOP_P0_1MHZ 13 36 #define CLK_TOP_TXCLK_SRC_PRE 14 37 #define CLK_TOP_RTC 15 38 #define CLK_TOP_MEMPLL 16 39 #define CLK_TOP_DMPLL 17 40 #define CLK_TOP_SYSPLL_D2 18 41 #define CLK_TOP_SYSPLL1_D2 19 42 #define CLK_TOP_SYSPLL1_D4 20 43 #define CLK_TOP_SYSPLL1_D8 21 44 #define CLK_TOP_SYSPLL2_D4 22 45 #define CLK_TOP_SYSPLL2_D8 23 46 #define CLK_TOP_SYSPLL_D5 24 47 #define CLK_TOP_SYSPLL3_D2 25 48 #define CLK_TOP_SYSPLL3_D4 26 49 #define CLK_TOP_SYSPLL4_D2 27 50 #define CLK_TOP_SYSPLL4_D4 28 51 #define CLK_TOP_SYSPLL4_D16 29 52 #define CLK_TOP_UNIVPLL 30 53 #define CLK_TOP_UNIVPLL_D2 31 54 #define CLK_TOP_UNIVPLL1_D2 32 55 #define CLK_TOP_UNIVPLL1_D4 33 56 #define CLK_TOP_UNIVPLL1_D8 34 57 #define CLK_TOP_UNIVPLL1_D16 35 58 #define CLK_TOP_UNIVPLL2_D2 36 59 #define CLK_TOP_UNIVPLL2_D4 37 60 #define CLK_TOP_UNIVPLL2_D8 38 61 #define CLK_TOP_UNIVPLL2_D16 39 62 #define CLK_TOP_UNIVPLL_D5 40 63 #define CLK_TOP_UNIVPLL3_D2 41 64 #define CLK_TOP_UNIVPLL3_D4 42 65 #define CLK_TOP_UNIVPLL3_D16 43 66 #define CLK_TOP_UNIVPLL_D7 44 67 #define CLK_TOP_UNIVPLL_D80_D4 45 68 #define CLK_TOP_UNIV48M 46 69 #define CLK_TOP_SGMIIPLL 47 70 #define CLK_TOP_SGMIIPLL_D2 48 71 #define CLK_TOP_AUD1PLL 49 72 #define CLK_TOP_AUD2PLL 50 73 #define CLK_TOP_AUD_I2S2_MCK 51 74 #define CLK_TOP_TO_USB3_REF 52 75 #define CLK_TOP_PCIE1_MAC_EN 53 76 #define CLK_TOP_PCIE0_MAC_EN 54 77 #define CLK_TOP_ETH_500M 55 78 #define CLK_TOP_AXI_SEL 56 79 #define CLK_TOP_MEM_SEL 57 80 #define CLK_TOP_DDRPHYCFG_SEL 58 81 #define CLK_TOP_ETH_SEL 59 82 #define CLK_TOP_PWM_SEL 60 83 #define CLK_TOP_F10M_REF_SEL 61 84 #define CLK_TOP_NFI_INFRA_SEL 62 85 #define CLK_TOP_FLASH_SEL 63 86 #define CLK_TOP_UART_SEL 64 87 #define CLK_TOP_SPI0_SEL 65 88 #define CLK_TOP_SPI1_SEL 66 89 #define CLK_TOP_MSDC50_0_SEL 67 90 #define CLK_TOP_MSDC30_0_SEL 68 91 #define CLK_TOP_MSDC30_1_SEL 69 92 #define CLK_TOP_A1SYS_HP_SEL 70 93 #define CLK_TOP_A2SYS_HP_SEL 71 94 #define CLK_TOP_INTDIR_SEL 72 95 #define CLK_TOP_AUD_INTBUS_SEL 73 96 #define CLK_TOP_PMICSPI_SEL 74 97 #define CLK_TOP_SCP_SEL 75 98 #define CLK_TOP_ATB_SEL 76 99 #define CLK_TOP_HIF_SEL 77 100 #define CLK_TOP_AUDIO_SEL 78 101 #define CLK_TOP_U2_SEL 79 102 #define CLK_TOP_AUD1_SEL 80 103 #define CLK_TOP_AUD2_SEL 81 104 #define CLK_TOP_IRRX_SEL 82 105 #define CLK_TOP_IRTX_SEL 83 106 #define CLK_TOP_ASM_L_SEL 84 107 #define CLK_TOP_ASM_M_SEL 85 108 #define CLK_TOP_ASM_H_SEL 86 109 #define CLK_TOP_APLL1_SEL 87 110 #define CLK_TOP_APLL2_SEL 88 111 #define CLK_TOP_I2S0_MCK_SEL 89 112 #define CLK_TOP_I2S1_MCK_SEL 90 113 #define CLK_TOP_I2S2_MCK_SEL 91 114 #define CLK_TOP_I2S3_MCK_SEL 92 115 #define CLK_TOP_APLL1_DIV 93 116 #define CLK_TOP_APLL2_DIV 94 117 #define CLK_TOP_I2S0_MCK_DIV 95 118 #define CLK_TOP_I2S1_MCK_DIV 96 119 #define CLK_TOP_I2S2_MCK_DIV 97 120 #define CLK_TOP_I2S3_MCK_DIV 98 121 #define CLK_TOP_A1SYS_HP_DIV 99 122 #define CLK_TOP_A2SYS_HP_DIV 100 123 #define CLK_TOP_APLL1_DIV_PD 101 124 #define CLK_TOP_APLL2_DIV_PD 102 125 #define CLK_TOP_I2S0_MCK_DIV_PD 103 126 #define CLK_TOP_I2S1_MCK_DIV_PD 104 127 #define CLK_TOP_I2S2_MCK_DIV_PD 105 128 #define CLK_TOP_I2S3_MCK_DIV_PD 106 129 #define CLK_TOP_A1SYS_HP_DIV_PD 107 130 #define CLK_TOP_A2SYS_HP_DIV_PD 108 131 #define CLK_TOP_NR_CLK 109 132 133 /* INFRACFG */ 134 135 #define CLK_INFRA_MUX1_SEL 0 136 #define CLK_INFRA_DBGCLK_PD 1 137 #define CLK_INFRA_AUDIO_PD 2 138 #define CLK_INFRA_IRRX_PD 3 139 #define CLK_INFRA_APXGPT_PD 4 140 #define CLK_INFRA_PMIC_PD 5 141 #define CLK_INFRA_TRNG 6 142 #define CLK_INFRA_NR_CLK 7 143 144 /* PERICFG */ 145 146 #define CLK_PERIBUS_SEL 0 147 #define CLK_PERI_THERM_PD 1 148 #define CLK_PERI_PWM1_PD 2 149 #define CLK_PERI_PWM2_PD 3 150 #define CLK_PERI_PWM3_PD 4 151 #define CLK_PERI_PWM4_PD 5 152 #define CLK_PERI_PWM5_PD 6 153 #define CLK_PERI_PWM6_PD 7 154 #define CLK_PERI_PWM7_PD 8 155 #define CLK_PERI_PWM_PD 9 156 #define CLK_PERI_AP_DMA_PD 10 157 #define CLK_PERI_MSDC30_0_PD 11 158 #define CLK_PERI_MSDC30_1_PD 12 159 #define CLK_PERI_UART0_PD 13 160 #define CLK_PERI_UART1_PD 14 161 #define CLK_PERI_UART2_PD 15 162 #define CLK_PERI_UART3_PD 16 163 #define CLK_PERI_UART4_PD 17 164 #define CLK_PERI_BTIF_PD 18 165 #define CLK_PERI_I2C0_PD 19 166 #define CLK_PERI_I2C1_PD 20 167 #define CLK_PERI_I2C2_PD 21 168 #define CLK_PERI_SPI1_PD 22 169 #define CLK_PERI_AUXADC_PD 23 170 #define CLK_PERI_SPI0_PD 24 171 #define CLK_PERI_SNFI_PD 25 172 #define CLK_PERI_NFI_PD 26 173 #define CLK_PERI_NFIECC_PD 27 174 #define CLK_PERI_FLASH_PD 28 175 #define CLK_PERI_IRTX_PD 29 176 #define CLK_PERI_NR_CLK 30 177 178 /* APMIXEDSYS */ 179 180 #define CLK_APMIXED_ARMPLL 0 181 #define CLK_APMIXED_MAINPLL 1 182 #define CLK_APMIXED_UNIV2PLL 2 183 #define CLK_APMIXED_ETH1PLL 3 184 #define CLK_APMIXED_ETH2PLL 4 185 #define CLK_APMIXED_AUD1PLL 5 186 #define CLK_APMIXED_AUD2PLL 6 187 #define CLK_APMIXED_TRGPLL 7 188 #define CLK_APMIXED_SGMIPLL 8 189 #define CLK_APMIXED_MAIN_CORE_EN 9 190 #define CLK_APMIXED_NR_CLK 10 191 192 /* AUDIOSYS */ 193 194 #define CLK_AUDIO_AFE 0 195 #define CLK_AUDIO_HDMI 1 196 #define CLK_AUDIO_SPDF 2 197 #define CLK_AUDIO_APLL 3 198 #define CLK_AUDIO_I2SIN1 4 199 #define CLK_AUDIO_I2SIN2 5 200 #define CLK_AUDIO_I2SIN3 6 201 #define CLK_AUDIO_I2SIN4 7 202 #define CLK_AUDIO_I2SO1 8 203 #define CLK_AUDIO_I2SO2 9 204 #define CLK_AUDIO_I2SO3 10 205 #define CLK_AUDIO_I2SO4 11 206 #define CLK_AUDIO_ASRCI1 12 207 #define CLK_AUDIO_ASRCI2 13 208 #define CLK_AUDIO_ASRCO1 14 209 #define CLK_AUDIO_ASRCO2 15 210 #define CLK_AUDIO_INTDIR 16 211 #define CLK_AUDIO_A1SYS 17 212 #define CLK_AUDIO_A2SYS 18 213 #define CLK_AUDIO_UL1 19 214 #define CLK_AUDIO_UL2 20 215 #define CLK_AUDIO_UL3 21 216 #define CLK_AUDIO_UL4 22 217 #define CLK_AUDIO_UL5 23 218 #define CLK_AUDIO_UL6 24 219 #define CLK_AUDIO_DL1 25 220 #define CLK_AUDIO_DL2 26 221 #define CLK_AUDIO_DL3 27 222 #define CLK_AUDIO_DL4 28 223 #define CLK_AUDIO_DL5 29 224 #define CLK_AUDIO_DL6 30 225 #define CLK_AUDIO_DLMCH 31 226 #define CLK_AUDIO_ARB1 32 227 #define CLK_AUDIO_AWB 33 228 #define CLK_AUDIO_AWB2 34 229 #define CLK_AUDIO_DAI 35 230 #define CLK_AUDIO_MOD 36 231 #define CLK_AUDIO_ASRCI3 37 232 #define CLK_AUDIO_ASRCI4 38 233 #define CLK_AUDIO_ASRCO3 39 234 #define CLK_AUDIO_ASRCO4 40 235 #define CLK_AUDIO_MEM_ASRC1 41 236 #define CLK_AUDIO_MEM_ASRC2 42 237 #define CLK_AUDIO_MEM_ASRC3 43 238 #define CLK_AUDIO_MEM_ASRC4 44 239 #define CLK_AUDIO_MEM_ASRC5 45 240 #define CLK_AUDIO_AFE_CONN 46 241 #define CLK_AUDIO_NR_CLK 47 242 243 /* SSUSBSYS */ 244 245 #define CLK_SSUSB_U2_PHY_1P_EN 0 246 #define CLK_SSUSB_U2_PHY_EN 1 247 #define CLK_SSUSB_REF_EN 2 248 #define CLK_SSUSB_SYS_EN 3 249 #define CLK_SSUSB_MCU_EN 4 250 #define CLK_SSUSB_DMA_EN 5 251 #define CLK_SSUSB_NR_CLK 6 252 253 /* PCIESYS */ 254 255 #define CLK_PCIE_P1_AUX_EN 0 256 #define CLK_PCIE_P1_OBFF_EN 1 257 #define CLK_PCIE_P1_AHB_EN 2 258 #define CLK_PCIE_P1_AXI_EN 3 259 #define CLK_PCIE_P1_MAC_EN 4 260 #define CLK_PCIE_P1_PIPE_EN 5 261 #define CLK_PCIE_P0_AUX_EN 6 262 #define CLK_PCIE_P0_OBFF_EN 7 263 #define CLK_PCIE_P0_AHB_EN 8 264 #define CLK_PCIE_P0_AXI_EN 9 265 #define CLK_PCIE_P0_MAC_EN 10 266 #define CLK_PCIE_P0_PIPE_EN 11 267 #define CLK_SATA_AHB_EN 12 268 #define CLK_SATA_AXI_EN 13 269 #define CLK_SATA_ASIC_EN 14 270 #define CLK_SATA_RBC_EN 15 271 #define CLK_SATA_PM_EN 16 272 #define CLK_PCIE_NR_CLK 17 273 274 /* ETHSYS */ 275 276 #define CLK_ETH_HSDMA_EN 0 277 #define CLK_ETH_ESW_EN 1 278 #define CLK_ETH_GP2_EN 2 279 #define CLK_ETH_GP1_EN 3 280 #define CLK_ETH_GP0_EN 4 281 #define CLK_ETH_NR_CLK 5 282 283 /* SGMIISYS */ 284 285 #define CLK_SGMII_TX250M_EN 0 286 #define CLK_SGMII_RX250M_EN 1 287 #define CLK_SGMII_CDR_REF 2 288 #define CLK_SGMII_CDR_FB 3 289 #define CLK_SGMII_NR_CLK 4 290 291 #endif /* _DT_BINDINGS_CLK_MT7622_H */ 292 293