1 /* $NetBSD: mt7622-clk.h,v 1.1.1.3 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-only */ 4 /* 5 * Copyright (c) 2017 MediaTek Inc. 6 * Author: Chen Zhong <chen.zhong@mediatek.com> 7 */ 8 9 #ifndef _DT_BINDINGS_CLK_MT7622_H 10 #define _DT_BINDINGS_CLK_MT7622_H 11 12 /* TOPCKGEN */ 13 14 #define CLK_TOP_TO_U2_PHY 0 15 #define CLK_TOP_TO_U2_PHY_1P 1 16 #define CLK_TOP_PCIE0_PIPE_EN 2 17 #define CLK_TOP_PCIE1_PIPE_EN 3 18 #define CLK_TOP_SSUSB_TX250M 4 19 #define CLK_TOP_SSUSB_EQ_RX250M 5 20 #define CLK_TOP_SSUSB_CDR_REF 6 21 #define CLK_TOP_SSUSB_CDR_FB 7 22 #define CLK_TOP_SATA_ASIC 8 23 #define CLK_TOP_SATA_RBC 9 24 #define CLK_TOP_TO_USB3_SYS 10 25 #define CLK_TOP_P1_1MHZ 11 26 #define CLK_TOP_4MHZ 12 27 #define CLK_TOP_P0_1MHZ 13 28 #define CLK_TOP_TXCLK_SRC_PRE 14 29 #define CLK_TOP_RTC 15 30 #define CLK_TOP_MEMPLL 16 31 #define CLK_TOP_DMPLL 17 32 #define CLK_TOP_SYSPLL_D2 18 33 #define CLK_TOP_SYSPLL1_D2 19 34 #define CLK_TOP_SYSPLL1_D4 20 35 #define CLK_TOP_SYSPLL1_D8 21 36 #define CLK_TOP_SYSPLL2_D4 22 37 #define CLK_TOP_SYSPLL2_D8 23 38 #define CLK_TOP_SYSPLL_D5 24 39 #define CLK_TOP_SYSPLL3_D2 25 40 #define CLK_TOP_SYSPLL3_D4 26 41 #define CLK_TOP_SYSPLL4_D2 27 42 #define CLK_TOP_SYSPLL4_D4 28 43 #define CLK_TOP_SYSPLL4_D16 29 44 #define CLK_TOP_UNIVPLL 30 45 #define CLK_TOP_UNIVPLL_D2 31 46 #define CLK_TOP_UNIVPLL1_D2 32 47 #define CLK_TOP_UNIVPLL1_D4 33 48 #define CLK_TOP_UNIVPLL1_D8 34 49 #define CLK_TOP_UNIVPLL1_D16 35 50 #define CLK_TOP_UNIVPLL2_D2 36 51 #define CLK_TOP_UNIVPLL2_D4 37 52 #define CLK_TOP_UNIVPLL2_D8 38 53 #define CLK_TOP_UNIVPLL2_D16 39 54 #define CLK_TOP_UNIVPLL_D5 40 55 #define CLK_TOP_UNIVPLL3_D2 41 56 #define CLK_TOP_UNIVPLL3_D4 42 57 #define CLK_TOP_UNIVPLL3_D16 43 58 #define CLK_TOP_UNIVPLL_D7 44 59 #define CLK_TOP_UNIVPLL_D80_D4 45 60 #define CLK_TOP_UNIV48M 46 61 #define CLK_TOP_SGMIIPLL 47 62 #define CLK_TOP_SGMIIPLL_D2 48 63 #define CLK_TOP_AUD1PLL 49 64 #define CLK_TOP_AUD2PLL 50 65 #define CLK_TOP_AUD_I2S2_MCK 51 66 #define CLK_TOP_TO_USB3_REF 52 67 #define CLK_TOP_PCIE1_MAC_EN 53 68 #define CLK_TOP_PCIE0_MAC_EN 54 69 #define CLK_TOP_ETH_500M 55 70 #define CLK_TOP_AXI_SEL 56 71 #define CLK_TOP_MEM_SEL 57 72 #define CLK_TOP_DDRPHYCFG_SEL 58 73 #define CLK_TOP_ETH_SEL 59 74 #define CLK_TOP_PWM_SEL 60 75 #define CLK_TOP_F10M_REF_SEL 61 76 #define CLK_TOP_NFI_INFRA_SEL 62 77 #define CLK_TOP_FLASH_SEL 63 78 #define CLK_TOP_UART_SEL 64 79 #define CLK_TOP_SPI0_SEL 65 80 #define CLK_TOP_SPI1_SEL 66 81 #define CLK_TOP_MSDC50_0_SEL 67 82 #define CLK_TOP_MSDC30_0_SEL 68 83 #define CLK_TOP_MSDC30_1_SEL 69 84 #define CLK_TOP_A1SYS_HP_SEL 70 85 #define CLK_TOP_A2SYS_HP_SEL 71 86 #define CLK_TOP_INTDIR_SEL 72 87 #define CLK_TOP_AUD_INTBUS_SEL 73 88 #define CLK_TOP_PMICSPI_SEL 74 89 #define CLK_TOP_SCP_SEL 75 90 #define CLK_TOP_ATB_SEL 76 91 #define CLK_TOP_HIF_SEL 77 92 #define CLK_TOP_AUDIO_SEL 78 93 #define CLK_TOP_U2_SEL 79 94 #define CLK_TOP_AUD1_SEL 80 95 #define CLK_TOP_AUD2_SEL 81 96 #define CLK_TOP_IRRX_SEL 82 97 #define CLK_TOP_IRTX_SEL 83 98 #define CLK_TOP_ASM_L_SEL 84 99 #define CLK_TOP_ASM_M_SEL 85 100 #define CLK_TOP_ASM_H_SEL 86 101 #define CLK_TOP_APLL1_SEL 87 102 #define CLK_TOP_APLL2_SEL 88 103 #define CLK_TOP_I2S0_MCK_SEL 89 104 #define CLK_TOP_I2S1_MCK_SEL 90 105 #define CLK_TOP_I2S2_MCK_SEL 91 106 #define CLK_TOP_I2S3_MCK_SEL 92 107 #define CLK_TOP_APLL1_DIV 93 108 #define CLK_TOP_APLL2_DIV 94 109 #define CLK_TOP_I2S0_MCK_DIV 95 110 #define CLK_TOP_I2S1_MCK_DIV 96 111 #define CLK_TOP_I2S2_MCK_DIV 97 112 #define CLK_TOP_I2S3_MCK_DIV 98 113 #define CLK_TOP_A1SYS_HP_DIV 99 114 #define CLK_TOP_A2SYS_HP_DIV 100 115 #define CLK_TOP_APLL1_DIV_PD 101 116 #define CLK_TOP_APLL2_DIV_PD 102 117 #define CLK_TOP_I2S0_MCK_DIV_PD 103 118 #define CLK_TOP_I2S1_MCK_DIV_PD 104 119 #define CLK_TOP_I2S2_MCK_DIV_PD 105 120 #define CLK_TOP_I2S3_MCK_DIV_PD 106 121 #define CLK_TOP_A1SYS_HP_DIV_PD 107 122 #define CLK_TOP_A2SYS_HP_DIV_PD 108 123 #define CLK_TOP_NR_CLK 109 124 125 /* INFRACFG */ 126 127 #define CLK_INFRA_MUX1_SEL 0 128 #define CLK_INFRA_DBGCLK_PD 1 129 #define CLK_INFRA_AUDIO_PD 2 130 #define CLK_INFRA_IRRX_PD 3 131 #define CLK_INFRA_APXGPT_PD 4 132 #define CLK_INFRA_PMIC_PD 5 133 #define CLK_INFRA_TRNG 6 134 #define CLK_INFRA_NR_CLK 7 135 136 /* PERICFG */ 137 138 #define CLK_PERIBUS_SEL 0 139 #define CLK_PERI_THERM_PD 1 140 #define CLK_PERI_PWM1_PD 2 141 #define CLK_PERI_PWM2_PD 3 142 #define CLK_PERI_PWM3_PD 4 143 #define CLK_PERI_PWM4_PD 5 144 #define CLK_PERI_PWM5_PD 6 145 #define CLK_PERI_PWM6_PD 7 146 #define CLK_PERI_PWM7_PD 8 147 #define CLK_PERI_PWM_PD 9 148 #define CLK_PERI_AP_DMA_PD 10 149 #define CLK_PERI_MSDC30_0_PD 11 150 #define CLK_PERI_MSDC30_1_PD 12 151 #define CLK_PERI_UART0_PD 13 152 #define CLK_PERI_UART1_PD 14 153 #define CLK_PERI_UART2_PD 15 154 #define CLK_PERI_UART3_PD 16 155 #define CLK_PERI_UART4_PD 17 156 #define CLK_PERI_BTIF_PD 18 157 #define CLK_PERI_I2C0_PD 19 158 #define CLK_PERI_I2C1_PD 20 159 #define CLK_PERI_I2C2_PD 21 160 #define CLK_PERI_SPI1_PD 22 161 #define CLK_PERI_AUXADC_PD 23 162 #define CLK_PERI_SPI0_PD 24 163 #define CLK_PERI_SNFI_PD 25 164 #define CLK_PERI_NFI_PD 26 165 #define CLK_PERI_NFIECC_PD 27 166 #define CLK_PERI_FLASH_PD 28 167 #define CLK_PERI_IRTX_PD 29 168 #define CLK_PERI_NR_CLK 30 169 170 /* APMIXEDSYS */ 171 172 #define CLK_APMIXED_ARMPLL 0 173 #define CLK_APMIXED_MAINPLL 1 174 #define CLK_APMIXED_UNIV2PLL 2 175 #define CLK_APMIXED_ETH1PLL 3 176 #define CLK_APMIXED_ETH2PLL 4 177 #define CLK_APMIXED_AUD1PLL 5 178 #define CLK_APMIXED_AUD2PLL 6 179 #define CLK_APMIXED_TRGPLL 7 180 #define CLK_APMIXED_SGMIPLL 8 181 #define CLK_APMIXED_MAIN_CORE_EN 9 182 #define CLK_APMIXED_NR_CLK 10 183 184 /* AUDIOSYS */ 185 186 #define CLK_AUDIO_AFE 0 187 #define CLK_AUDIO_HDMI 1 188 #define CLK_AUDIO_SPDF 2 189 #define CLK_AUDIO_APLL 3 190 #define CLK_AUDIO_I2SIN1 4 191 #define CLK_AUDIO_I2SIN2 5 192 #define CLK_AUDIO_I2SIN3 6 193 #define CLK_AUDIO_I2SIN4 7 194 #define CLK_AUDIO_I2SO1 8 195 #define CLK_AUDIO_I2SO2 9 196 #define CLK_AUDIO_I2SO3 10 197 #define CLK_AUDIO_I2SO4 11 198 #define CLK_AUDIO_ASRCI1 12 199 #define CLK_AUDIO_ASRCI2 13 200 #define CLK_AUDIO_ASRCO1 14 201 #define CLK_AUDIO_ASRCO2 15 202 #define CLK_AUDIO_INTDIR 16 203 #define CLK_AUDIO_A1SYS 17 204 #define CLK_AUDIO_A2SYS 18 205 #define CLK_AUDIO_UL1 19 206 #define CLK_AUDIO_UL2 20 207 #define CLK_AUDIO_UL3 21 208 #define CLK_AUDIO_UL4 22 209 #define CLK_AUDIO_UL5 23 210 #define CLK_AUDIO_UL6 24 211 #define CLK_AUDIO_DL1 25 212 #define CLK_AUDIO_DL2 26 213 #define CLK_AUDIO_DL3 27 214 #define CLK_AUDIO_DL4 28 215 #define CLK_AUDIO_DL5 29 216 #define CLK_AUDIO_DL6 30 217 #define CLK_AUDIO_DLMCH 31 218 #define CLK_AUDIO_ARB1 32 219 #define CLK_AUDIO_AWB 33 220 #define CLK_AUDIO_AWB2 34 221 #define CLK_AUDIO_DAI 35 222 #define CLK_AUDIO_MOD 36 223 #define CLK_AUDIO_ASRCI3 37 224 #define CLK_AUDIO_ASRCI4 38 225 #define CLK_AUDIO_ASRCO3 39 226 #define CLK_AUDIO_ASRCO4 40 227 #define CLK_AUDIO_MEM_ASRC1 41 228 #define CLK_AUDIO_MEM_ASRC2 42 229 #define CLK_AUDIO_MEM_ASRC3 43 230 #define CLK_AUDIO_MEM_ASRC4 44 231 #define CLK_AUDIO_MEM_ASRC5 45 232 #define CLK_AUDIO_AFE_CONN 46 233 #define CLK_AUDIO_NR_CLK 47 234 235 /* SSUSBSYS */ 236 237 #define CLK_SSUSB_U2_PHY_1P_EN 0 238 #define CLK_SSUSB_U2_PHY_EN 1 239 #define CLK_SSUSB_REF_EN 2 240 #define CLK_SSUSB_SYS_EN 3 241 #define CLK_SSUSB_MCU_EN 4 242 #define CLK_SSUSB_DMA_EN 5 243 #define CLK_SSUSB_NR_CLK 6 244 245 /* PCIESYS */ 246 247 #define CLK_PCIE_P1_AUX_EN 0 248 #define CLK_PCIE_P1_OBFF_EN 1 249 #define CLK_PCIE_P1_AHB_EN 2 250 #define CLK_PCIE_P1_AXI_EN 3 251 #define CLK_PCIE_P1_MAC_EN 4 252 #define CLK_PCIE_P1_PIPE_EN 5 253 #define CLK_PCIE_P0_AUX_EN 6 254 #define CLK_PCIE_P0_OBFF_EN 7 255 #define CLK_PCIE_P0_AHB_EN 8 256 #define CLK_PCIE_P0_AXI_EN 9 257 #define CLK_PCIE_P0_MAC_EN 10 258 #define CLK_PCIE_P0_PIPE_EN 11 259 #define CLK_SATA_AHB_EN 12 260 #define CLK_SATA_AXI_EN 13 261 #define CLK_SATA_ASIC_EN 14 262 #define CLK_SATA_RBC_EN 15 263 #define CLK_SATA_PM_EN 16 264 #define CLK_PCIE_NR_CLK 17 265 266 /* ETHSYS */ 267 268 #define CLK_ETH_HSDMA_EN 0 269 #define CLK_ETH_ESW_EN 1 270 #define CLK_ETH_GP2_EN 2 271 #define CLK_ETH_GP1_EN 3 272 #define CLK_ETH_GP0_EN 4 273 #define CLK_ETH_NR_CLK 5 274 275 /* SGMIISYS */ 276 277 #define CLK_SGMII_TX250M_EN 0 278 #define CLK_SGMII_RX250M_EN 1 279 #define CLK_SGMII_CDR_REF 2 280 #define CLK_SGMII_CDR_FB 3 281 #define CLK_SGMII_NR_CLK 4 282 283 #endif /* _DT_BINDINGS_CLK_MT7622_H */ 284 285