1 /* $NetBSD: k210-clk.h,v 1.1.1.1 2021/11/07 16:49:59 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (C) 2019-20 Sean Anderson <seanga2@gmail.com> 6 * Copyright (c) 2020 Western Digital Corporation or its affiliates. 7 */ 8 #ifndef CLOCK_K210_CLK_H 9 #define CLOCK_K210_CLK_H 10 11 /* 12 * Kendryte K210 SoC clock identifiers (arbitrary values). 13 */ 14 #define K210_CLK_CPU 0 15 #define K210_CLK_SRAM0 1 16 #define K210_CLK_SRAM1 2 17 #define K210_CLK_AI 3 18 #define K210_CLK_DMA 4 19 #define K210_CLK_FFT 5 20 #define K210_CLK_ROM 6 21 #define K210_CLK_DVP 7 22 #define K210_CLK_APB0 8 23 #define K210_CLK_APB1 9 24 #define K210_CLK_APB2 10 25 #define K210_CLK_I2S0 11 26 #define K210_CLK_I2S1 12 27 #define K210_CLK_I2S2 13 28 #define K210_CLK_I2S0_M 14 29 #define K210_CLK_I2S1_M 15 30 #define K210_CLK_I2S2_M 16 31 #define K210_CLK_WDT0 17 32 #define K210_CLK_WDT1 18 33 #define K210_CLK_SPI0 19 34 #define K210_CLK_SPI1 20 35 #define K210_CLK_SPI2 21 36 #define K210_CLK_I2C0 22 37 #define K210_CLK_I2C1 23 38 #define K210_CLK_I2C2 24 39 #define K210_CLK_SPI3 25 40 #define K210_CLK_TIMER0 26 41 #define K210_CLK_TIMER1 27 42 #define K210_CLK_TIMER2 28 43 #define K210_CLK_GPIO 29 44 #define K210_CLK_UART1 30 45 #define K210_CLK_UART2 31 46 #define K210_CLK_UART3 32 47 #define K210_CLK_FPIOA 33 48 #define K210_CLK_SHA 34 49 #define K210_CLK_AES 35 50 #define K210_CLK_OTP 36 51 #define K210_CLK_RTC 37 52 53 #define K210_NUM_CLKS 38 54 55 #endif /* CLOCK_K210_CLK_H */ 56