1 /* $NetBSD: jz4740-cgu.h,v 1.1.1.3 2020/01/03 14:33:06 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * This header provides clock numbers for the ingenic,jz4740-cgu DT binding. 6 * 7 * They are roughly ordered as: 8 * - external clocks 9 * - PLLs 10 * - muxes/dividers in the order they appear in the jz4740 programmers manual 11 * - gates in order of their bit in the CLKGR* registers 12 */ 13 14 #ifndef __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 15 #define __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ 16 17 #define JZ4740_CLK_EXT 0 18 #define JZ4740_CLK_RTC 1 19 #define JZ4740_CLK_PLL 2 20 #define JZ4740_CLK_PLL_HALF 3 21 #define JZ4740_CLK_CCLK 4 22 #define JZ4740_CLK_HCLK 5 23 #define JZ4740_CLK_PCLK 6 24 #define JZ4740_CLK_MCLK 7 25 #define JZ4740_CLK_LCD 8 26 #define JZ4740_CLK_LCD_PCLK 9 27 #define JZ4740_CLK_I2S 10 28 #define JZ4740_CLK_SPI 11 29 #define JZ4740_CLK_MMC 12 30 #define JZ4740_CLK_UHC 13 31 #define JZ4740_CLK_UDC 14 32 #define JZ4740_CLK_UART0 15 33 #define JZ4740_CLK_UART1 16 34 #define JZ4740_CLK_DMA 17 35 #define JZ4740_CLK_IPU 18 36 #define JZ4740_CLK_ADC 19 37 #define JZ4740_CLK_I2C 20 38 #define JZ4740_CLK_AIC 21 39 #define JZ4740_CLK_TCU 22 40 41 #endif /* __DT_BINDINGS_CLOCK_JZ4740_CGU_H__ */ 42