1 /* $NetBSD: imx7ulp-clock.h,v 1.1.1.3 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0+ */ 4 /* 5 * Copyright (C) 2016 Freescale Semiconductor, Inc. 6 * Copyright 2017~2018 NXP 7 * 8 */ 9 10 #ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H 11 #define __DT_BINDINGS_CLOCK_IMX7ULP_H 12 13 /* SCG1 */ 14 15 #define IMX7ULP_CLK_DUMMY 0 16 #define IMX7ULP_CLK_ROSC 1 17 #define IMX7ULP_CLK_SOSC 2 18 #define IMX7ULP_CLK_FIRC 3 19 #define IMX7ULP_CLK_SPLL_PRE_SEL 4 20 #define IMX7ULP_CLK_SPLL_PRE_DIV 5 21 #define IMX7ULP_CLK_SPLL 6 22 #define IMX7ULP_CLK_SPLL_POST_DIV1 7 23 #define IMX7ULP_CLK_SPLL_POST_DIV2 8 24 #define IMX7ULP_CLK_SPLL_PFD0 9 25 #define IMX7ULP_CLK_SPLL_PFD1 10 26 #define IMX7ULP_CLK_SPLL_PFD2 11 27 #define IMX7ULP_CLK_SPLL_PFD3 12 28 #define IMX7ULP_CLK_SPLL_PFD_SEL 13 29 #define IMX7ULP_CLK_SPLL_SEL 14 30 #define IMX7ULP_CLK_APLL_PRE_SEL 15 31 #define IMX7ULP_CLK_APLL_PRE_DIV 16 32 #define IMX7ULP_CLK_APLL 17 33 #define IMX7ULP_CLK_APLL_POST_DIV1 18 34 #define IMX7ULP_CLK_APLL_POST_DIV2 19 35 #define IMX7ULP_CLK_APLL_PFD0 20 36 #define IMX7ULP_CLK_APLL_PFD1 21 37 #define IMX7ULP_CLK_APLL_PFD2 22 38 #define IMX7ULP_CLK_APLL_PFD3 23 39 #define IMX7ULP_CLK_APLL_PFD_SEL 24 40 #define IMX7ULP_CLK_APLL_SEL 25 41 #define IMX7ULP_CLK_UPLL 26 42 #define IMX7ULP_CLK_SYS_SEL 27 43 #define IMX7ULP_CLK_CORE_DIV 28 44 #define IMX7ULP_CLK_BUS_DIV 29 45 #define IMX7ULP_CLK_PLAT_DIV 30 46 #define IMX7ULP_CLK_DDR_SEL 31 47 #define IMX7ULP_CLK_DDR_DIV 32 48 #define IMX7ULP_CLK_NIC_SEL 33 49 #define IMX7ULP_CLK_NIC0_DIV 34 50 #define IMX7ULP_CLK_GPU_DIV 35 51 #define IMX7ULP_CLK_NIC1_DIV 36 52 #define IMX7ULP_CLK_NIC1_BUS_DIV 37 53 #define IMX7ULP_CLK_NIC1_EXT_DIV 38 54 /* IMX7ULP_CLK_MIPI_PLL is unsupported and shouldn't be used in DT */ 55 #define IMX7ULP_CLK_MIPI_PLL 39 56 #define IMX7ULP_CLK_SIRC 40 57 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 58 #define IMX7ULP_CLK_FIRC_BUS_CLK 42 59 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 60 #define IMX7ULP_CLK_HSRUN_SYS_SEL 44 61 #define IMX7ULP_CLK_HSRUN_CORE_DIV 45 62 63 #define IMX7ULP_CLK_CORE 46 64 #define IMX7ULP_CLK_HSRUN_CORE 47 65 66 #define IMX7ULP_CLK_SCG1_END 48 67 68 /* PCC2 */ 69 #define IMX7ULP_CLK_DMA1 0 70 #define IMX7ULP_CLK_RGPIO2P1 1 71 #define IMX7ULP_CLK_FLEXBUS 2 72 #define IMX7ULP_CLK_SEMA42_1 3 73 #define IMX7ULP_CLK_DMA_MUX1 4 74 #define IMX7ULP_CLK_CAAM 6 75 #define IMX7ULP_CLK_LPTPM4 7 76 #define IMX7ULP_CLK_LPTPM5 8 77 #define IMX7ULP_CLK_LPIT1 9 78 #define IMX7ULP_CLK_LPSPI2 10 79 #define IMX7ULP_CLK_LPSPI3 11 80 #define IMX7ULP_CLK_LPI2C4 12 81 #define IMX7ULP_CLK_LPI2C5 13 82 #define IMX7ULP_CLK_LPUART4 14 83 #define IMX7ULP_CLK_LPUART5 15 84 #define IMX7ULP_CLK_FLEXIO1 16 85 #define IMX7ULP_CLK_USB0 17 86 #define IMX7ULP_CLK_USB1 18 87 #define IMX7ULP_CLK_USB_PHY 19 88 #define IMX7ULP_CLK_USB_PL301 20 89 #define IMX7ULP_CLK_USDHC0 21 90 #define IMX7ULP_CLK_USDHC1 22 91 #define IMX7ULP_CLK_WDG1 23 92 #define IMX7ULP_CLK_WDG2 24 93 94 #define IMX7ULP_CLK_PCC2_END 25 95 96 /* PCC3 */ 97 #define IMX7ULP_CLK_LPTPM6 0 98 #define IMX7ULP_CLK_LPTPM7 1 99 #define IMX7ULP_CLK_LPI2C6 2 100 #define IMX7ULP_CLK_LPI2C7 3 101 #define IMX7ULP_CLK_LPUART6 4 102 #define IMX7ULP_CLK_LPUART7 5 103 #define IMX7ULP_CLK_VIU 6 104 #define IMX7ULP_CLK_DSI 7 105 #define IMX7ULP_CLK_LCDIF 8 106 #define IMX7ULP_CLK_MMDC 9 107 #define IMX7ULP_CLK_PCTLC 10 108 #define IMX7ULP_CLK_PCTLD 11 109 #define IMX7ULP_CLK_PCTLE 12 110 #define IMX7ULP_CLK_PCTLF 13 111 #define IMX7ULP_CLK_GPU3D 14 112 #define IMX7ULP_CLK_GPU2D 15 113 114 #define IMX7ULP_CLK_PCC3_END 16 115 116 /* SMC1 */ 117 #define IMX7ULP_CLK_ARM 0 118 119 #define IMX7ULP_CLK_SMC1_END 1 120 121 #endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */ 122