1 /* $NetBSD: hi3620-clock.h,v 1.1.1.1 2017/06/15 20:14:23 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2012-2013 Hisilicon Limited. 5 * Copyright (c) 2012-2013 Linaro Limited. 6 * 7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 8 * Xin Li <li.xin@linaro.org> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 * GNU General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, write to the Free Software Foundation, Inc., 22 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 23 * 24 */ 25 26 #ifndef __DTS_HI3620_CLOCK_H 27 #define __DTS_HI3620_CLOCK_H 28 29 #define HI3620_NONE_CLOCK 0 30 31 /* fixed rate & fixed factor clocks */ 32 #define HI3620_OSC32K 1 33 #define HI3620_OSC26M 2 34 #define HI3620_PCLK 3 35 #define HI3620_PLL_ARM0 4 36 #define HI3620_PLL_ARM1 5 37 #define HI3620_PLL_PERI 6 38 #define HI3620_PLL_USB 7 39 #define HI3620_PLL_HDMI 8 40 #define HI3620_PLL_GPU 9 41 #define HI3620_RCLK_TCXO 10 42 #define HI3620_RCLK_CFGAXI 11 43 #define HI3620_RCLK_PICO 12 44 45 /* mux clocks */ 46 #define HI3620_TIMER0_MUX 32 47 #define HI3620_TIMER1_MUX 33 48 #define HI3620_TIMER2_MUX 34 49 #define HI3620_TIMER3_MUX 35 50 #define HI3620_TIMER4_MUX 36 51 #define HI3620_TIMER5_MUX 37 52 #define HI3620_TIMER6_MUX 38 53 #define HI3620_TIMER7_MUX 39 54 #define HI3620_TIMER8_MUX 40 55 #define HI3620_TIMER9_MUX 41 56 #define HI3620_UART0_MUX 42 57 #define HI3620_UART1_MUX 43 58 #define HI3620_UART2_MUX 44 59 #define HI3620_UART3_MUX 45 60 #define HI3620_UART4_MUX 46 61 #define HI3620_SPI0_MUX 47 62 #define HI3620_SPI1_MUX 48 63 #define HI3620_SPI2_MUX 49 64 #define HI3620_SAXI_MUX 50 65 #define HI3620_PWM0_MUX 51 66 #define HI3620_PWM1_MUX 52 67 #define HI3620_SD_MUX 53 68 #define HI3620_MMC1_MUX 54 69 #define HI3620_MMC1_MUX2 55 70 #define HI3620_G2D_MUX 56 71 #define HI3620_VENC_MUX 57 72 #define HI3620_VDEC_MUX 58 73 #define HI3620_VPP_MUX 59 74 #define HI3620_EDC0_MUX 60 75 #define HI3620_LDI0_MUX 61 76 #define HI3620_EDC1_MUX 62 77 #define HI3620_LDI1_MUX 63 78 #define HI3620_RCLK_HSIC 64 79 #define HI3620_MMC2_MUX 65 80 #define HI3620_MMC3_MUX 66 81 82 /* divider clocks */ 83 #define HI3620_SHAREAXI_DIV 128 84 #define HI3620_CFGAXI_DIV 129 85 #define HI3620_SD_DIV 130 86 #define HI3620_MMC1_DIV 131 87 #define HI3620_HSIC_DIV 132 88 #define HI3620_MMC2_DIV 133 89 #define HI3620_MMC3_DIV 134 90 91 /* gate clocks */ 92 #define HI3620_TIMERCLK01 160 93 #define HI3620_TIMER_RCLK01 161 94 #define HI3620_TIMERCLK23 162 95 #define HI3620_TIMER_RCLK23 163 96 #define HI3620_TIMERCLK45 164 97 #define HI3620_TIMERCLK67 165 98 #define HI3620_TIMERCLK89 166 99 #define HI3620_RTCCLK 167 100 #define HI3620_KPC_CLK 168 101 #define HI3620_GPIOCLK0 169 102 #define HI3620_GPIOCLK1 170 103 #define HI3620_GPIOCLK2 171 104 #define HI3620_GPIOCLK3 172 105 #define HI3620_GPIOCLK4 173 106 #define HI3620_GPIOCLK5 174 107 #define HI3620_GPIOCLK6 175 108 #define HI3620_GPIOCLK7 176 109 #define HI3620_GPIOCLK8 177 110 #define HI3620_GPIOCLK9 178 111 #define HI3620_GPIOCLK10 179 112 #define HI3620_GPIOCLK11 180 113 #define HI3620_GPIOCLK12 181 114 #define HI3620_GPIOCLK13 182 115 #define HI3620_GPIOCLK14 183 116 #define HI3620_GPIOCLK15 184 117 #define HI3620_GPIOCLK16 185 118 #define HI3620_GPIOCLK17 186 119 #define HI3620_GPIOCLK18 187 120 #define HI3620_GPIOCLK19 188 121 #define HI3620_GPIOCLK20 189 122 #define HI3620_GPIOCLK21 190 123 #define HI3620_DPHY0_CLK 191 124 #define HI3620_DPHY1_CLK 192 125 #define HI3620_DPHY2_CLK 193 126 #define HI3620_USBPHY_CLK 194 127 #define HI3620_ACP_CLK 195 128 #define HI3620_PWMCLK0 196 129 #define HI3620_PWMCLK1 197 130 #define HI3620_UARTCLK0 198 131 #define HI3620_UARTCLK1 199 132 #define HI3620_UARTCLK2 200 133 #define HI3620_UARTCLK3 201 134 #define HI3620_UARTCLK4 202 135 #define HI3620_SPICLK0 203 136 #define HI3620_SPICLK1 204 137 #define HI3620_SPICLK2 205 138 #define HI3620_I2CCLK0 206 139 #define HI3620_I2CCLK1 207 140 #define HI3620_I2CCLK2 208 141 #define HI3620_I2CCLK3 209 142 #define HI3620_SCI_CLK 210 143 #define HI3620_DDRC_PER_CLK 211 144 #define HI3620_DMAC_CLK 212 145 #define HI3620_USB2DVC_CLK 213 146 #define HI3620_SD_CLK 214 147 #define HI3620_MMC_CLK1 215 148 #define HI3620_MMC_CLK2 216 149 #define HI3620_MMC_CLK3 217 150 #define HI3620_MCU_CLK 218 151 152 #define HI3620_SD_CIUCLK 0 153 #define HI3620_MMC_CIUCLK1 1 154 #define HI3620_MMC_CIUCLK2 2 155 #define HI3620_MMC_CIUCLK3 3 156 157 #define HI3620_NR_CLKS 219 158 159 #endif /* __DTS_HI3620_CLOCK_H */ 160