1 /* $NetBSD: hi3620-clock.h,v 1.1.1.2 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2012-2013 Hisilicon Limited. 6 * Copyright (c) 2012-2013 Linaro Limited. 7 * 8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> 9 * Xin Li <li.xin@linaro.org> 10 */ 11 12 #ifndef __DTS_HI3620_CLOCK_H 13 #define __DTS_HI3620_CLOCK_H 14 15 #define HI3620_NONE_CLOCK 0 16 17 /* fixed rate & fixed factor clocks */ 18 #define HI3620_OSC32K 1 19 #define HI3620_OSC26M 2 20 #define HI3620_PCLK 3 21 #define HI3620_PLL_ARM0 4 22 #define HI3620_PLL_ARM1 5 23 #define HI3620_PLL_PERI 6 24 #define HI3620_PLL_USB 7 25 #define HI3620_PLL_HDMI 8 26 #define HI3620_PLL_GPU 9 27 #define HI3620_RCLK_TCXO 10 28 #define HI3620_RCLK_CFGAXI 11 29 #define HI3620_RCLK_PICO 12 30 31 /* mux clocks */ 32 #define HI3620_TIMER0_MUX 32 33 #define HI3620_TIMER1_MUX 33 34 #define HI3620_TIMER2_MUX 34 35 #define HI3620_TIMER3_MUX 35 36 #define HI3620_TIMER4_MUX 36 37 #define HI3620_TIMER5_MUX 37 38 #define HI3620_TIMER6_MUX 38 39 #define HI3620_TIMER7_MUX 39 40 #define HI3620_TIMER8_MUX 40 41 #define HI3620_TIMER9_MUX 41 42 #define HI3620_UART0_MUX 42 43 #define HI3620_UART1_MUX 43 44 #define HI3620_UART2_MUX 44 45 #define HI3620_UART3_MUX 45 46 #define HI3620_UART4_MUX 46 47 #define HI3620_SPI0_MUX 47 48 #define HI3620_SPI1_MUX 48 49 #define HI3620_SPI2_MUX 49 50 #define HI3620_SAXI_MUX 50 51 #define HI3620_PWM0_MUX 51 52 #define HI3620_PWM1_MUX 52 53 #define HI3620_SD_MUX 53 54 #define HI3620_MMC1_MUX 54 55 #define HI3620_MMC1_MUX2 55 56 #define HI3620_G2D_MUX 56 57 #define HI3620_VENC_MUX 57 58 #define HI3620_VDEC_MUX 58 59 #define HI3620_VPP_MUX 59 60 #define HI3620_EDC0_MUX 60 61 #define HI3620_LDI0_MUX 61 62 #define HI3620_EDC1_MUX 62 63 #define HI3620_LDI1_MUX 63 64 #define HI3620_RCLK_HSIC 64 65 #define HI3620_MMC2_MUX 65 66 #define HI3620_MMC3_MUX 66 67 68 /* divider clocks */ 69 #define HI3620_SHAREAXI_DIV 128 70 #define HI3620_CFGAXI_DIV 129 71 #define HI3620_SD_DIV 130 72 #define HI3620_MMC1_DIV 131 73 #define HI3620_HSIC_DIV 132 74 #define HI3620_MMC2_DIV 133 75 #define HI3620_MMC3_DIV 134 76 77 /* gate clocks */ 78 #define HI3620_TIMERCLK01 160 79 #define HI3620_TIMER_RCLK01 161 80 #define HI3620_TIMERCLK23 162 81 #define HI3620_TIMER_RCLK23 163 82 #define HI3620_TIMERCLK45 164 83 #define HI3620_TIMERCLK67 165 84 #define HI3620_TIMERCLK89 166 85 #define HI3620_RTCCLK 167 86 #define HI3620_KPC_CLK 168 87 #define HI3620_GPIOCLK0 169 88 #define HI3620_GPIOCLK1 170 89 #define HI3620_GPIOCLK2 171 90 #define HI3620_GPIOCLK3 172 91 #define HI3620_GPIOCLK4 173 92 #define HI3620_GPIOCLK5 174 93 #define HI3620_GPIOCLK6 175 94 #define HI3620_GPIOCLK7 176 95 #define HI3620_GPIOCLK8 177 96 #define HI3620_GPIOCLK9 178 97 #define HI3620_GPIOCLK10 179 98 #define HI3620_GPIOCLK11 180 99 #define HI3620_GPIOCLK12 181 100 #define HI3620_GPIOCLK13 182 101 #define HI3620_GPIOCLK14 183 102 #define HI3620_GPIOCLK15 184 103 #define HI3620_GPIOCLK16 185 104 #define HI3620_GPIOCLK17 186 105 #define HI3620_GPIOCLK18 187 106 #define HI3620_GPIOCLK19 188 107 #define HI3620_GPIOCLK20 189 108 #define HI3620_GPIOCLK21 190 109 #define HI3620_DPHY0_CLK 191 110 #define HI3620_DPHY1_CLK 192 111 #define HI3620_DPHY2_CLK 193 112 #define HI3620_USBPHY_CLK 194 113 #define HI3620_ACP_CLK 195 114 #define HI3620_PWMCLK0 196 115 #define HI3620_PWMCLK1 197 116 #define HI3620_UARTCLK0 198 117 #define HI3620_UARTCLK1 199 118 #define HI3620_UARTCLK2 200 119 #define HI3620_UARTCLK3 201 120 #define HI3620_UARTCLK4 202 121 #define HI3620_SPICLK0 203 122 #define HI3620_SPICLK1 204 123 #define HI3620_SPICLK2 205 124 #define HI3620_I2CCLK0 206 125 #define HI3620_I2CCLK1 207 126 #define HI3620_I2CCLK2 208 127 #define HI3620_I2CCLK3 209 128 #define HI3620_SCI_CLK 210 129 #define HI3620_DDRC_PER_CLK 211 130 #define HI3620_DMAC_CLK 212 131 #define HI3620_USB2DVC_CLK 213 132 #define HI3620_SD_CLK 214 133 #define HI3620_MMC_CLK1 215 134 #define HI3620_MMC_CLK2 216 135 #define HI3620_MMC_CLK3 217 136 #define HI3620_MCU_CLK 218 137 138 #define HI3620_SD_CIUCLK 0 139 #define HI3620_MMC_CIUCLK1 1 140 #define HI3620_MMC_CIUCLK2 2 141 #define HI3620_MMC_CIUCLK3 3 142 143 #define HI3620_NR_CLKS 219 144 145 #endif /* __DTS_HI3620_CLOCK_H */ 146