1 /* $NetBSD: hi3516cv300-clock.h,v 1.1.1.2 2020/01/03 14:33:04 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later */ 4 /* 5 * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. 6 */ 7 8 #ifndef __DTS_HI3516CV300_CLOCK_H 9 #define __DTS_HI3516CV300_CLOCK_H 10 11 /* hi3516CV300 core CRG */ 12 #define HI3516CV300_APB_CLK 0 13 #define HI3516CV300_UART0_CLK 1 14 #define HI3516CV300_UART1_CLK 2 15 #define HI3516CV300_UART2_CLK 3 16 #define HI3516CV300_SPI0_CLK 4 17 #define HI3516CV300_SPI1_CLK 5 18 #define HI3516CV300_FMC_CLK 6 19 #define HI3516CV300_MMC0_CLK 7 20 #define HI3516CV300_MMC1_CLK 8 21 #define HI3516CV300_MMC2_CLK 9 22 #define HI3516CV300_MMC3_CLK 10 23 #define HI3516CV300_ETH_CLK 11 24 #define HI3516CV300_ETH_MACIF_CLK 12 25 #define HI3516CV300_DMAC_CLK 13 26 #define HI3516CV300_PWM_CLK 14 27 #define HI3516CV300_USB2_BUS_CLK 15 28 #define HI3516CV300_USB2_OHCI48M_CLK 16 29 #define HI3516CV300_USB2_OHCI12M_CLK 17 30 #define HI3516CV300_USB2_OTG_UTMI_CLK 18 31 #define HI3516CV300_USB2_HST_PHY_CLK 19 32 #define HI3516CV300_USB2_UTMI0_CLK 20 33 #define HI3516CV300_USB2_PHY_CLK 21 34 35 /* hi3516CV300 sysctrl CRG */ 36 #define HI3516CV300_WDT_CLK 1 37 38 #endif /* __DTS_HI3516CV300_CLOCK_H */ 39