1 /* $NetBSD: ast2600-clock.h,v 1.1.1.1 2020/01/03 14:33:05 skrll Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ 4 #ifndef DT_BINDINGS_AST2600_CLOCK_H 5 #define DT_BINDINGS_AST2600_CLOCK_H 6 7 #define ASPEED_CLK_GATE_ECLK 0 8 #define ASPEED_CLK_GATE_GCLK 1 9 10 #define ASPEED_CLK_GATE_MCLK 2 11 12 #define ASPEED_CLK_GATE_VCLK 3 13 #define ASPEED_CLK_GATE_BCLK 4 14 #define ASPEED_CLK_GATE_DCLK 5 15 16 #define ASPEED_CLK_GATE_LCLK 6 17 #define ASPEED_CLK_GATE_LHCCLK 7 18 19 #define ASPEED_CLK_GATE_D1CLK 8 20 #define ASPEED_CLK_GATE_YCLK 9 21 22 #define ASPEED_CLK_GATE_REF0CLK 10 23 #define ASPEED_CLK_GATE_REF1CLK 11 24 25 #define ASPEED_CLK_GATE_ESPICLK 12 26 27 #define ASPEED_CLK_GATE_USBUHCICLK 13 28 #define ASPEED_CLK_GATE_USBPORT1CLK 14 29 #define ASPEED_CLK_GATE_USBPORT2CLK 15 30 31 #define ASPEED_CLK_GATE_RSACLK 16 32 #define ASPEED_CLK_GATE_RVASCLK 17 33 34 #define ASPEED_CLK_GATE_MAC1CLK 18 35 #define ASPEED_CLK_GATE_MAC2CLK 19 36 #define ASPEED_CLK_GATE_MAC3CLK 20 37 #define ASPEED_CLK_GATE_MAC4CLK 21 38 39 #define ASPEED_CLK_GATE_UART1CLK 22 40 #define ASPEED_CLK_GATE_UART2CLK 23 41 #define ASPEED_CLK_GATE_UART3CLK 24 42 #define ASPEED_CLK_GATE_UART4CLK 25 43 #define ASPEED_CLK_GATE_UART5CLK 26 44 #define ASPEED_CLK_GATE_UART6CLK 27 45 #define ASPEED_CLK_GATE_UART7CLK 28 46 #define ASPEED_CLK_GATE_UART8CLK 29 47 #define ASPEED_CLK_GATE_UART9CLK 30 48 #define ASPEED_CLK_GATE_UART10CLK 31 49 #define ASPEED_CLK_GATE_UART11CLK 32 50 #define ASPEED_CLK_GATE_UART12CLK 33 51 #define ASPEED_CLK_GATE_UART13CLK 34 52 53 #define ASPEED_CLK_GATE_SDCLK 35 54 #define ASPEED_CLK_GATE_EMMCCLK 36 55 56 #define ASPEED_CLK_GATE_I3C0CLK 37 57 #define ASPEED_CLK_GATE_I3C1CLK 38 58 #define ASPEED_CLK_GATE_I3C2CLK 39 59 #define ASPEED_CLK_GATE_I3C3CLK 40 60 #define ASPEED_CLK_GATE_I3C4CLK 41 61 #define ASPEED_CLK_GATE_I3C5CLK 42 62 #define ASPEED_CLK_GATE_I3C6CLK 43 63 #define ASPEED_CLK_GATE_I3C7CLK 44 64 65 #define ASPEED_CLK_GATE_FSICLK 45 66 67 #define ASPEED_CLK_HPLL 46 68 #define ASPEED_CLK_MPLL 47 69 #define ASPEED_CLK_DPLL 48 70 #define ASPEED_CLK_EPLL 49 71 #define ASPEED_CLK_APLL 50 72 #define ASPEED_CLK_AHB 51 73 #define ASPEED_CLK_APB1 52 74 #define ASPEED_CLK_APB2 53 75 #define ASPEED_CLK_BCLK 54 76 #define ASPEED_CLK_D1CLK 55 77 #define ASPEED_CLK_VCLK 56 78 #define ASPEED_CLK_LHCLK 57 79 #define ASPEED_CLK_UART 58 80 #define ASPEED_CLK_UARTX 59 81 #define ASPEED_CLK_SDIO 60 82 #define ASPEED_CLK_EMMC 61 83 #define ASPEED_CLK_ECLK 62 84 #define ASPEED_CLK_ECLK_MUX 63 85 #define ASPEED_CLK_MAC12 64 86 #define ASPEED_CLK_MAC34 65 87 #define ASPEED_CLK_USBPHY_40M 66 88 #define ASPEED_CLK_MAC1RCLK 67 89 #define ASPEED_CLK_MAC2RCLK 68 90 #define ASPEED_CLK_MAC3RCLK 69 91 #define ASPEED_CLK_MAC4RCLK 70 92 93 /* Only list resets here that are not part of a gate */ 94 #define ASPEED_RESET_ADC 55 95 #define ASPEED_RESET_JTAG_MASTER2 54 96 #define ASPEED_RESET_I3C_DMA 39 97 #define ASPEED_RESET_PWM 37 98 #define ASPEED_RESET_PECI 36 99 #define ASPEED_RESET_MII 35 100 #define ASPEED_RESET_I2C 34 101 #define ASPEED_RESET_H2X 31 102 #define ASPEED_RESET_GP_MCU 30 103 #define ASPEED_RESET_DP_MCU 29 104 #define ASPEED_RESET_DP 28 105 #define ASPEED_RESET_RC_XDMA 27 106 #define ASPEED_RESET_GRAPHICS 26 107 #define ASPEED_RESET_DEV_XDMA 25 108 #define ASPEED_RESET_DEV_MCTP 24 109 #define ASPEED_RESET_RC_MCTP 23 110 #define ASPEED_RESET_JTAG_MASTER 22 111 #define ASPEED_RESET_PCIE_DEV_O 21 112 #define ASPEED_RESET_PCIE_DEV_OEN 20 113 #define ASPEED_RESET_PCIE_RC_O 19 114 #define ASPEED_RESET_PCIE_RC_OEN 18 115 #define ASPEED_RESET_PCI_DP 5 116 #define ASPEED_RESET_AHB 1 117 #define ASPEED_RESET_SDRAM 0 118 119 #endif 120