1 /* $NetBSD: agilex-clock.h,v 1.1.1.1 2021/11/07 16:49:58 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 */ 4 /* 5 * Copyright (C) 2019, Intel Corporation 6 */ 7 8 #ifndef __AGILEX_CLOCK_H 9 #define __AGILEX_CLOCK_H 10 11 /* fixed rate clocks */ 12 #define AGILEX_OSC1 0 13 #define AGILEX_CB_INTOSC_HS_DIV2_CLK 1 14 #define AGILEX_CB_INTOSC_LS_CLK 2 15 #define AGILEX_L4_SYS_FREE_CLK 3 16 #define AGILEX_F2S_FREE_CLK 4 17 18 /* PLL clocks */ 19 #define AGILEX_MAIN_PLL_CLK 5 20 #define AGILEX_MAIN_PLL_C0_CLK 6 21 #define AGILEX_MAIN_PLL_C1_CLK 7 22 #define AGILEX_MAIN_PLL_C2_CLK 8 23 #define AGILEX_MAIN_PLL_C3_CLK 9 24 #define AGILEX_PERIPH_PLL_CLK 10 25 #define AGILEX_PERIPH_PLL_C0_CLK 11 26 #define AGILEX_PERIPH_PLL_C1_CLK 12 27 #define AGILEX_PERIPH_PLL_C2_CLK 13 28 #define AGILEX_PERIPH_PLL_C3_CLK 14 29 #define AGILEX_MPU_FREE_CLK 15 30 #define AGILEX_MPU_CCU_CLK 16 31 #define AGILEX_BOOT_CLK 17 32 33 /* fixed factor clocks */ 34 #define AGILEX_L3_MAIN_FREE_CLK 18 35 #define AGILEX_NOC_FREE_CLK 19 36 #define AGILEX_S2F_USR0_CLK 20 37 #define AGILEX_NOC_CLK 21 38 #define AGILEX_EMAC_A_FREE_CLK 22 39 #define AGILEX_EMAC_B_FREE_CLK 23 40 #define AGILEX_EMAC_PTP_FREE_CLK 24 41 #define AGILEX_GPIO_DB_FREE_CLK 25 42 #define AGILEX_SDMMC_FREE_CLK 26 43 #define AGILEX_S2F_USER0_FREE_CLK 27 44 #define AGILEX_S2F_USER1_FREE_CLK 28 45 #define AGILEX_PSI_REF_FREE_CLK 29 46 47 /* Gate clocks */ 48 #define AGILEX_MPU_CLK 30 49 #define AGILEX_MPU_L2RAM_CLK 31 50 #define AGILEX_MPU_PERIPH_CLK 32 51 #define AGILEX_L4_MAIN_CLK 33 52 #define AGILEX_L4_MP_CLK 34 53 #define AGILEX_L4_SP_CLK 35 54 #define AGILEX_CS_AT_CLK 36 55 #define AGILEX_CS_TRACE_CLK 37 56 #define AGILEX_CS_PDBG_CLK 38 57 #define AGILEX_CS_TIMER_CLK 39 58 #define AGILEX_S2F_USER0_CLK 40 59 #define AGILEX_EMAC0_CLK 41 60 #define AGILEX_EMAC1_CLK 43 61 #define AGILEX_EMAC2_CLK 44 62 #define AGILEX_EMAC_PTP_CLK 45 63 #define AGILEX_GPIO_DB_CLK 46 64 #define AGILEX_NAND_CLK 47 65 #define AGILEX_PSI_REF_CLK 48 66 #define AGILEX_S2F_USER1_CLK 49 67 #define AGILEX_SDMMC_CLK 50 68 #define AGILEX_SPI_M_CLK 51 69 #define AGILEX_USB_CLK 52 70 #define AGILEX_NAND_X_CLK 53 71 #define AGILEX_NAND_ECC_CLK 54 72 #define AGILEX_NUM_CLKS 55 73 74 #endif /* __AGILEX_CLOCK_H */ 75