xref: /netbsd-src/sys/external/bsd/drm2/dist/include/uapi/drm/msm_drm.h (revision 41ec02673d281bbb3d38e6c78504ce6e30c228c1)
1 /*	$NetBSD: msm_drm.h,v 1.2 2021/12/18 23:45:46 riastradh Exp $	*/
2 
3 /*
4  * Copyright (C) 2013 Red Hat
5  * Author: Rob Clark <robdclark@gmail.com>
6  *
7  * Permission is hereby granted, free of charge, to any person obtaining a
8  * copy of this software and associated documentation files (the "Software"),
9  * to deal in the Software without restriction, including without limitation
10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11  * and/or sell copies of the Software, and to permit persons to whom the
12  * Software is furnished to do so, subject to the following conditions:
13  *
14  * The above copyright notice and this permission notice (including the next
15  * paragraph) shall be included in all copies or substantial portions of the
16  * Software.
17  *
18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
21  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24  * SOFTWARE.
25  */
26 
27 #ifndef __MSM_DRM_H__
28 #define __MSM_DRM_H__
29 
30 #include "drm.h"
31 
32 #if defined(__cplusplus)
33 extern "C" {
34 #endif
35 
36 /* Please note that modifications to all structs defined here are
37  * subject to backwards-compatibility constraints:
38  *  1) Do not use pointers, use __u64 instead for 32 bit / 64 bit
39  *     user/kernel compatibility
40  *  2) Keep fields aligned to their size
41  *  3) Because of how drm_ioctl() works, we can add new fields at
42  *     the end of an ioctl if some care is taken: drm_ioctl() will
43  *     zero out the new fields at the tail of the ioctl, so a zero
44  *     value should have a backwards compatible meaning.  And for
45  *     output params, userspace won't see the newly added output
46  *     fields.. so that has to be somehow ok.
47  */
48 
49 #define MSM_PIPE_NONE        0x00
50 #define MSM_PIPE_2D0         0x01
51 #define MSM_PIPE_2D1         0x02
52 #define MSM_PIPE_3D0         0x10
53 
54 /* The pipe-id just uses the lower bits, so can be OR'd with flags in
55  * the upper 16 bits (which could be extended further, if needed, maybe
56  * we extend/overload the pipe-id some day to deal with multiple rings,
57  * but even then I don't think we need the full lower 16 bits).
58  */
59 #define MSM_PIPE_ID_MASK     0xffff
60 #define MSM_PIPE_ID(x)       ((x) & MSM_PIPE_ID_MASK)
61 #define MSM_PIPE_FLAGS(x)    ((x) & ~MSM_PIPE_ID_MASK)
62 
63 /* timeouts are specified in clock-monotonic absolute times (to simplify
64  * restarting interrupted ioctls).  The following struct is logically the
65  * same as 'struct timespec' but 32/64b ABI safe.
66  */
67 struct drm_msm_timespec {
68 	__s64 tv_sec;          /* seconds */
69 	__s64 tv_nsec;         /* nanoseconds */
70 };
71 
72 #define MSM_PARAM_GPU_ID     0x01
73 #define MSM_PARAM_GMEM_SIZE  0x02
74 #define MSM_PARAM_CHIP_ID    0x03
75 #define MSM_PARAM_MAX_FREQ   0x04
76 #define MSM_PARAM_TIMESTAMP  0x05
77 #define MSM_PARAM_GMEM_BASE  0x06
78 #define MSM_PARAM_NR_RINGS   0x07
79 #define MSM_PARAM_PP_PGTABLE 0x08  /* => 1 for per-process pagetables, else 0 */
80 #define MSM_PARAM_FAULTS     0x09
81 
82 struct drm_msm_param {
83 	__u32 pipe;           /* in, MSM_PIPE_x */
84 	__u32 param;          /* in, MSM_PARAM_x */
85 	__u64 value;          /* out (get_param) or in (set_param) */
86 };
87 
88 /*
89  * GEM buffers:
90  */
91 
92 #define MSM_BO_SCANOUT       0x00000001     /* scanout capable */
93 #define MSM_BO_GPU_READONLY  0x00000002
94 #define MSM_BO_CACHE_MASK    0x000f0000
95 /* cache modes */
96 #define MSM_BO_CACHED        0x00010000
97 #define MSM_BO_WC            0x00020000
98 #define MSM_BO_UNCACHED      0x00040000
99 
100 #define MSM_BO_FLAGS         (MSM_BO_SCANOUT | \
101                               MSM_BO_GPU_READONLY | \
102                               MSM_BO_CACHED | \
103                               MSM_BO_WC | \
104                               MSM_BO_UNCACHED)
105 
106 struct drm_msm_gem_new {
107 	__u64 size;           /* in */
108 	__u32 flags;          /* in, mask of MSM_BO_x */
109 	__u32 handle;         /* out */
110 };
111 
112 /* Get or set GEM buffer info.  The requested value can be passed
113  * directly in 'value', or for data larger than 64b 'value' is a
114  * pointer to userspace buffer, with 'len' specifying the number of
115  * bytes copied into that buffer.  For info returned by pointer,
116  * calling the GEM_INFO ioctl with null 'value' will return the
117  * required buffer size in 'len'
118  */
119 #define MSM_INFO_GET_OFFSET	0x00   /* get mmap() offset, returned by value */
120 #define MSM_INFO_GET_IOVA	0x01   /* get iova, returned by value */
121 #define MSM_INFO_SET_NAME	0x02   /* set the debug name (by pointer) */
122 #define MSM_INFO_GET_NAME	0x03   /* get debug name, returned by pointer */
123 
124 struct drm_msm_gem_info {
125 	__u32 handle;         /* in */
126 	__u32 info;           /* in - one of MSM_INFO_* */
127 	__u64 value;          /* in or out */
128 	__u32 len;            /* in or out */
129 	__u32 pad;
130 };
131 
132 #define MSM_PREP_READ        0x01
133 #define MSM_PREP_WRITE       0x02
134 #define MSM_PREP_NOSYNC      0x04
135 
136 #define MSM_PREP_FLAGS       (MSM_PREP_READ | MSM_PREP_WRITE | MSM_PREP_NOSYNC)
137 
138 struct drm_msm_gem_cpu_prep {
139 	__u32 handle;         /* in */
140 	__u32 op;             /* in, mask of MSM_PREP_x */
141 	struct drm_msm_timespec timeout;   /* in */
142 };
143 
144 struct drm_msm_gem_cpu_fini {
145 	__u32 handle;         /* in */
146 };
147 
148 /*
149  * Cmdstream Submission:
150  */
151 
152 /* The value written into the cmdstream is logically:
153  *
154  *   ((relocbuf->gpuaddr + reloc_offset) << shift) | or
155  *
156  * When we have GPU's w/ >32bit ptrs, it should be possible to deal
157  * with this by emit'ing two reloc entries with appropriate shift
158  * values.  Or a new MSM_SUBMIT_CMD_x type would also be an option.
159  *
160  * NOTE that reloc's must be sorted by order of increasing submit_offset,
161  * otherwise EINVAL.
162  */
163 struct drm_msm_gem_submit_reloc {
164 	__u32 submit_offset;  /* in, offset from submit_bo */
165 	__u32 or;             /* in, value OR'd with result */
166 	__s32 shift;          /* in, amount of left shift (can be negative) */
167 	__u32 reloc_idx;      /* in, index of reloc_bo buffer */
168 	__u64 reloc_offset;   /* in, offset from start of reloc_bo */
169 };
170 
171 /* submit-types:
172  *   BUF - this cmd buffer is executed normally.
173  *   IB_TARGET_BUF - this cmd buffer is an IB target.  Reloc's are
174  *      processed normally, but the kernel does not setup an IB to
175  *      this buffer in the first-level ringbuffer
176  *   CTX_RESTORE_BUF - only executed if there has been a GPU context
177  *      switch since the last SUBMIT ioctl
178  */
179 #define MSM_SUBMIT_CMD_BUF             0x0001
180 #define MSM_SUBMIT_CMD_IB_TARGET_BUF   0x0002
181 #define MSM_SUBMIT_CMD_CTX_RESTORE_BUF 0x0003
182 struct drm_msm_gem_submit_cmd {
183 	__u32 type;           /* in, one of MSM_SUBMIT_CMD_x */
184 	__u32 submit_idx;     /* in, index of submit_bo cmdstream buffer */
185 	__u32 submit_offset;  /* in, offset into submit_bo */
186 	__u32 size;           /* in, cmdstream size */
187 	__u32 pad;
188 	__u32 nr_relocs;      /* in, number of submit_reloc's */
189 	__u64 relocs;         /* in, ptr to array of submit_reloc's */
190 };
191 
192 /* Each buffer referenced elsewhere in the cmdstream submit (ie. the
193  * cmdstream buffer(s) themselves or reloc entries) has one (and only
194  * one) entry in the submit->bos[] table.
195  *
196  * As a optimization, the current buffer (gpu virtual address) can be
197  * passed back through the 'presumed' field.  If on a subsequent reloc,
198  * userspace passes back a 'presumed' address that is still valid,
199  * then patching the cmdstream for this entry is skipped.  This can
200  * avoid kernel needing to map/access the cmdstream bo in the common
201  * case.
202  */
203 #define MSM_SUBMIT_BO_READ             0x0001
204 #define MSM_SUBMIT_BO_WRITE            0x0002
205 #define MSM_SUBMIT_BO_DUMP             0x0004
206 
207 #define MSM_SUBMIT_BO_FLAGS            (MSM_SUBMIT_BO_READ | \
208 					MSM_SUBMIT_BO_WRITE | \
209 					MSM_SUBMIT_BO_DUMP)
210 
211 struct drm_msm_gem_submit_bo {
212 	__u32 flags;          /* in, mask of MSM_SUBMIT_BO_x */
213 	__u32 handle;         /* in, GEM handle */
214 	__u64 presumed;       /* in/out, presumed buffer address */
215 };
216 
217 /* Valid submit ioctl flags: */
218 #define MSM_SUBMIT_NO_IMPLICIT   0x80000000 /* disable implicit sync */
219 #define MSM_SUBMIT_FENCE_FD_IN   0x40000000 /* enable input fence_fd */
220 #define MSM_SUBMIT_FENCE_FD_OUT  0x20000000 /* enable output fence_fd */
221 #define MSM_SUBMIT_SUDO          0x10000000 /* run submitted cmds from RB */
222 #define MSM_SUBMIT_FLAGS                ( \
223 		MSM_SUBMIT_NO_IMPLICIT   | \
224 		MSM_SUBMIT_FENCE_FD_IN   | \
225 		MSM_SUBMIT_FENCE_FD_OUT  | \
226 		MSM_SUBMIT_SUDO          | \
227 		0)
228 
229 /* Each cmdstream submit consists of a table of buffers involved, and
230  * one or more cmdstream buffers.  This allows for conditional execution
231  * (context-restore), and IB buffers needed for per tile/bin draw cmds.
232  */
233 struct drm_msm_gem_submit {
234 	__u32 flags;          /* MSM_PIPE_x | MSM_SUBMIT_x */
235 	__u32 fence;          /* out */
236 	__u32 nr_bos;         /* in, number of submit_bo's */
237 	__u32 nr_cmds;        /* in, number of submit_cmd's */
238 	__u64 bos;            /* in, ptr to array of submit_bo's */
239 	__u64 cmds;           /* in, ptr to array of submit_cmd's */
240 	__s32 fence_fd;       /* in/out fence fd (see MSM_SUBMIT_FENCE_FD_IN/OUT) */
241 	__u32 queueid;         /* in, submitqueue id */
242 };
243 
244 /* The normal way to synchronize with the GPU is just to CPU_PREP on
245  * a buffer if you need to access it from the CPU (other cmdstream
246  * submission from same or other contexts, PAGE_FLIP ioctl, etc, all
247  * handle the required synchronization under the hood).  This ioctl
248  * mainly just exists as a way to implement the gallium pipe_fence
249  * APIs without requiring a dummy bo to synchronize on.
250  */
251 struct drm_msm_wait_fence {
252 	__u32 fence;          /* in */
253 	__u32 pad;
254 	struct drm_msm_timespec timeout;   /* in */
255 	__u32 queueid;         /* in, submitqueue id */
256 };
257 
258 /* madvise provides a way to tell the kernel in case a buffers contents
259  * can be discarded under memory pressure, which is useful for userspace
260  * bo cache where we want to optimistically hold on to buffer allocate
261  * and potential mmap, but allow the pages to be discarded under memory
262  * pressure.
263  *
264  * Typical usage would involve madvise(DONTNEED) when buffer enters BO
265  * cache, and madvise(WILLNEED) if trying to recycle buffer from BO cache.
266  * In the WILLNEED case, 'retained' indicates to userspace whether the
267  * backing pages still exist.
268  */
269 #define MSM_MADV_WILLNEED 0       /* backing pages are needed, status returned in 'retained' */
270 #define MSM_MADV_DONTNEED 1       /* backing pages not needed */
271 #define __MSM_MADV_PURGED 2       /* internal state */
272 
273 struct drm_msm_gem_madvise {
274 	__u32 handle;         /* in, GEM handle */
275 	__u32 madv;           /* in, MSM_MADV_x */
276 	__u32 retained;       /* out, whether backing store still exists */
277 };
278 
279 /*
280  * Draw queues allow the user to set specific submission parameter. Command
281  * submissions specify a specific submitqueue to use.  ID 0 is reserved for
282  * backwards compatibility as a "default" submitqueue
283  */
284 
285 #define MSM_SUBMITQUEUE_FLAGS (0)
286 
287 struct drm_msm_submitqueue {
288 	__u32 flags;   /* in, MSM_SUBMITQUEUE_x */
289 	__u32 prio;    /* in, Priority level */
290 	__u32 id;      /* out, identifier */
291 };
292 
293 #define MSM_SUBMITQUEUE_PARAM_FAULTS   0
294 
295 struct drm_msm_submitqueue_query {
296 	__u64 data;
297 	__u32 id;
298 	__u32 param;
299 	__u32 len;
300 	__u32 pad;
301 };
302 
303 #define DRM_MSM_GET_PARAM              0x00
304 /* placeholder:
305 #define DRM_MSM_SET_PARAM              0x01
306  */
307 #define DRM_MSM_GEM_NEW                0x02
308 #define DRM_MSM_GEM_INFO               0x03
309 #define DRM_MSM_GEM_CPU_PREP           0x04
310 #define DRM_MSM_GEM_CPU_FINI           0x05
311 #define DRM_MSM_GEM_SUBMIT             0x06
312 #define DRM_MSM_WAIT_FENCE             0x07
313 #define DRM_MSM_GEM_MADVISE            0x08
314 /* placeholder:
315 #define DRM_MSM_GEM_SVM_NEW            0x09
316  */
317 #define DRM_MSM_SUBMITQUEUE_NEW        0x0A
318 #define DRM_MSM_SUBMITQUEUE_CLOSE      0x0B
319 #define DRM_MSM_SUBMITQUEUE_QUERY      0x0C
320 
321 #define DRM_IOCTL_MSM_GET_PARAM        DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GET_PARAM, struct drm_msm_param)
322 #define DRM_IOCTL_MSM_GEM_NEW          DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_NEW, struct drm_msm_gem_new)
323 #define DRM_IOCTL_MSM_GEM_INFO         DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_INFO, struct drm_msm_gem_info)
324 #define DRM_IOCTL_MSM_GEM_CPU_PREP     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_PREP, struct drm_msm_gem_cpu_prep)
325 #define DRM_IOCTL_MSM_GEM_CPU_FINI     DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_GEM_CPU_FINI, struct drm_msm_gem_cpu_fini)
326 #define DRM_IOCTL_MSM_GEM_SUBMIT       DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_SUBMIT, struct drm_msm_gem_submit)
327 #define DRM_IOCTL_MSM_WAIT_FENCE       DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_WAIT_FENCE, struct drm_msm_wait_fence)
328 #define DRM_IOCTL_MSM_GEM_MADVISE      DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_GEM_MADVISE, struct drm_msm_gem_madvise)
329 #define DRM_IOCTL_MSM_SUBMITQUEUE_NEW    DRM_IOWR(DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_NEW, struct drm_msm_submitqueue)
330 #define DRM_IOCTL_MSM_SUBMITQUEUE_CLOSE  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_CLOSE, __u32)
331 #define DRM_IOCTL_MSM_SUBMITQUEUE_QUERY  DRM_IOW (DRM_COMMAND_BASE + DRM_MSM_SUBMITQUEUE_QUERY, struct drm_msm_submitqueue_query)
332 
333 #if defined(__cplusplus)
334 }
335 #endif
336 
337 #endif /* __MSM_DRM_H__ */
338