1 /* $NetBSD: i915_suspend.c,v 1.3 2021/12/18 23:45:28 riastradh Exp $ */
2
3 /*
4 *
5 * Copyright 2008 (c) Intel Corporation
6 * Jesse Barnes <jbarnes@virtuousgeek.org>
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 */
28
29 #include <sys/cdefs.h>
30 __KERNEL_RCSID(0, "$NetBSD: i915_suspend.c,v 1.3 2021/12/18 23:45:28 riastradh Exp $");
31
32 #include <drm/i915_drm.h>
33
34 #include "display/intel_fbc.h"
35 #include "display/intel_gmbus.h"
36 #include "display/intel_vga.h"
37
38 #include "i915_drv.h"
39 #include "i915_reg.h"
40 #include "i915_suspend.h"
41
i915_save_display(struct drm_i915_private * dev_priv)42 static void i915_save_display(struct drm_i915_private *dev_priv)
43 {
44 /* Display arbitration control */
45 if (INTEL_GEN(dev_priv) <= 4)
46 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
47
48 /* save FBC interval */
49 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
50 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
51 }
52
i915_restore_display(struct drm_i915_private * dev_priv)53 static void i915_restore_display(struct drm_i915_private *dev_priv)
54 {
55 /* Display arbitration */
56 if (INTEL_GEN(dev_priv) <= 4)
57 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
58
59 /* only restore FBC info on the platform that supports FBC*/
60 intel_fbc_global_disable(dev_priv);
61
62 /* restore FBC interval */
63 if (HAS_FBC(dev_priv) && INTEL_GEN(dev_priv) <= 4 && !IS_G4X(dev_priv))
64 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
65
66 intel_vga_redisable(dev_priv);
67 }
68
i915_save_state(struct drm_i915_private * dev_priv)69 int i915_save_state(struct drm_i915_private *dev_priv)
70 {
71 struct pci_dev *pdev = dev_priv->drm.pdev;
72 int i;
73
74 i915_save_display(dev_priv);
75
76 if (IS_GEN(dev_priv, 4))
77 pci_read_config_word(pdev, GCDGMBUS,
78 &dev_priv->regfile.saveGCDGMBUS);
79
80 /* Cache mode state */
81 if (INTEL_GEN(dev_priv) < 7)
82 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
83
84 /* Memory Arbitration state */
85 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
86
87 /* Scratch space */
88 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
89 for (i = 0; i < 7; i++) {
90 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
91 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
92 }
93 for (i = 0; i < 3; i++)
94 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
95 } else if (IS_GEN(dev_priv, 2)) {
96 for (i = 0; i < 7; i++)
97 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
98 } else if (HAS_GMCH(dev_priv)) {
99 for (i = 0; i < 16; i++) {
100 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i));
101 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i));
102 }
103 for (i = 0; i < 3; i++)
104 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i));
105 }
106
107 return 0;
108 }
109
i915_restore_state(struct drm_i915_private * dev_priv)110 int i915_restore_state(struct drm_i915_private *dev_priv)
111 {
112 struct pci_dev *pdev = dev_priv->drm.pdev;
113 int i;
114
115 if (IS_GEN(dev_priv, 4))
116 pci_write_config_word(pdev, GCDGMBUS,
117 dev_priv->regfile.saveGCDGMBUS);
118 i915_restore_display(dev_priv);
119
120 /* Cache mode state */
121 if (INTEL_GEN(dev_priv) < 7)
122 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 |
123 0xffff0000);
124
125 /* Memory arbitration state */
126 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
127
128 /* Scratch space */
129 if (IS_GEN(dev_priv, 2) && IS_MOBILE(dev_priv)) {
130 for (i = 0; i < 7; i++) {
131 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
132 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
133 }
134 for (i = 0; i < 3; i++)
135 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
136 } else if (IS_GEN(dev_priv, 2)) {
137 for (i = 0; i < 7; i++)
138 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
139 } else if (HAS_GMCH(dev_priv)) {
140 for (i = 0; i < 16; i++) {
141 I915_WRITE(SWF0(i), dev_priv->regfile.saveSWF0[i]);
142 I915_WRITE(SWF1(i), dev_priv->regfile.saveSWF1[i]);
143 }
144 for (i = 0; i < 3; i++)
145 I915_WRITE(SWF3(i), dev_priv->regfile.saveSWF3[i]);
146 }
147
148 intel_gmbus_reset(dev_priv);
149
150 return 0;
151 }
152