1 /* $NetBSD: amdgpu_vega10_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $ */
2
3 /*
4 * Copyright 2017 Advanced Micro Devices, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 */
25 #include <sys/cdefs.h>
26 __KERNEL_RCSID(0, "$NetBSD: amdgpu_vega10_reg_init.c,v 1.2 2021/12/18 23:44:58 riastradh Exp $");
27
28 #include "amdgpu.h"
29 #include "soc15.h"
30
31 #include "soc15_common.h"
32 #include "vega10_ip_offset.h"
33
vega10_reg_base_init(struct amdgpu_device * adev)34 int vega10_reg_base_init(struct amdgpu_device *adev)
35 {
36 /* HW has more IP blocks, only initialized the blocke beend by our driver */
37 uint32_t i;
38 for (i = 0 ; i < MAX_INSTANCE ; ++i) {
39 adev->reg_offset[GC_HWIP][i] = (uint32_t *)(&(GC_BASE.instance[i]));
40 adev->reg_offset[HDP_HWIP][i] = (uint32_t *)(&(HDP_BASE.instance[i]));
41 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i]));
42 adev->reg_offset[ATHUB_HWIP][i] = (uint32_t *)(&(ATHUB_BASE.instance[i]));
43 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i]));
44 adev->reg_offset[MP0_HWIP][i] = (uint32_t *)(&(MP0_BASE.instance[i]));
45 adev->reg_offset[MP1_HWIP][i] = (uint32_t *)(&(MP1_BASE.instance[i]));
46 adev->reg_offset[UVD_HWIP][i] = (uint32_t *)(&(UVD_BASE.instance[i]));
47 adev->reg_offset[VCE_HWIP][i] = (uint32_t *)(&(VCE_BASE.instance[i]));
48 adev->reg_offset[VCN_HWIP][i] = (uint32_t *)(&(VCN_BASE.instance[i]));
49 adev->reg_offset[DF_HWIP][i] = (uint32_t *)(&(DF_BASE.instance[i]));
50 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCE_BASE.instance[i]));
51 adev->reg_offset[OSSSYS_HWIP][i] = (uint32_t *)(&(OSSSYS_BASE.instance[i]));
52 adev->reg_offset[SDMA0_HWIP][i] = (uint32_t *)(&(SDMA0_BASE.instance[i]));
53 adev->reg_offset[SDMA1_HWIP][i] = (uint32_t *)(&(SDMA1_BASE.instance[i]));
54 adev->reg_offset[SMUIO_HWIP][i] = (uint32_t *)(&(SMUIO_BASE.instance[i]));
55 adev->reg_offset[PWR_HWIP][i] = (uint32_t *)(&(PWR_BASE.instance[i]));
56 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIF_BASE.instance[i]));
57 adev->reg_offset[THM_HWIP][i] = (uint32_t *)(&(THM_BASE.instance[i]));
58 adev->reg_offset[CLK_HWIP][i] = (uint32_t *)(&(CLK_BASE.instance[i]));
59 }
60 return 0;
61 }
62
vega10_doorbell_index_init(struct amdgpu_device * adev)63 void vega10_doorbell_index_init(struct amdgpu_device *adev)
64 {
65 adev->doorbell_index.kiq = AMDGPU_DOORBELL64_KIQ;
66 adev->doorbell_index.mec_ring0 = AMDGPU_DOORBELL64_MEC_RING0;
67 adev->doorbell_index.mec_ring1 = AMDGPU_DOORBELL64_MEC_RING1;
68 adev->doorbell_index.mec_ring2 = AMDGPU_DOORBELL64_MEC_RING2;
69 adev->doorbell_index.mec_ring3 = AMDGPU_DOORBELL64_MEC_RING3;
70 adev->doorbell_index.mec_ring4 = AMDGPU_DOORBELL64_MEC_RING4;
71 adev->doorbell_index.mec_ring5 = AMDGPU_DOORBELL64_MEC_RING5;
72 adev->doorbell_index.mec_ring6 = AMDGPU_DOORBELL64_MEC_RING6;
73 adev->doorbell_index.mec_ring7 = AMDGPU_DOORBELL64_MEC_RING7;
74 adev->doorbell_index.userqueue_start = AMDGPU_DOORBELL64_USERQUEUE_START;
75 adev->doorbell_index.userqueue_end = AMDGPU_DOORBELL64_USERQUEUE_END;
76 adev->doorbell_index.gfx_ring0 = AMDGPU_DOORBELL64_GFX_RING0;
77 adev->doorbell_index.sdma_engine[0] = AMDGPU_DOORBELL64_sDMA_ENGINE0;
78 adev->doorbell_index.sdma_engine[1] = AMDGPU_DOORBELL64_sDMA_ENGINE1;
79 adev->doorbell_index.ih = AMDGPU_DOORBELL64_IH;
80 adev->doorbell_index.uvd_vce.uvd_ring0_1 = AMDGPU_DOORBELL64_UVD_RING0_1;
81 adev->doorbell_index.uvd_vce.uvd_ring2_3 = AMDGPU_DOORBELL64_UVD_RING2_3;
82 adev->doorbell_index.uvd_vce.uvd_ring4_5 = AMDGPU_DOORBELL64_UVD_RING4_5;
83 adev->doorbell_index.uvd_vce.uvd_ring6_7 = AMDGPU_DOORBELL64_UVD_RING6_7;
84 adev->doorbell_index.uvd_vce.vce_ring0_1 = AMDGPU_DOORBELL64_VCE_RING0_1;
85 adev->doorbell_index.uvd_vce.vce_ring2_3 = AMDGPU_DOORBELL64_VCE_RING2_3;
86 adev->doorbell_index.uvd_vce.vce_ring4_5 = AMDGPU_DOORBELL64_VCE_RING4_5;
87 adev->doorbell_index.uvd_vce.vce_ring6_7 = AMDGPU_DOORBELL64_VCE_RING6_7;
88 adev->doorbell_index.vcn.vcn_ring0_1 = AMDGPU_DOORBELL64_VCN0_1;
89 adev->doorbell_index.vcn.vcn_ring2_3 = AMDGPU_DOORBELL64_VCN2_3;
90 adev->doorbell_index.vcn.vcn_ring4_5 = AMDGPU_DOORBELL64_VCN4_5;
91 adev->doorbell_index.vcn.vcn_ring6_7 = AMDGPU_DOORBELL64_VCN6_7;
92
93 adev->doorbell_index.first_non_cp = AMDGPU_DOORBELL64_FIRST_NON_CP;
94 adev->doorbell_index.last_non_cp = AMDGPU_DOORBELL64_LAST_NON_CP;
95
96 /* In unit of dword doorbell */
97 adev->doorbell_index.max_assignment = AMDGPU_DOORBELL64_MAX_ASSIGNMENT << 1;
98 adev->doorbell_index.sdma_doorbell_range = 4;
99 }
100
101