1 /* $NetBSD: zs_ioasic.c,v 1.32 2006/05/10 06:24:03 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 42 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 43 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 44 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 45 * 46 * Runs two serial lines per chip using slave drivers. 47 * Plain tty/async lines use the zstty slave. 48 */ 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.32 2006/05/10 06:24:03 skrll Exp $"); 52 53 #include "opt_ddb.h" 54 #include "opt_kgdb.h" 55 #include "zskbd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/conf.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/file.h> 63 #include <sys/ioctl.h> 64 #include <sys/kernel.h> 65 #include <sys/proc.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/syslog.h> 69 70 #include <machine/autoconf.h> 71 #include <machine/intr.h> 72 #include <machine/z8530var.h> 73 74 #include <dev/cons.h> 75 #include <dev/ic/z8530reg.h> 76 77 #include <dev/tc/tcvar.h> 78 #include <dev/tc/ioasicreg.h> 79 #include <dev/tc/ioasicvar.h> 80 81 #include <dev/tc/zs_ioasicvar.h> 82 83 #if defined(__alpha__) || defined(alpha) 84 #include <machine/rpb.h> 85 #endif 86 #if defined(pmax) 87 #include <pmax/pmax/pmaxtype.h> 88 #endif 89 90 /* 91 * Helpers for console support. 92 */ 93 static void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int); 94 static int zs_ioasic_cngetc(dev_t); 95 static void zs_ioasic_cnputc(dev_t, int); 96 static void zs_ioasic_cnpollc(dev_t, int); 97 98 struct consdev zs_ioasic_cons = { 99 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 100 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL, 101 }; 102 103 static tc_offset_t zs_ioasic_console_offset; 104 static int zs_ioasic_console_channel; 105 static int zs_ioasic_console; 106 static struct zs_chanstate zs_ioasic_conschanstate_store; 107 108 static int zs_ioasic_isconsole(tc_offset_t, int); 109 static void zs_putc(struct zs_chanstate *, int); 110 111 /* 112 * Some warts needed by z8530tty.c 113 */ 114 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 115 116 /* 117 * ZS chips are feeded a 7.372 MHz clock. 118 */ 119 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 120 121 /* The layout of this is hardware-dependent (padding, order). */ 122 struct zshan { 123 #if defined(__alpha__) || defined(alpha) 124 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 125 u_int zc_pad0; 126 volatile u_int zc_data; /* data */ 127 u_int sc_pad1; 128 #endif 129 #if defined(pmax) 130 volatile u_int16_t zc_csr; /* ctrl,status, and indirect access */ 131 unsigned : 16; 132 volatile u_int16_t zc_data; /* data */ 133 unsigned : 16; 134 #endif 135 }; 136 137 struct zsdevice { 138 /* Yes, they are backwards. */ 139 struct zshan zs_chan_b; 140 struct zshan zs_chan_a; 141 }; 142 143 static const u_char zs_ioasic_init_reg[16] = { 144 0, /* 0: CMD (reset, etc.) */ 145 0, /* 1: No interrupts yet. */ 146 0xf0, /* 2: IVECT */ 147 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 148 ZSWR4_CLK_X16 | ZSWR4_ONESB, 149 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 150 0, /* 6: TXSYNC/SYNCLO */ 151 0, /* 7: RXSYNC/SYNCHI */ 152 0, /* 8: alias for data port */ 153 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 154 0, /*10: Misc. TX/RX control bits */ 155 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 156 22, /*12: BAUDLO (default=9600) */ 157 0, /*13: BAUDHI (default=9600) */ 158 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 159 ZSWR15_BREAK_IE, 160 }; 161 162 static struct zshan * 163 zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel) 164 { 165 struct zsdevice *addr; 166 struct zshan *zc; 167 168 #if defined(__alpha__) || defined(alpha) 169 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 170 #endif 171 #if defined(pmax) 172 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 173 #endif 174 175 if (channel == 0) 176 zc = &addr->zs_chan_a; 177 else 178 zc = &addr->zs_chan_b; 179 180 return (zc); 181 } 182 183 184 /**************************************************************** 185 * Autoconfig 186 ****************************************************************/ 187 188 /* Definition of the driver for autoconfig. */ 189 static int zs_ioasic_match(struct device *, struct cfdata *, void *); 190 static void zs_ioasic_attach(struct device *, struct device *, void *); 191 static int zs_ioasic_print(void *, const char *name); 192 static int zs_ioasic_submatch(struct device *, struct cfdata *, 193 const int *, void *); 194 195 CFATTACH_DECL(zsc_ioasic, sizeof(struct zsc_softc), 196 zs_ioasic_match, zs_ioasic_attach, NULL, NULL); 197 198 /* Interrupt handlers. */ 199 static int zs_ioasic_hardintr(void *); 200 static void zs_ioasic_softintr(void *); 201 202 /* 203 * Is the zs chip present? 204 */ 205 static int 206 zs_ioasic_match(struct device *parent, struct cfdata *cf, void *aux) 207 { 208 struct ioasicdev_attach_args *d = aux; 209 tc_addr_t zs_addr; 210 211 /* 212 * Make sure that we're looking for the right kind of device. 213 */ 214 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 215 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 216 return (0); 217 218 /* 219 * Find out the device address, and check it for validity. 220 */ 221 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 222 if (tc_badaddr(zs_addr)) 223 return (0); 224 225 return (1); 226 } 227 228 /* 229 * Attach a found zs. 230 */ 231 static void 232 zs_ioasic_attach(struct device *parent, struct device *self, void *aux) 233 { 234 struct zsc_softc *zs = device_private(self); 235 struct zsc_attach_args zs_args; 236 struct zs_chanstate *cs; 237 struct ioasicdev_attach_args *d = aux; 238 struct zshan *zc; 239 int s, channel; 240 u_long zflg; 241 int locs[ZSCCF_NLOCS]; 242 243 printf("\n"); 244 245 /* 246 * Initialize software state for each channel. 247 */ 248 for (channel = 0; channel < 2; channel++) { 249 zs_args.channel = channel; 250 zs_args.hwflags = 0; 251 252 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 253 cs = &zs_ioasic_conschanstate_store; 254 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 255 } else { 256 cs = malloc(sizeof(struct zs_chanstate), 257 M_DEVBUF, M_NOWAIT|M_ZERO); 258 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 259 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 260 261 bcopy(zs_ioasic_init_reg, cs->cs_creg, 16); 262 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 263 264 cs->cs_defcflag = zs_def_cflag; 265 cs->cs_defspeed = 9600; /* XXX */ 266 (void) zs_set_modes(cs, cs->cs_defcflag); 267 } 268 269 zs->zsc_cs[channel] = cs; 270 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 271 cs->cs_channel = channel; 272 cs->cs_ops = &zsops_null; 273 cs->cs_brg_clk = PCLK / 16; 274 275 /* 276 * DCD and CTS interrupts are only meaningful on 277 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 278 * 279 * XXX This is sorta gross. 280 */ 281 if (d->iada_offset == 0x00100000 && channel == 1) { 282 cs->cs_creg[15] |= ZSWR15_DCD_IE; 283 cs->cs_preg[15] |= ZSWR15_DCD_IE; 284 zflg = ZIP_FLAGS_DCDCTS; 285 } else 286 zflg = 0; 287 if (channel == 1) 288 zflg |= ZIP_FLAGS_DTRRTS; 289 cs->cs_private = (void *)zflg; 290 291 /* 292 * Clear the master interrupt enable. 293 * The INTENA is common to both channels, 294 * so just do it on the A channel. 295 */ 296 if (channel == 0) { 297 zs_write_reg(cs, 9, 0); 298 } 299 300 /* 301 * Set up the flow/modem control channel pointer to 302 * deal with the weird wiring on the TC Alpha and 303 * DECstation. 304 */ 305 if (channel == 1) 306 cs->cs_ctl_chan = zs->zsc_cs[0]; 307 else 308 cs->cs_ctl_chan = NULL; 309 310 locs[ZSCCF_CHANNEL] = channel; 311 312 /* 313 * Look for a child driver for this channel. 314 * The child attach will setup the hardware. 315 */ 316 if (config_found_sm_loc(self, "zsc", locs, (void *)&zs_args, 317 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 318 /* No sub-driver. Just reset it. */ 319 u_char reset = (channel == 0) ? 320 ZSWR9_A_RESET : ZSWR9_B_RESET; 321 s = splhigh(); 322 zs_write_reg(cs, 9, reset); 323 splx(s); 324 } 325 } 326 327 /* 328 * Set up the ioasic interrupt handler. 329 */ 330 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 331 zs_ioasic_hardintr, zs); 332 zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, 333 zs_ioasic_softintr, zs); 334 if (zs->zsc_sih == NULL) 335 panic("zs_ioasic_attach: unable to register softintr"); 336 337 /* 338 * Set the master interrupt enable and interrupt vector. The 339 * Sun does this only on one channel. The old Alpha SCC driver 340 * did it on both. We'll do it on both. 341 */ 342 s = splhigh(); 343 /* interrupt vector */ 344 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 345 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 346 347 /* master interrupt control (enable) */ 348 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 349 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 350 #if defined(__alpha__) || defined(alpha) 351 /* ioasic interrupt enable */ 352 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 353 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 354 tc_mb(); 355 #endif 356 splx(s); 357 } 358 359 static int 360 zs_ioasic_print(void *aux, const char *name) 361 { 362 struct zsc_attach_args *args = aux; 363 364 if (name != NULL) 365 aprint_normal("%s:", name); 366 367 if (args->channel != -1) 368 aprint_normal(" channel %d", args->channel); 369 370 return (UNCONF); 371 } 372 373 static int 374 zs_ioasic_submatch(struct device *parent, struct cfdata *cf, const int *locs, 375 void *aux) 376 { 377 struct zsc_softc *zs = (void *)parent; 378 struct zsc_attach_args *pa = aux; 379 const char *defname = ""; 380 381 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 382 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL]) 383 return (0); 384 385 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 386 if (pa->channel == 0) { 387 #if defined(pmax) 388 if (systype == DS_MAXINE) 389 return (0); 390 #endif 391 if (zs->zsc_addroffset == 0x100000) 392 defname = "vsms"; 393 else 394 defname = "lkkbd"; 395 } 396 else if (zs->zsc_addroffset == 0x100000) 397 defname = "zstty"; 398 #if defined(pmax) 399 else if (systype == DS_MAXINE) 400 return (0); 401 #endif 402 #if defined(__alpha__) || defined(alpha) 403 else if (cputype == ST_DEC_3000_300) 404 return (0); 405 #endif 406 else 407 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 408 409 if (strcmp(cf->cf_name, defname)) 410 return (0); 411 } 412 return (config_match(parent, cf, aux)); 413 } 414 415 /* 416 * Hardware interrupt handler. 417 */ 418 static int 419 zs_ioasic_hardintr(void *arg) 420 { 421 struct zsc_softc *zsc = arg; 422 423 /* 424 * Call the upper-level MI hardware interrupt handler. 425 */ 426 zsc_intr_hard(zsc); 427 428 /* 429 * Check to see if we need to schedule any software-level 430 * processing interrupts. 431 */ 432 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 433 softintr_schedule(zsc->zsc_sih); 434 435 return (1); 436 } 437 438 /* 439 * Software-level interrupt (character processing, lower priority). 440 */ 441 static void 442 zs_ioasic_softintr(void *arg) 443 { 444 struct zsc_softc *zsc = arg; 445 int s; 446 447 s = spltty(); 448 (void) zsc_intr_soft(zsc); 449 splx(s); 450 } 451 452 /* 453 * MD functions for setting the baud rate and control modes. 454 */ 455 int 456 zs_set_speed(struct zs_chanstate *cs, int bps /*bits per second*/) 457 { 458 int tconst, real_bps; 459 460 if (bps == 0) 461 return (0); 462 463 #ifdef DIAGNOSTIC 464 if (cs->cs_brg_clk == 0) 465 panic("zs_set_speed"); 466 #endif 467 468 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 469 if (tconst < 0) 470 return (EINVAL); 471 472 /* Convert back to make sure we can do it. */ 473 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 474 475 /* XXX - Allow some tolerance here? */ 476 if (real_bps != bps) 477 return (EINVAL); 478 479 cs->cs_preg[12] = tconst; 480 cs->cs_preg[13] = tconst >> 8; 481 482 /* Caller will stuff the pending registers. */ 483 return (0); 484 } 485 486 int 487 zs_set_modes(struct zs_chanstate *cs, int cflag) 488 { 489 u_long privflags = (u_long)cs->cs_private; 490 int s; 491 492 /* 493 * Output hardware flow control on the chip is horrendous: 494 * if carrier detect drops, the receiver is disabled, and if 495 * CTS drops, the transmitter is stoped IN MID CHARACTER! 496 * Therefore, NEVER set the HFC bit, and instead use the 497 * status interrupt to detect CTS changes. 498 */ 499 s = splzs(); 500 if ((cflag & (CLOCAL | MDMBUF)) != 0) 501 cs->cs_rr0_dcd = 0; 502 else 503 cs->cs_rr0_dcd = ZSRR0_DCD; 504 if ((cflag & CRTSCTS) != 0) { 505 cs->cs_wr5_dtr = ZSWR5_DTR; 506 cs->cs_wr5_rts = ZSWR5_RTS; 507 cs->cs_rr0_cts = ZSRR0_CTS; 508 } else if ((cflag & CDTRCTS) != 0) { 509 cs->cs_wr5_dtr = 0; 510 cs->cs_wr5_rts = ZSWR5_DTR; 511 cs->cs_rr0_cts = ZSRR0_CTS; 512 } else if ((cflag & MDMBUF) != 0) { 513 cs->cs_wr5_dtr = 0; 514 cs->cs_wr5_rts = ZSWR5_DTR; 515 cs->cs_rr0_cts = ZSRR0_DCD; 516 } else { 517 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 518 cs->cs_wr5_rts = 0; 519 cs->cs_rr0_cts = 0; 520 } 521 522 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 523 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 524 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 525 } 526 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) { 527 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR); 528 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR); 529 } 530 splx(s); 531 532 /* Caller will stuff the pending registers. */ 533 return (0); 534 } 535 536 /* 537 * Functions to read and write individual registers in a channel. 538 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 539 * and the Alpha TC hardware does NOT take care of this for you. 540 * The delay is now handled inside the chip access functions. 541 * These could be inlines, but with the delay, speed is moot. 542 */ 543 #if defined(pmax) 544 #undef DELAY 545 #define DELAY(x) 546 #endif 547 548 u_int 549 zs_read_reg(struct zs_chanstate *cs, u_int reg) 550 { 551 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 552 unsigned val; 553 554 zc->zc_csr = reg << 8; 555 tc_wmb(); 556 DELAY(5); 557 val = (zc->zc_csr >> 8) & 0xff; 558 /* tc_mb(); */ 559 DELAY(5); 560 return (val); 561 } 562 563 void 564 zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val) 565 { 566 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 567 568 zc->zc_csr = reg << 8; 569 tc_wmb(); 570 DELAY(5); 571 zc->zc_csr = val << 8; 572 tc_wmb(); 573 DELAY(5); 574 } 575 576 u_int 577 zs_read_csr(struct zs_chanstate *cs) 578 { 579 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 580 unsigned val; 581 582 val = (zc->zc_csr >> 8) & 0xff; 583 /* tc_mb(); */ 584 DELAY(5); 585 return (val); 586 } 587 588 void 589 zs_write_csr(struct zs_chanstate *cs, u_int val) 590 { 591 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 592 593 zc->zc_csr = val << 8; 594 tc_wmb(); 595 DELAY(5); 596 } 597 598 u_int 599 zs_read_data(struct zs_chanstate *cs) 600 { 601 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 602 unsigned val; 603 604 val = (zc->zc_data) >> 8 & 0xff; 605 /* tc_mb(); */ 606 DELAY(5); 607 return (val); 608 } 609 610 void 611 zs_write_data(struct zs_chanstate *cs, u_int val) 612 { 613 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 614 615 zc->zc_data = val << 8; 616 tc_wmb(); 617 DELAY(5); 618 } 619 620 /**************************************************************** 621 * Console support functions 622 ****************************************************************/ 623 624 /* 625 * Handle user request to enter kernel debugger. 626 */ 627 void 628 zs_abort(struct zs_chanstate *cs) 629 { 630 int rr0; 631 632 /* Wait for end of break. */ 633 /* XXX - Limit the wait? */ 634 do { 635 rr0 = zs_read_csr(cs); 636 } while (rr0 & ZSRR0_BREAK); 637 638 #if defined(KGDB) 639 zskgdb(cs); 640 #elif defined(DDB) 641 Debugger(); 642 #else 643 printf("zs_abort: ignoring break on console\n"); 644 #endif 645 } 646 647 /* 648 * Polled input char. 649 */ 650 int 651 zs_getc(struct zs_chanstate *cs) 652 { 653 int s, c, rr0; 654 655 s = splhigh(); 656 /* Wait for a character to arrive. */ 657 do { 658 rr0 = zs_read_csr(cs); 659 } while ((rr0 & ZSRR0_RX_READY) == 0); 660 661 c = zs_read_data(cs); 662 splx(s); 663 664 /* 665 * This is used by the kd driver to read scan codes, 666 * so don't translate '\r' ==> '\n' here... 667 */ 668 return (c); 669 } 670 671 /* 672 * Polled output char. 673 */ 674 static void 675 zs_putc(struct zs_chanstate *cs, int c) 676 { 677 register int s, rr0; 678 679 s = splhigh(); 680 /* Wait for transmitter to become ready. */ 681 do { 682 rr0 = zs_read_csr(cs); 683 } while ((rr0 & ZSRR0_TX_READY) == 0); 684 685 zs_write_data(cs, c); 686 687 /* Wait for the character to be transmitted. */ 688 do { 689 rr0 = zs_read_csr(cs); 690 } while ((rr0 & ZSRR0_TX_READY) == 0); 691 splx(s); 692 } 693 694 /*****************************************************************/ 695 696 /* 697 * zs_ioasic_cninit -- 698 * Initialize the serial channel for either a keyboard or 699 * a serial console. 700 */ 701 static void 702 zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 703 { 704 struct zs_chanstate *cs; 705 tc_addr_t zs_addr; 706 struct zshan *zc; 707 u_long zflg; 708 709 /* 710 * Initialize the console finder helpers. 711 */ 712 zs_ioasic_console_offset = zs_offset; 713 zs_ioasic_console_channel = channel; 714 zs_ioasic_console = 1; 715 716 /* 717 * Pointer to channel state. 718 */ 719 cs = &zs_ioasic_conschanstate_store; 720 721 /* 722 * Compute the physical address of the chip, "map" it via 723 * K0SEG, and then get the address of the actual channel. 724 */ 725 #if defined(__alpha__) || defined(alpha) 726 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 727 #endif 728 #if defined(pmax) 729 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 730 #endif 731 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 732 733 /* Setup temporary chanstate. */ 734 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 735 736 cs->cs_channel = channel; 737 cs->cs_ops = &zsops_null; 738 cs->cs_brg_clk = PCLK / 16; 739 740 /* Initialize the pending registers. */ 741 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 742 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */ 743 744 /* 745 * DCD and CTS interrupts are only meaningful on 746 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 747 * 748 * XXX This is sorta gross. 749 */ 750 if (zs_offset == 0x00100000 && channel == 1) 751 zflg = ZIP_FLAGS_DCDCTS; 752 else 753 zflg = 0; 754 if (channel == 1) 755 zflg |= ZIP_FLAGS_DTRRTS; 756 cs->cs_private = (void *)zflg; 757 758 /* Clear the master interrupt enable. */ 759 zs_write_reg(cs, 9, 0); 760 761 /* Reset the whole SCC chip. */ 762 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 763 764 /* Copy "pending" to "current" and H/W. */ 765 zs_loadchannelregs(cs); 766 } 767 768 /* 769 * zs_ioasic_cnattach -- 770 * Initialize and attach a serial console. 771 */ 772 void 773 zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 774 { 775 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 776 extern const struct cdevsw zstty_cdevsw; 777 778 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 779 cs->cs_defspeed = 9600; 780 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 781 782 /* Point the console at the SCC. */ 783 cn_tab = &zs_ioasic_cons; 784 cn_tab->cn_pri = CN_REMOTE; 785 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 786 (zs_offset == 0x100000) ? 0 : 1); 787 } 788 789 /* 790 * zs_ioasic_lk201_cnattach -- 791 * Initialize and attach a keyboard. 792 */ 793 int 794 zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, 795 int channel) 796 { 797 #if (NZSKBD > 0) 798 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 799 800 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 801 cs->cs_defspeed = 4800; 802 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 803 return (zskbd_cnattach(cs)); 804 #else 805 return (ENXIO); 806 #endif 807 } 808 809 static int 810 zs_ioasic_isconsole(tc_offset_t offset, int channel) 811 { 812 813 if (zs_ioasic_console && 814 offset == zs_ioasic_console_offset && 815 channel == zs_ioasic_console_channel) 816 return (1); 817 818 return (0); 819 } 820 821 /* 822 * Polled console input putchar. 823 */ 824 static int 825 zs_ioasic_cngetc(dev_t dev) 826 { 827 828 return (zs_getc(&zs_ioasic_conschanstate_store)); 829 } 830 831 /* 832 * Polled console output putchar. 833 */ 834 static void 835 zs_ioasic_cnputc(dev_t dev, int c) 836 { 837 838 zs_putc(&zs_ioasic_conschanstate_store, c); 839 } 840 841 /* 842 * Set polling/no polling on console. 843 */ 844 static void 845 zs_ioasic_cnpollc(dev_t dev, int onoff) 846 { 847 848 /* XXX ??? */ 849 } 850