1 /* $NetBSD: zs_ioasic.c,v 1.46 2022/07/20 14:19:38 thorpej Exp $ */
2
3 /*-
4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the
9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 * POSSIBILITY OF SUCH DAMAGE.
31 */
32
33 /*
34 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver
35 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified
36 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax
37 * adaption by Mattias Drochner. Merge work by Tohru Nishimura.
38 *
39 * Runs two serial lines per chip using slave drivers.
40 * Plain tty/async lines use the zstty slave.
41 */
42
43 #include <sys/cdefs.h>
44 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.46 2022/07/20 14:19:38 thorpej Exp $");
45
46 #include "opt_ddb.h"
47 #include "opt_kgdb.h"
48 #include "zskbd.h"
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/conf.h>
53 #include <sys/device.h>
54 #include <sys/malloc.h>
55 #include <sys/file.h>
56 #include <sys/ioctl.h>
57 #include <sys/kernel.h>
58 #include <sys/proc.h>
59 #include <sys/tty.h>
60 #include <sys/time.h>
61 #include <sys/syslog.h>
62 #include <sys/intr.h>
63
64 #include <machine/autoconf.h>
65 #include <machine/z8530var.h>
66
67 #include <dev/cons.h>
68 #include <dev/ic/z8530reg.h>
69
70 #include <dev/tc/tcvar.h>
71 #include <dev/tc/ioasicreg.h>
72 #include <dev/tc/ioasicvar.h>
73
74 #include <dev/tc/zs_ioasicvar.h>
75
76 #if defined(__alpha__)
77 #include <machine/rpb.h>
78 #endif
79 #if defined(pmax)
80 #include <pmax/pmax/pmaxtype.h>
81 #endif
82
83 /*
84 * Helpers for console support.
85 */
86 static void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int);
87 static int zs_ioasic_cngetc(dev_t);
88 static void zs_ioasic_cnputc(dev_t, int);
89 static void zs_ioasic_cnpollc(dev_t, int);
90
91 struct consdev zs_ioasic_cons = {
92 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc,
93 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL,
94 };
95
96 static tc_offset_t zs_ioasic_console_offset;
97 static int zs_ioasic_console_channel;
98 static int zs_ioasic_console;
99 static struct zs_chanstate zs_ioasic_conschanstate_store;
100
101 static int zs_ioasic_isconsole(tc_offset_t, int);
102 static void zs_putc(struct zs_chanstate *, int);
103
104 /*
105 * Some warts needed by z8530tty.c
106 */
107 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
108
109 /*
110 * ZS chips are fed a 7.372 MHz clock.
111 */
112 #define PCLK (9600 * 768) /* PCLK pin input clock rate */
113
114 /* The layout of this is hardware-dependent (padding, order). */
115 struct zshan {
116 #if defined(__alpha__)
117 volatile u_int zc_csr; /* ctrl,status, and indirect access */
118 u_int zc_pad0;
119 volatile u_int zc_data; /* data */
120 u_int sc_pad1;
121 #endif
122 #if defined(pmax)
123 volatile uint16_t zc_csr; /* ctrl,status, and indirect access */
124 unsigned : 16;
125 volatile uint16_t zc_data; /* data */
126 unsigned : 16;
127 #endif
128 };
129
130 struct zsdevice {
131 /* Yes, they are backwards. */
132 struct zshan zs_chan_b;
133 struct zshan zs_chan_a;
134 };
135
136 static const u_char zs_ioasic_init_reg[16] = {
137 0, /* 0: CMD (reset, etc.) */
138 0, /* 1: No interrupts yet. */
139 0xf0, /* 2: IVECT */
140 ZSWR3_RX_8 | ZSWR3_RX_ENABLE,
141 ZSWR4_CLK_X16 | ZSWR4_ONESB,
142 ZSWR5_TX_8 | ZSWR5_TX_ENABLE,
143 0, /* 6: TXSYNC/SYNCLO */
144 0, /* 7: RXSYNC/SYNCHI */
145 0, /* 8: alias for data port */
146 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT,
147 0, /*10: Misc. TX/RX control bits */
148 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD,
149 22, /*12: BAUDLO (default=9600) */
150 0, /*13: BAUDHI (default=9600) */
151 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK,
152 ZSWR15_BREAK_IE,
153 };
154
155 static struct zshan *
zs_ioasic_get_chan_addr(tc_addr_t zsaddr,int channel)156 zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel)
157 {
158 struct zsdevice *addr;
159 struct zshan *zc;
160
161 #if defined(__alpha__)
162 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr);
163 #endif
164 #if defined(pmax)
165 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr);
166 #endif
167
168 if (channel == 0)
169 zc = &addr->zs_chan_a;
170 else
171 zc = &addr->zs_chan_b;
172
173 return (zc);
174 }
175
176
177 /****************************************************************
178 * Autoconfig
179 ****************************************************************/
180
181 /* Definition of the driver for autoconfig. */
182 static int zs_ioasic_match(device_t, cfdata_t, void *);
183 static void zs_ioasic_attach(device_t, device_t, void *);
184 static int zs_ioasic_print(void *, const char *name);
185 static int zs_ioasic_submatch(device_t, cfdata_t,
186 const int *, void *);
187
188 CFATTACH_DECL_NEW(zsc_ioasic, sizeof(struct zsc_softc),
189 zs_ioasic_match, zs_ioasic_attach, NULL, NULL);
190
191 /* Interrupt handlers. */
192 static int zs_ioasic_hardintr(void *);
193 static void zs_ioasic_softintr(void *);
194
195 /*
196 * Is the zs chip present?
197 */
198 static int
zs_ioasic_match(device_t parent,cfdata_t cf,void * aux)199 zs_ioasic_match(device_t parent, cfdata_t cf, void *aux)
200 {
201 struct ioasicdev_attach_args *d = aux;
202 tc_addr_t zs_addr;
203
204 /*
205 * Make sure that we're looking for the right kind of device.
206 */
207 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 &&
208 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0)
209 return (0);
210
211 /*
212 * Find out the device address, and check it for validity.
213 */
214 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr);
215 if (tc_badaddr(zs_addr))
216 return (0);
217
218 return (1);
219 }
220
221 /*
222 * Attach a found zs.
223 */
224 static void
zs_ioasic_attach(device_t parent,device_t self,void * aux)225 zs_ioasic_attach(device_t parent, device_t self, void *aux)
226 {
227 struct zsc_softc *zs = device_private(self);
228 struct zsc_attach_args zs_args;
229 struct zs_chanstate *cs;
230 struct ioasicdev_attach_args *d = aux;
231 struct zshan *zc;
232 int s, channel;
233 u_long zflg;
234 int locs[ZSCCF_NLOCS];
235
236 zs->zsc_dev = self;
237 aprint_normal("\n");
238
239 /*
240 * Initialize software state for each channel.
241 */
242 for (channel = 0; channel < 2; channel++) {
243 zs_args.channel = channel;
244 zs_args.hwflags = 0;
245
246 if (zs_ioasic_isconsole(d->iada_offset, channel)) {
247 cs = &zs_ioasic_conschanstate_store;
248 zs_args.hwflags |= ZS_HWFLAG_CONSOLE;
249 } else {
250 cs = malloc(sizeof(struct zs_chanstate),
251 M_DEVBUF, M_WAITOK | M_ZERO);
252 zs_lock_init(cs);
253 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel);
254 cs->cs_reg_csr = (volatile void *)&zc->zc_csr;
255
256 memcpy(cs->cs_creg, zs_ioasic_init_reg, 16);
257 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);
258
259 cs->cs_defcflag = zs_def_cflag;
260 cs->cs_defspeed = 9600; /* XXX */
261 (void)zs_set_modes(cs, cs->cs_defcflag);
262 }
263
264 zs->zsc_cs[channel] = cs;
265 zs->zsc_addroffset = d->iada_offset; /* cookie only */
266 cs->cs_channel = channel;
267 cs->cs_ops = &zsops_null;
268 cs->cs_brg_clk = PCLK / 16;
269
270 /*
271 * DCD and CTS interrupts are only meaningful on
272 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
273 *
274 * XXX This is sorta gross.
275 */
276 if (d->iada_offset == 0x00100000 && channel == 1) {
277 cs->cs_creg[15] |= ZSWR15_DCD_IE;
278 cs->cs_preg[15] |= ZSWR15_DCD_IE;
279 zflg = ZIP_FLAGS_DCDCTS;
280 } else
281 zflg = 0;
282 if (channel == 1)
283 zflg |= ZIP_FLAGS_DTRRTS;
284 cs->cs_private = (void *)zflg;
285
286 /*
287 * Clear the master interrupt enable.
288 * The INTENA is common to both channels,
289 * so just do it on the A channel.
290 */
291 if (channel == 0) {
292 zs_write_reg(cs, 9, 0);
293 }
294
295 /*
296 * Set up the flow/modem control channel pointer to
297 * deal with the weird wiring on the TC Alpha and
298 * DECstation.
299 */
300 if (channel == 1)
301 cs->cs_ctl_chan = zs->zsc_cs[0];
302 else
303 cs->cs_ctl_chan = NULL;
304
305 locs[ZSCCF_CHANNEL] = channel;
306
307 /*
308 * Look for a child driver for this channel.
309 * The child attach will setup the hardware.
310 */
311 if (config_found(self, (void *)&zs_args, zs_ioasic_print,
312 CFARGS(.submatch = zs_ioasic_submatch,
313 .locators = locs)) == NULL) {
314 /* No sub-driver. Just reset it. */
315 uint8_t reset = (channel == 0) ?
316 ZSWR9_A_RESET : ZSWR9_B_RESET;
317 s = splhigh();
318 zs_write_reg(cs, 9, reset);
319 splx(s);
320 }
321 }
322
323 /*
324 * Set up the ioasic interrupt handler.
325 */
326 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY,
327 zs_ioasic_hardintr, zs);
328 zs->zsc_sih = softint_establish(SOFTINT_SERIAL,
329 zs_ioasic_softintr, zs);
330 if (zs->zsc_sih == NULL)
331 panic("%s: unable to register softintr", __func__);
332
333 /*
334 * Set the master interrupt enable and interrupt vector. The
335 * Sun does this only on one channel. The old Alpha SCC driver
336 * did it on both. We'll do it on both.
337 */
338 s = splhigh();
339 /* interrupt vector */
340 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]);
341 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]);
342
343 /* master interrupt control (enable) */
344 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]);
345 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]);
346 #if defined(__alpha__)
347 /* ioasic interrupt enable */
348 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |=
349 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0;
350 tc_mb();
351 #endif
352 splx(s);
353 }
354
355 static int
zs_ioasic_print(void * aux,const char * name)356 zs_ioasic_print(void *aux, const char *name)
357 {
358 struct zsc_attach_args *args = aux;
359
360 if (name != NULL)
361 aprint_normal("%s:", name);
362
363 if (args->channel != -1)
364 aprint_normal(" channel %d", args->channel);
365
366 return (UNCONF);
367 }
368
369 static int
zs_ioasic_submatch(device_t parent,cfdata_t cf,const int * locs,void * aux)370 zs_ioasic_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux)
371 {
372 struct zsc_softc *zs = device_private(parent);
373 struct zsc_attach_args *pa = aux;
374 const char *defname = "";
375
376 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT &&
377 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL])
378 return (0);
379
380 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) {
381 if (pa->channel == 0) {
382 #if defined(pmax)
383 if (systype == DS_MAXINE)
384 return (0);
385 #endif
386 if (zs->zsc_addroffset == 0x100000)
387 defname = "vsms";
388 else
389 defname = "lkkbd";
390 }
391 else if (zs->zsc_addroffset == 0x100000)
392 defname = "zstty";
393 #if defined(pmax)
394 else if (systype == DS_MAXINE)
395 return (0);
396 #endif
397 #if defined(__alpha__)
398 else if (cputype == ST_DEC_3000_300)
399 return (0);
400 #endif
401 else
402 defname = "zstty"; /* 3min/3max+, DEC3000/500 */
403
404 if (strcmp(cf->cf_name, defname))
405 return (0);
406 }
407 return (config_match(parent, cf, aux));
408 }
409
410 /*
411 * Hardware interrupt handler.
412 */
413 static int
zs_ioasic_hardintr(void * arg)414 zs_ioasic_hardintr(void *arg)
415 {
416 struct zsc_softc *zsc = arg;
417
418 /*
419 * Call the upper-level MI hardware interrupt handler.
420 */
421 zsc_intr_hard(zsc);
422
423 /*
424 * Check to see if we need to schedule any software-level
425 * processing interrupts.
426 */
427 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq)
428 softint_schedule(zsc->zsc_sih);
429
430 return (1);
431 }
432
433 /*
434 * Software-level interrupt (character processing, lower priority).
435 */
436 static void
zs_ioasic_softintr(void * arg)437 zs_ioasic_softintr(void *arg)
438 {
439 struct zsc_softc *zsc = arg;
440 int s;
441
442 s = spltty();
443 (void)zsc_intr_soft(zsc);
444 splx(s);
445 }
446
447 /*
448 * MD functions for setting the baud rate and control modes.
449 */
450 int
zs_set_speed(struct zs_chanstate * cs,int bps)451 zs_set_speed(struct zs_chanstate *cs, int bps /*bits per second*/)
452 {
453 int tconst, real_bps;
454
455 if (bps == 0)
456 return (0);
457
458 #ifdef DIAGNOSTIC
459 if (cs->cs_brg_clk == 0)
460 panic("zs_set_speed");
461 #endif
462
463 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps);
464 if (tconst < 0)
465 return (EINVAL);
466
467 /* Convert back to make sure we can do it. */
468 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst);
469
470 /* XXX - Allow some tolerance here? */
471 if (real_bps != bps)
472 return (EINVAL);
473
474 cs->cs_preg[12] = tconst;
475 cs->cs_preg[13] = tconst >> 8;
476
477 /* Caller will stuff the pending registers. */
478 return (0);
479 }
480
481 int
zs_set_modes(struct zs_chanstate * cs,int cflag)482 zs_set_modes(struct zs_chanstate *cs, int cflag)
483 {
484 u_long privflags = (u_long)cs->cs_private;
485 int s;
486
487 /*
488 * Output hardware flow control on the chip is horrendous:
489 * if carrier detect drops, the receiver is disabled, and if
490 * CTS drops, the transmitter is stopped IN MID CHARACTER!
491 * Therefore, NEVER set the HFC bit, and instead use the
492 * status interrupt to detect CTS changes.
493 */
494 s = splzs();
495 if ((cflag & (CLOCAL | MDMBUF)) != 0)
496 cs->cs_rr0_dcd = 0;
497 else
498 cs->cs_rr0_dcd = ZSRR0_DCD;
499 if ((cflag & CRTSCTS) != 0) {
500 cs->cs_wr5_dtr = ZSWR5_DTR;
501 cs->cs_wr5_rts = ZSWR5_RTS;
502 cs->cs_rr0_cts = ZSRR0_CTS;
503 } else if ((cflag & CDTRCTS) != 0) {
504 cs->cs_wr5_dtr = 0;
505 cs->cs_wr5_rts = ZSWR5_DTR;
506 cs->cs_rr0_cts = ZSRR0_CTS;
507 } else if ((cflag & MDMBUF) != 0) {
508 cs->cs_wr5_dtr = 0;
509 cs->cs_wr5_rts = ZSWR5_DTR;
510 cs->cs_rr0_cts = ZSRR0_DCD;
511 } else {
512 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS;
513 cs->cs_wr5_rts = 0;
514 cs->cs_rr0_cts = 0;
515 }
516
517 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) {
518 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD);
519 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD);
520 }
521 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) {
522 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR);
523 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR);
524 }
525 splx(s);
526
527 /* Caller will stuff the pending registers. */
528 return (0);
529 }
530
531 /*
532 * Functions to read and write individual registers in a channel.
533 * The ZS chip requires a 1.6 uSec. recovery time between accesses,
534 * and the Alpha TC hardware does NOT take care of this for you.
535 * The delay is now handled inside the chip access functions.
536 * These could be inlines, but with the delay, speed is moot.
537 */
538 #if defined(pmax)
539 #undef DELAY
540 #define DELAY(x)
541 #endif
542
543 u_int
zs_read_reg(struct zs_chanstate * cs,u_int reg)544 zs_read_reg(struct zs_chanstate *cs, u_int reg)
545 {
546 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
547 unsigned val;
548
549 zc->zc_csr = reg << 8;
550 tc_wmb();
551 DELAY(5);
552 val = (zc->zc_csr >> 8) & 0xff;
553 /* tc_mb(); */
554 DELAY(5);
555 return (val);
556 }
557
558 void
zs_write_reg(struct zs_chanstate * cs,u_int reg,u_int val)559 zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val)
560 {
561 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
562
563 zc->zc_csr = reg << 8;
564 tc_wmb();
565 DELAY(5);
566 zc->zc_csr = val << 8;
567 tc_wmb();
568 DELAY(5);
569 }
570
571 u_int
zs_read_csr(struct zs_chanstate * cs)572 zs_read_csr(struct zs_chanstate *cs)
573 {
574 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
575 unsigned val;
576
577 val = (zc->zc_csr >> 8) & 0xff;
578 /* tc_mb(); */
579 DELAY(5);
580 return (val);
581 }
582
583 void
zs_write_csr(struct zs_chanstate * cs,u_int val)584 zs_write_csr(struct zs_chanstate *cs, u_int val)
585 {
586 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
587
588 zc->zc_csr = val << 8;
589 tc_wmb();
590 DELAY(5);
591 }
592
593 u_int
zs_read_data(struct zs_chanstate * cs)594 zs_read_data(struct zs_chanstate *cs)
595 {
596 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
597 unsigned val;
598
599 val = (zc->zc_data) >> 8 & 0xff;
600 /* tc_mb(); */
601 DELAY(5);
602 return (val);
603 }
604
605 void
zs_write_data(struct zs_chanstate * cs,u_int val)606 zs_write_data(struct zs_chanstate *cs, u_int val)
607 {
608 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr;
609
610 zc->zc_data = val << 8;
611 tc_wmb();
612 DELAY(5);
613 }
614
615 /****************************************************************
616 * Console support functions
617 ****************************************************************/
618
619 /*
620 * Handle user request to enter kernel debugger.
621 */
622 void
zs_abort(struct zs_chanstate * cs)623 zs_abort(struct zs_chanstate *cs)
624 {
625 u_int rr0;
626
627 /* Wait for end of break. */
628 /* XXX - Limit the wait? */
629 do {
630 rr0 = zs_read_csr(cs);
631 } while (rr0 & ZSRR0_BREAK);
632
633 #if defined(KGDB)
634 zskgdb(cs);
635 #elif defined(DDB)
636 Debugger();
637 #else
638 printf("zs_abort: ignoring break on console\n");
639 #endif
640 }
641
642 /*
643 * Polled input char.
644 */
645 int
zs_getc(struct zs_chanstate * cs)646 zs_getc(struct zs_chanstate *cs)
647 {
648 int s, c;
649 u_int rr0;
650
651 s = splhigh();
652 /* Wait for a character to arrive. */
653 do {
654 rr0 = zs_read_csr(cs);
655 } while ((rr0 & ZSRR0_RX_READY) == 0);
656
657 c = zs_read_data(cs);
658 splx(s);
659
660 /*
661 * This is used by the kd driver to read scan codes,
662 * so don't translate '\r' ==> '\n' here...
663 */
664 return (c);
665 }
666
667 /*
668 * Polled output char.
669 */
670 static void
zs_putc(struct zs_chanstate * cs,int c)671 zs_putc(struct zs_chanstate *cs, int c)
672 {
673 int s;
674 u_int rr0;
675
676 s = splhigh();
677 /* Wait for transmitter to become ready. */
678 do {
679 rr0 = zs_read_csr(cs);
680 } while ((rr0 & ZSRR0_TX_READY) == 0);
681
682 zs_write_data(cs, c);
683
684 /* Wait for the character to be transmitted. */
685 do {
686 rr0 = zs_read_csr(cs);
687 } while ((rr0 & ZSRR0_TX_READY) == 0);
688 splx(s);
689 }
690
691 /*****************************************************************/
692
693 /*
694 * zs_ioasic_cninit --
695 * Initialize the serial channel for either a keyboard or
696 * a serial console.
697 */
698 static void
zs_ioasic_cninit(tc_addr_t ioasic_addr,tc_offset_t zs_offset,int channel)699 zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel)
700 {
701 struct zs_chanstate *cs;
702 tc_addr_t zs_addr;
703 struct zshan *zc;
704 u_long zflg;
705
706 /*
707 * Initialize the console finder helpers.
708 */
709 zs_ioasic_console_offset = zs_offset;
710 zs_ioasic_console_channel = channel;
711 zs_ioasic_console = 1;
712
713 /*
714 * Pointer to channel state.
715 */
716 cs = &zs_ioasic_conschanstate_store;
717
718 /*
719 * Compute the physical address of the chip, "map" it via
720 * K0SEG, and then get the address of the actual channel.
721 */
722 #if defined(__alpha__)
723 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset);
724 #endif
725 #if defined(pmax)
726 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset);
727 #endif
728 zc = zs_ioasic_get_chan_addr(zs_addr, channel);
729
730 /* Setup temporary chanstate. */
731 cs->cs_reg_csr = (volatile void *)&zc->zc_csr;
732
733 cs->cs_channel = channel;
734 cs->cs_ops = &zsops_null;
735 cs->cs_brg_clk = PCLK / 16;
736
737 /* Initialize the pending registers. */
738 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16);
739 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */
740
741 /*
742 * DCD and CTS interrupts are only meaningful on
743 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1.
744 *
745 * XXX This is sorta gross.
746 */
747 if (zs_offset == 0x00100000 && channel == 1)
748 zflg = ZIP_FLAGS_DCDCTS;
749 else
750 zflg = 0;
751 if (channel == 1)
752 zflg |= ZIP_FLAGS_DTRRTS;
753 cs->cs_private = (void *)zflg;
754
755 /* Clear the master interrupt enable. */
756 zs_write_reg(cs, 9, 0);
757
758 /* Reset the whole SCC chip. */
759 zs_write_reg(cs, 9, ZSWR9_HARD_RESET);
760
761 /* Copy "pending" to "current" and H/W. */
762 zs_loadchannelregs(cs);
763 }
764
765 /*
766 * zs_ioasic_cnattach --
767 * Initialize and attach a serial console.
768 */
769 void
zs_ioasic_cnattach(tc_addr_t ioasic_addr,tc_offset_t zs_offset,int channel)770 zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel)
771 {
772 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
773 extern const struct cdevsw zstty_cdevsw;
774
775 zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
776 zs_lock_init(cs);
777 cs->cs_defspeed = 9600;
778 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
779
780 /* Point the console at the SCC. */
781 cn_tab = &zs_ioasic_cons;
782 cn_tab->cn_pri = CN_REMOTE;
783 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw),
784 (zs_offset == 0x100000) ? 0 : 1);
785 }
786
787 /*
788 * zs_ioasic_lk201_cnattach --
789 * Initialize and attach a keyboard.
790 */
791 int
zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr,tc_offset_t zs_offset,int channel)792 zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset,
793 int channel)
794 {
795 #if (NZSKBD > 0)
796 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store;
797
798 zs_ioasic_cninit(ioasic_addr, zs_offset, channel);
799 zs_lock_init(cs);
800 cs->cs_defspeed = 4800;
801 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8;
802 return (zskbd_cnattach(cs));
803 #else
804 return (ENXIO);
805 #endif
806 }
807
808 static int
zs_ioasic_isconsole(tc_offset_t offset,int channel)809 zs_ioasic_isconsole(tc_offset_t offset, int channel)
810 {
811
812 if (zs_ioasic_console &&
813 offset == zs_ioasic_console_offset &&
814 channel == zs_ioasic_console_channel)
815 return (1);
816
817 return (0);
818 }
819
820 /*
821 * Polled console input putchar.
822 */
823 static int
zs_ioasic_cngetc(dev_t dev)824 zs_ioasic_cngetc(dev_t dev)
825 {
826
827 return (zs_getc(&zs_ioasic_conschanstate_store));
828 }
829
830 /*
831 * Polled console output putchar.
832 */
833 static void
zs_ioasic_cnputc(dev_t dev,int c)834 zs_ioasic_cnputc(dev_t dev, int c)
835 {
836
837 zs_putc(&zs_ioasic_conschanstate_store, c);
838 }
839
840 /*
841 * Set polling/no polling on console.
842 */
843 static void
zs_ioasic_cnpollc(dev_t dev,int onoff)844 zs_ioasic_cnpollc(dev_t dev, int onoff)
845 {
846
847 /* XXX ??? */
848 }
849