1 /* $NetBSD: zs_ioasic.c,v 1.29 2005/12/11 12:24:00 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 42 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 43 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 44 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 45 * 46 * Runs two serial lines per chip using slave drivers. 47 * Plain tty/async lines use the zstty slave. 48 */ 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.29 2005/12/11 12:24:00 christos Exp $"); 52 53 #include "opt_ddb.h" 54 #include "opt_kgdb.h" 55 #include "zskbd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/conf.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/file.h> 63 #include <sys/ioctl.h> 64 #include <sys/kernel.h> 65 #include <sys/proc.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/syslog.h> 69 70 #include <machine/autoconf.h> 71 #include <machine/intr.h> 72 #include <machine/z8530var.h> 73 74 #include <dev/cons.h> 75 #include <dev/ic/z8530reg.h> 76 77 #include <dev/tc/tcvar.h> 78 #include <dev/tc/ioasicreg.h> 79 #include <dev/tc/ioasicvar.h> 80 81 #include <dev/tc/zs_ioasicvar.h> 82 83 #if defined(__alpha__) || defined(alpha) 84 #include <machine/rpb.h> 85 #endif 86 #if defined(pmax) 87 #include <pmax/pmax/pmaxtype.h> 88 #endif 89 90 /* 91 * Helpers for console support. 92 */ 93 void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int); 94 int zs_ioasic_cngetc(dev_t); 95 void zs_ioasic_cnputc(dev_t, int); 96 void zs_ioasic_cnpollc(dev_t, int); 97 98 struct consdev zs_ioasic_cons = { 99 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 100 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL, 101 }; 102 103 tc_offset_t zs_ioasic_console_offset; 104 int zs_ioasic_console_channel; 105 int zs_ioasic_console; 106 struct zs_chanstate zs_ioasic_conschanstate_store; 107 108 int zs_ioasic_isconsole(tc_offset_t, int); 109 int zs_getc(struct zs_chanstate *); 110 void zs_putc(struct zs_chanstate *, int); 111 112 /* 113 * Some warts needed by z8530tty.c 114 */ 115 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 116 117 /* 118 * ZS chips are feeded a 7.372 MHz clock. 119 */ 120 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 121 122 /* The layout of this is hardware-dependent (padding, order). */ 123 struct zshan { 124 #if defined(__alpha__) || defined(alpha) 125 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 126 u_int zc_pad0; 127 volatile u_int zc_data; /* data */ 128 u_int sc_pad1; 129 #endif 130 #if defined(pmax) 131 volatile u_int16_t zc_csr; /* ctrl,status, and indirect access */ 132 unsigned : 16; 133 volatile u_int16_t zc_data; /* data */ 134 unsigned : 16; 135 #endif 136 }; 137 138 struct zsdevice { 139 /* Yes, they are backwards. */ 140 struct zshan zs_chan_b; 141 struct zshan zs_chan_a; 142 }; 143 144 static u_char zs_ioasic_init_reg[16] = { 145 0, /* 0: CMD (reset, etc.) */ 146 0, /* 1: No interrupts yet. */ 147 0xf0, /* 2: IVECT */ 148 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 149 ZSWR4_CLK_X16 | ZSWR4_ONESB, 150 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 151 0, /* 6: TXSYNC/SYNCLO */ 152 0, /* 7: RXSYNC/SYNCHI */ 153 0, /* 8: alias for data port */ 154 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 155 0, /*10: Misc. TX/RX control bits */ 156 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 157 22, /*12: BAUDLO (default=9600) */ 158 0, /*13: BAUDHI (default=9600) */ 159 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 160 ZSWR15_BREAK_IE, 161 }; 162 163 struct zshan *zs_ioasic_get_chan_addr(tc_addr_t, int); 164 165 struct zshan * 166 zs_ioasic_get_chan_addr(zsaddr, channel) 167 tc_addr_t zsaddr; 168 int channel; 169 { 170 struct zsdevice *addr; 171 struct zshan *zc; 172 173 #if defined(__alpha__) || defined(alpha) 174 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 175 #endif 176 #if defined(pmax) 177 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 178 #endif 179 180 if (channel == 0) 181 zc = &addr->zs_chan_a; 182 else 183 zc = &addr->zs_chan_b; 184 185 return (zc); 186 } 187 188 189 /**************************************************************** 190 * Autoconfig 191 ****************************************************************/ 192 193 /* Definition of the driver for autoconfig. */ 194 int zs_ioasic_match(struct device *, struct cfdata *, void *); 195 void zs_ioasic_attach(struct device *, struct device *, void *); 196 int zs_ioasic_print(void *, const char *name); 197 int zs_ioasic_submatch(struct device *, struct cfdata *, 198 const int *, void *); 199 200 CFATTACH_DECL(zsc_ioasic, sizeof(struct zsc_softc), 201 zs_ioasic_match, zs_ioasic_attach, NULL, NULL); 202 203 /* Interrupt handlers. */ 204 int zs_ioasic_hardintr(void *); 205 void zs_ioasic_softintr(void *); 206 207 /* 208 * Is the zs chip present? 209 */ 210 int 211 zs_ioasic_match(parent, cf, aux) 212 struct device *parent; 213 struct cfdata *cf; 214 void *aux; 215 { 216 struct ioasicdev_attach_args *d = aux; 217 tc_addr_t zs_addr; 218 219 /* 220 * Make sure that we're looking for the right kind of device. 221 */ 222 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 223 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 224 return (0); 225 226 /* 227 * Find out the device address, and check it for validity. 228 */ 229 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 230 if (tc_badaddr(zs_addr)) 231 return (0); 232 233 return (1); 234 } 235 236 /* 237 * Attach a found zs. 238 */ 239 void 240 zs_ioasic_attach(parent, self, aux) 241 struct device *parent; 242 struct device *self; 243 void *aux; 244 { 245 struct zsc_softc *zs = (void *) self; 246 struct zsc_attach_args zs_args; 247 struct zs_chanstate *cs; 248 struct ioasicdev_attach_args *d = aux; 249 struct zshan *zc; 250 int s, channel; 251 u_long zflg; 252 int locs[ZSCCF_NLOCS]; 253 254 printf("\n"); 255 256 /* 257 * Initialize software state for each channel. 258 */ 259 for (channel = 0; channel < 2; channel++) { 260 zs_args.channel = channel; 261 zs_args.hwflags = 0; 262 263 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 264 cs = &zs_ioasic_conschanstate_store; 265 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 266 } else { 267 cs = malloc(sizeof(struct zs_chanstate), 268 M_DEVBUF, M_NOWAIT|M_ZERO); 269 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 270 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 271 272 bcopy(zs_ioasic_init_reg, cs->cs_creg, 16); 273 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 274 275 cs->cs_defcflag = zs_def_cflag; 276 cs->cs_defspeed = 9600; /* XXX */ 277 (void) zs_set_modes(cs, cs->cs_defcflag); 278 } 279 280 zs->zsc_cs[channel] = cs; 281 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 282 cs->cs_channel = channel; 283 cs->cs_ops = &zsops_null; 284 cs->cs_brg_clk = PCLK / 16; 285 286 /* 287 * DCD and CTS interrupts are only meaningful on 288 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 289 * 290 * XXX This is sorta gross. 291 */ 292 if (d->iada_offset == 0x00100000 && channel == 1) { 293 cs->cs_creg[15] |= ZSWR15_DCD_IE; 294 cs->cs_preg[15] |= ZSWR15_DCD_IE; 295 zflg = ZIP_FLAGS_DCDCTS; 296 } else 297 zflg = 0; 298 if (channel == 1) 299 zflg |= ZIP_FLAGS_DTRRTS; 300 (u_long)cs->cs_private = zflg; 301 302 /* 303 * Clear the master interrupt enable. 304 * The INTENA is common to both channels, 305 * so just do it on the A channel. 306 */ 307 if (channel == 0) { 308 zs_write_reg(cs, 9, 0); 309 } 310 311 /* 312 * Set up the flow/modem control channel pointer to 313 * deal with the weird wiring on the TC Alpha and 314 * DECstation. 315 */ 316 if (channel == 1) 317 cs->cs_ctl_chan = zs->zsc_cs[0]; 318 else 319 cs->cs_ctl_chan = NULL; 320 321 locs[ZSCCF_CHANNEL] = channel; 322 323 /* 324 * Look for a child driver for this channel. 325 * The child attach will setup the hardware. 326 */ 327 if (config_found_sm_loc(self, "zsc", locs, (void *)&zs_args, 328 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 329 /* No sub-driver. Just reset it. */ 330 u_char reset = (channel == 0) ? 331 ZSWR9_A_RESET : ZSWR9_B_RESET; 332 s = splhigh(); 333 zs_write_reg(cs, 9, reset); 334 splx(s); 335 } 336 } 337 338 /* 339 * Set up the ioasic interrupt handler. 340 */ 341 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 342 zs_ioasic_hardintr, zs); 343 zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, 344 zs_ioasic_softintr, zs); 345 if (zs->zsc_sih == NULL) 346 panic("zs_ioasic_attach: unable to register softintr"); 347 348 /* 349 * Set the master interrupt enable and interrupt vector. The 350 * Sun does this only on one channel. The old Alpha SCC driver 351 * did it on both. We'll do it on both. 352 */ 353 s = splhigh(); 354 /* interrupt vector */ 355 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 356 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 357 358 /* master interrupt control (enable) */ 359 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 360 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 361 #if defined(__alpha__) || defined(alpha) 362 /* ioasic interrupt enable */ 363 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 364 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 365 tc_mb(); 366 #endif 367 splx(s); 368 } 369 370 int 371 zs_ioasic_print(aux, name) 372 void *aux; 373 const char *name; 374 { 375 struct zsc_attach_args *args = aux; 376 377 if (name != NULL) 378 aprint_normal("%s:", name); 379 380 if (args->channel != -1) 381 aprint_normal(" channel %d", args->channel); 382 383 return (UNCONF); 384 } 385 386 int 387 zs_ioasic_submatch(parent, cf, locs, aux) 388 struct device *parent; 389 struct cfdata *cf; 390 const int *locs; 391 void *aux; 392 { 393 struct zsc_softc *zs = (void *)parent; 394 struct zsc_attach_args *pa = aux; 395 const char *defname = ""; 396 397 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 398 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL]) 399 return (0); 400 401 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 402 if (pa->channel == 0) { 403 #if defined(pmax) 404 if (systype == DS_MAXINE) 405 return (0); 406 #endif 407 if (zs->zsc_addroffset == 0x100000) 408 defname = "vsms"; 409 else 410 defname = "lkkbd"; 411 } 412 else if (zs->zsc_addroffset == 0x100000) 413 defname = "zstty"; 414 #if defined(pmax) 415 else if (systype == DS_MAXINE) 416 return (0); 417 #endif 418 #if defined(__alpha__) || defined(alpha) 419 else if (cputype == ST_DEC_3000_300) 420 return (0); 421 #endif 422 else 423 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 424 425 if (strcmp(cf->cf_name, defname)) 426 return (0); 427 } 428 return (config_match(parent, cf, aux)); 429 } 430 431 /* 432 * Hardware interrupt handler. 433 */ 434 int 435 zs_ioasic_hardintr(arg) 436 void *arg; 437 { 438 struct zsc_softc *zsc = arg; 439 440 /* 441 * Call the upper-level MI hardware interrupt handler. 442 */ 443 zsc_intr_hard(zsc); 444 445 /* 446 * Check to see if we need to schedule any software-level 447 * processing interrupts. 448 */ 449 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 450 softintr_schedule(zsc->zsc_sih); 451 452 return (1); 453 } 454 455 /* 456 * Software-level interrupt (character processing, lower priority). 457 */ 458 void 459 zs_ioasic_softintr(arg) 460 void *arg; 461 { 462 struct zsc_softc *zsc = arg; 463 int s; 464 465 s = spltty(); 466 (void) zsc_intr_soft(zsc); 467 splx(s); 468 } 469 470 /* 471 * MD functions for setting the baud rate and control modes. 472 */ 473 int 474 zs_set_speed(cs, bps) 475 struct zs_chanstate *cs; 476 int bps; /* bits per second */ 477 { 478 int tconst, real_bps; 479 480 if (bps == 0) 481 return (0); 482 483 #ifdef DIAGNOSTIC 484 if (cs->cs_brg_clk == 0) 485 panic("zs_set_speed"); 486 #endif 487 488 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 489 if (tconst < 0) 490 return (EINVAL); 491 492 /* Convert back to make sure we can do it. */ 493 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 494 495 /* XXX - Allow some tolerance here? */ 496 if (real_bps != bps) 497 return (EINVAL); 498 499 cs->cs_preg[12] = tconst; 500 cs->cs_preg[13] = tconst >> 8; 501 502 /* Caller will stuff the pending registers. */ 503 return (0); 504 } 505 506 int 507 zs_set_modes(cs, cflag) 508 struct zs_chanstate *cs; 509 int cflag; /* bits per second */ 510 { 511 u_long privflags = (u_long)cs->cs_private; 512 int s; 513 514 /* 515 * Output hardware flow control on the chip is horrendous: 516 * if carrier detect drops, the receiver is disabled, and if 517 * CTS drops, the transmitter is stoped IN MID CHARACTER! 518 * Therefore, NEVER set the HFC bit, and instead use the 519 * status interrupt to detect CTS changes. 520 */ 521 s = splzs(); 522 if ((cflag & (CLOCAL | MDMBUF)) != 0) 523 cs->cs_rr0_dcd = 0; 524 else 525 cs->cs_rr0_dcd = ZSRR0_DCD; 526 if ((cflag & CRTSCTS) != 0) { 527 cs->cs_wr5_dtr = ZSWR5_DTR; 528 cs->cs_wr5_rts = ZSWR5_RTS; 529 cs->cs_rr0_cts = ZSRR0_CTS; 530 } else if ((cflag & CDTRCTS) != 0) { 531 cs->cs_wr5_dtr = 0; 532 cs->cs_wr5_rts = ZSWR5_DTR; 533 cs->cs_rr0_cts = ZSRR0_CTS; 534 } else if ((cflag & MDMBUF) != 0) { 535 cs->cs_wr5_dtr = 0; 536 cs->cs_wr5_rts = ZSWR5_DTR; 537 cs->cs_rr0_cts = ZSRR0_DCD; 538 } else { 539 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 540 cs->cs_wr5_rts = 0; 541 cs->cs_rr0_cts = 0; 542 } 543 544 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 545 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 546 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 547 } 548 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) { 549 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR); 550 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR); 551 } 552 splx(s); 553 554 /* Caller will stuff the pending registers. */ 555 return (0); 556 } 557 558 /* 559 * Functions to read and write individual registers in a channel. 560 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 561 * and the Alpha TC hardware does NOT take care of this for you. 562 * The delay is now handled inside the chip access functions. 563 * These could be inlines, but with the delay, speed is moot. 564 */ 565 #if defined(pmax) 566 #undef DELAY 567 #define DELAY(x) 568 #endif 569 570 u_int 571 zs_read_reg(cs, reg) 572 struct zs_chanstate *cs; 573 u_int reg; 574 { 575 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 576 unsigned val; 577 578 zc->zc_csr = reg << 8; 579 tc_wmb(); 580 DELAY(5); 581 val = (zc->zc_csr >> 8) & 0xff; 582 /* tc_mb(); */ 583 DELAY(5); 584 return (val); 585 } 586 587 void 588 zs_write_reg(cs, reg, val) 589 struct zs_chanstate *cs; 590 u_int reg, val; 591 { 592 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 593 594 zc->zc_csr = reg << 8; 595 tc_wmb(); 596 DELAY(5); 597 zc->zc_csr = val << 8; 598 tc_wmb(); 599 DELAY(5); 600 } 601 602 u_int 603 zs_read_csr(cs) 604 struct zs_chanstate *cs; 605 { 606 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 607 unsigned val; 608 609 val = (zc->zc_csr >> 8) & 0xff; 610 /* tc_mb(); */ 611 DELAY(5); 612 return (val); 613 } 614 615 void 616 zs_write_csr(cs, val) 617 struct zs_chanstate *cs; 618 u_int val; 619 { 620 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 621 622 zc->zc_csr = val << 8; 623 tc_wmb(); 624 DELAY(5); 625 } 626 627 u_int 628 zs_read_data(cs) 629 struct zs_chanstate *cs; 630 { 631 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 632 unsigned val; 633 634 val = (zc->zc_data) >> 8 & 0xff; 635 /* tc_mb(); */ 636 DELAY(5); 637 return (val); 638 } 639 640 void 641 zs_write_data(cs, val) 642 struct zs_chanstate *cs; 643 u_int val; 644 { 645 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 646 647 zc->zc_data = val << 8; 648 tc_wmb(); 649 DELAY(5); 650 } 651 652 /**************************************************************** 653 * Console support functions 654 ****************************************************************/ 655 656 /* 657 * Handle user request to enter kernel debugger. 658 */ 659 void 660 zs_abort(cs) 661 struct zs_chanstate *cs; 662 { 663 int rr0; 664 665 /* Wait for end of break. */ 666 /* XXX - Limit the wait? */ 667 do { 668 rr0 = zs_read_csr(cs); 669 } while (rr0 & ZSRR0_BREAK); 670 671 #if defined(KGDB) 672 zskgdb(cs); 673 #elif defined(DDB) 674 Debugger(); 675 #else 676 printf("zs_abort: ignoring break on console\n"); 677 #endif 678 } 679 680 /* 681 * Polled input char. 682 */ 683 int 684 zs_getc(cs) 685 struct zs_chanstate *cs; 686 { 687 int s, c, rr0; 688 689 s = splhigh(); 690 /* Wait for a character to arrive. */ 691 do { 692 rr0 = zs_read_csr(cs); 693 } while ((rr0 & ZSRR0_RX_READY) == 0); 694 695 c = zs_read_data(cs); 696 splx(s); 697 698 /* 699 * This is used by the kd driver to read scan codes, 700 * so don't translate '\r' ==> '\n' here... 701 */ 702 return (c); 703 } 704 705 /* 706 * Polled output char. 707 */ 708 void 709 zs_putc(cs, c) 710 struct zs_chanstate *cs; 711 int c; 712 { 713 register int s, rr0; 714 715 s = splhigh(); 716 /* Wait for transmitter to become ready. */ 717 do { 718 rr0 = zs_read_csr(cs); 719 } while ((rr0 & ZSRR0_TX_READY) == 0); 720 721 zs_write_data(cs, c); 722 723 /* Wait for the character to be transmitted. */ 724 do { 725 rr0 = zs_read_csr(cs); 726 } while ((rr0 & ZSRR0_TX_READY) == 0); 727 splx(s); 728 } 729 730 /*****************************************************************/ 731 732 /* 733 * zs_ioasic_cninit -- 734 * Initialize the serial channel for either a keyboard or 735 * a serial console. 736 */ 737 void 738 zs_ioasic_cninit(ioasic_addr, zs_offset, channel) 739 tc_addr_t ioasic_addr; 740 tc_offset_t zs_offset; 741 int channel; 742 { 743 struct zs_chanstate *cs; 744 tc_addr_t zs_addr; 745 struct zshan *zc; 746 u_long zflg; 747 748 /* 749 * Initialize the console finder helpers. 750 */ 751 zs_ioasic_console_offset = zs_offset; 752 zs_ioasic_console_channel = channel; 753 zs_ioasic_console = 1; 754 755 /* 756 * Pointer to channel state. 757 */ 758 cs = &zs_ioasic_conschanstate_store; 759 760 /* 761 * Compute the physical address of the chip, "map" it via 762 * K0SEG, and then get the address of the actual channel. 763 */ 764 #if defined(__alpha__) || defined(alpha) 765 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 766 #endif 767 #if defined(pmax) 768 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 769 #endif 770 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 771 772 /* Setup temporary chanstate. */ 773 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 774 775 cs->cs_channel = channel; 776 cs->cs_ops = &zsops_null; 777 cs->cs_brg_clk = PCLK / 16; 778 779 /* Initialize the pending registers. */ 780 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 781 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */ 782 783 /* 784 * DCD and CTS interrupts are only meaningful on 785 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 786 * 787 * XXX This is sorta gross. 788 */ 789 if (zs_offset == 0x00100000 && channel == 1) 790 zflg = ZIP_FLAGS_DCDCTS; 791 else 792 zflg = 0; 793 if (channel == 1) 794 zflg |= ZIP_FLAGS_DTRRTS; 795 (u_long)cs->cs_private = zflg; 796 797 /* Clear the master interrupt enable. */ 798 zs_write_reg(cs, 9, 0); 799 800 /* Reset the whole SCC chip. */ 801 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 802 803 /* Copy "pending" to "current" and H/W. */ 804 zs_loadchannelregs(cs); 805 } 806 807 /* 808 * zs_ioasic_cnattach -- 809 * Initialize and attach a serial console. 810 */ 811 void 812 zs_ioasic_cnattach(ioasic_addr, zs_offset, channel) 813 tc_addr_t ioasic_addr; 814 tc_offset_t zs_offset; 815 int channel; 816 { 817 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 818 extern const struct cdevsw zstty_cdevsw; 819 820 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 821 cs->cs_defspeed = 9600; 822 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 823 824 /* Point the console at the SCC. */ 825 cn_tab = &zs_ioasic_cons; 826 cn_tab->cn_pri = CN_REMOTE; 827 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 828 (zs_offset == 0x100000) ? 0 : 1); 829 } 830 831 /* 832 * zs_ioasic_lk201_cnattach -- 833 * Initialize and attach a keyboard. 834 */ 835 int 836 zs_ioasic_lk201_cnattach(ioasic_addr, zs_offset, channel) 837 tc_addr_t ioasic_addr; 838 tc_offset_t zs_offset; 839 int channel; 840 { 841 #if (NZSKBD > 0) 842 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 843 844 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 845 cs->cs_defspeed = 4800; 846 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 847 return (zskbd_cnattach(cs)); 848 #else 849 return (ENXIO); 850 #endif 851 } 852 853 int 854 zs_ioasic_isconsole(offset, channel) 855 tc_offset_t offset; 856 int channel; 857 { 858 859 if (zs_ioasic_console && 860 offset == zs_ioasic_console_offset && 861 channel == zs_ioasic_console_channel) 862 return (1); 863 864 return (0); 865 } 866 867 /* 868 * Polled console input putchar. 869 */ 870 int 871 zs_ioasic_cngetc(dev) 872 dev_t dev; 873 { 874 875 return (zs_getc(&zs_ioasic_conschanstate_store)); 876 } 877 878 /* 879 * Polled console output putchar. 880 */ 881 void 882 zs_ioasic_cnputc(dev, c) 883 dev_t dev; 884 int c; 885 { 886 887 zs_putc(&zs_ioasic_conschanstate_store, c); 888 } 889 890 /* 891 * Set polling/no polling on console. 892 */ 893 void 894 zs_ioasic_cnpollc(dev, onoff) 895 dev_t dev; 896 int onoff; 897 { 898 899 /* XXX ??? */ 900 } 901