1 /* $NetBSD: zs_ioasic.c,v 1.36 2008/03/29 19:15:36 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 42 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 43 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 44 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 45 * 46 * Runs two serial lines per chip using slave drivers. 47 * Plain tty/async lines use the zstty slave. 48 */ 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.36 2008/03/29 19:15:36 tsutsui Exp $"); 52 53 #include "opt_ddb.h" 54 #include "opt_kgdb.h" 55 #include "zskbd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/conf.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/file.h> 63 #include <sys/ioctl.h> 64 #include <sys/kernel.h> 65 #include <sys/proc.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/syslog.h> 69 #include <sys/intr.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/z8530var.h> 73 74 #include <dev/cons.h> 75 #include <dev/ic/z8530reg.h> 76 77 #include <dev/tc/tcvar.h> 78 #include <dev/tc/ioasicreg.h> 79 #include <dev/tc/ioasicvar.h> 80 81 #include <dev/tc/zs_ioasicvar.h> 82 83 #if defined(__alpha__) || defined(alpha) 84 #include <machine/rpb.h> 85 #endif 86 #if defined(pmax) 87 #include <pmax/pmax/pmaxtype.h> 88 #endif 89 90 /* 91 * Helpers for console support. 92 */ 93 static void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int); 94 static int zs_ioasic_cngetc(dev_t); 95 static void zs_ioasic_cnputc(dev_t, int); 96 static void zs_ioasic_cnpollc(dev_t, int); 97 98 struct consdev zs_ioasic_cons = { 99 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 100 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL, 101 }; 102 103 static tc_offset_t zs_ioasic_console_offset; 104 static int zs_ioasic_console_channel; 105 static int zs_ioasic_console; 106 static struct zs_chanstate zs_ioasic_conschanstate_store; 107 108 static int zs_ioasic_isconsole(tc_offset_t, int); 109 static void zs_putc(struct zs_chanstate *, int); 110 111 /* 112 * Some warts needed by z8530tty.c 113 */ 114 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 115 116 /* 117 * ZS chips are feeded a 7.372 MHz clock. 118 */ 119 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 120 121 /* The layout of this is hardware-dependent (padding, order). */ 122 struct zshan { 123 #if defined(__alpha__) || defined(alpha) 124 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 125 u_int zc_pad0; 126 volatile u_int zc_data; /* data */ 127 u_int sc_pad1; 128 #endif 129 #if defined(pmax) 130 volatile uint16_t zc_csr; /* ctrl,status, and indirect access */ 131 unsigned : 16; 132 volatile uint16_t zc_data; /* data */ 133 unsigned : 16; 134 #endif 135 }; 136 137 struct zsdevice { 138 /* Yes, they are backwards. */ 139 struct zshan zs_chan_b; 140 struct zshan zs_chan_a; 141 }; 142 143 static const u_char zs_ioasic_init_reg[16] = { 144 0, /* 0: CMD (reset, etc.) */ 145 0, /* 1: No interrupts yet. */ 146 0xf0, /* 2: IVECT */ 147 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 148 ZSWR4_CLK_X16 | ZSWR4_ONESB, 149 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 150 0, /* 6: TXSYNC/SYNCLO */ 151 0, /* 7: RXSYNC/SYNCHI */ 152 0, /* 8: alias for data port */ 153 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 154 0, /*10: Misc. TX/RX control bits */ 155 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 156 22, /*12: BAUDLO (default=9600) */ 157 0, /*13: BAUDHI (default=9600) */ 158 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 159 ZSWR15_BREAK_IE, 160 }; 161 162 static struct zshan * 163 zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel) 164 { 165 struct zsdevice *addr; 166 struct zshan *zc; 167 168 #if defined(__alpha__) || defined(alpha) 169 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 170 #endif 171 #if defined(pmax) 172 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 173 #endif 174 175 if (channel == 0) 176 zc = &addr->zs_chan_a; 177 else 178 zc = &addr->zs_chan_b; 179 180 return (zc); 181 } 182 183 184 /**************************************************************** 185 * Autoconfig 186 ****************************************************************/ 187 188 /* Definition of the driver for autoconfig. */ 189 static int zs_ioasic_match(device_t, cfdata_t, void *); 190 static void zs_ioasic_attach(device_t, device_t, void *); 191 static int zs_ioasic_print(void *, const char *name); 192 static int zs_ioasic_submatch(device_t, struct cfdata *, 193 const int *, void *); 194 195 CFATTACH_DECL_NEW(zsc_ioasic, sizeof(struct zsc_softc), 196 zs_ioasic_match, zs_ioasic_attach, NULL, NULL); 197 198 /* Interrupt handlers. */ 199 static int zs_ioasic_hardintr(void *); 200 static void zs_ioasic_softintr(void *); 201 202 /* 203 * Is the zs chip present? 204 */ 205 static int 206 zs_ioasic_match(device_t parent, cfdata_t cf, void *aux) 207 { 208 struct ioasicdev_attach_args *d = aux; 209 tc_addr_t zs_addr; 210 211 /* 212 * Make sure that we're looking for the right kind of device. 213 */ 214 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 215 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 216 return (0); 217 218 /* 219 * Find out the device address, and check it for validity. 220 */ 221 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 222 if (tc_badaddr(zs_addr)) 223 return (0); 224 225 return (1); 226 } 227 228 /* 229 * Attach a found zs. 230 */ 231 static void 232 zs_ioasic_attach(device_t parent, device_t self, void *aux) 233 { 234 struct zsc_softc *zs = device_private(self); 235 struct zsc_attach_args zs_args; 236 struct zs_chanstate *cs; 237 struct ioasicdev_attach_args *d = aux; 238 struct zshan *zc; 239 int s, channel; 240 u_long zflg; 241 int locs[ZSCCF_NLOCS]; 242 243 zs->zsc_dev = self; 244 aprint_normal("\n"); 245 246 /* 247 * Initialize software state for each channel. 248 */ 249 for (channel = 0; channel < 2; channel++) { 250 zs_args.channel = channel; 251 zs_args.hwflags = 0; 252 253 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 254 cs = &zs_ioasic_conschanstate_store; 255 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 256 } else { 257 cs = malloc(sizeof(struct zs_chanstate), 258 M_DEVBUF, M_NOWAIT|M_ZERO); 259 zs_lock_init(cs); 260 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 261 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 262 263 memcpy(cs->cs_creg, zs_ioasic_init_reg, 16); 264 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16); 265 266 cs->cs_defcflag = zs_def_cflag; 267 cs->cs_defspeed = 9600; /* XXX */ 268 (void)zs_set_modes(cs, cs->cs_defcflag); 269 } 270 271 zs->zsc_cs[channel] = cs; 272 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 273 cs->cs_channel = channel; 274 cs->cs_ops = &zsops_null; 275 cs->cs_brg_clk = PCLK / 16; 276 277 /* 278 * DCD and CTS interrupts are only meaningful on 279 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 280 * 281 * XXX This is sorta gross. 282 */ 283 if (d->iada_offset == 0x00100000 && channel == 1) { 284 cs->cs_creg[15] |= ZSWR15_DCD_IE; 285 cs->cs_preg[15] |= ZSWR15_DCD_IE; 286 zflg = ZIP_FLAGS_DCDCTS; 287 } else 288 zflg = 0; 289 if (channel == 1) 290 zflg |= ZIP_FLAGS_DTRRTS; 291 cs->cs_private = (void *)zflg; 292 293 /* 294 * Clear the master interrupt enable. 295 * The INTENA is common to both channels, 296 * so just do it on the A channel. 297 */ 298 if (channel == 0) { 299 zs_write_reg(cs, 9, 0); 300 } 301 302 /* 303 * Set up the flow/modem control channel pointer to 304 * deal with the weird wiring on the TC Alpha and 305 * DECstation. 306 */ 307 if (channel == 1) 308 cs->cs_ctl_chan = zs->zsc_cs[0]; 309 else 310 cs->cs_ctl_chan = NULL; 311 312 locs[ZSCCF_CHANNEL] = channel; 313 314 /* 315 * Look for a child driver for this channel. 316 * The child attach will setup the hardware. 317 */ 318 if (config_found_sm_loc(self, "zsc", locs, (void *)&zs_args, 319 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 320 /* No sub-driver. Just reset it. */ 321 uint8_t reset = (channel == 0) ? 322 ZSWR9_A_RESET : ZSWR9_B_RESET; 323 s = splhigh(); 324 zs_write_reg(cs, 9, reset); 325 splx(s); 326 } 327 } 328 329 /* 330 * Set up the ioasic interrupt handler. 331 */ 332 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 333 zs_ioasic_hardintr, zs); 334 zs->zsc_sih = softint_establish(SOFTINT_SERIAL, 335 zs_ioasic_softintr, zs); 336 if (zs->zsc_sih == NULL) 337 panic("%s: unable to register softintr", __func__); 338 339 /* 340 * Set the master interrupt enable and interrupt vector. The 341 * Sun does this only on one channel. The old Alpha SCC driver 342 * did it on both. We'll do it on both. 343 */ 344 s = splhigh(); 345 /* interrupt vector */ 346 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 347 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 348 349 /* master interrupt control (enable) */ 350 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 351 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 352 #if defined(__alpha__) || defined(alpha) 353 /* ioasic interrupt enable */ 354 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 355 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 356 tc_mb(); 357 #endif 358 splx(s); 359 } 360 361 static int 362 zs_ioasic_print(void *aux, const char *name) 363 { 364 struct zsc_attach_args *args = aux; 365 366 if (name != NULL) 367 aprint_normal("%s:", name); 368 369 if (args->channel != -1) 370 aprint_normal(" channel %d", args->channel); 371 372 return (UNCONF); 373 } 374 375 static int 376 zs_ioasic_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux) 377 { 378 struct zsc_softc *zs = device_private(parent); 379 struct zsc_attach_args *pa = aux; 380 const char *defname = ""; 381 382 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 383 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL]) 384 return (0); 385 386 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 387 if (pa->channel == 0) { 388 #if defined(pmax) 389 if (systype == DS_MAXINE) 390 return (0); 391 #endif 392 if (zs->zsc_addroffset == 0x100000) 393 defname = "vsms"; 394 else 395 defname = "lkkbd"; 396 } 397 else if (zs->zsc_addroffset == 0x100000) 398 defname = "zstty"; 399 #if defined(pmax) 400 else if (systype == DS_MAXINE) 401 return (0); 402 #endif 403 #if defined(__alpha__) || defined(alpha) 404 else if (cputype == ST_DEC_3000_300) 405 return (0); 406 #endif 407 else 408 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 409 410 if (strcmp(cf->cf_name, defname)) 411 return (0); 412 } 413 return (config_match(parent, cf, aux)); 414 } 415 416 /* 417 * Hardware interrupt handler. 418 */ 419 static int 420 zs_ioasic_hardintr(void *arg) 421 { 422 struct zsc_softc *zsc = arg; 423 424 /* 425 * Call the upper-level MI hardware interrupt handler. 426 */ 427 zsc_intr_hard(zsc); 428 429 /* 430 * Check to see if we need to schedule any software-level 431 * processing interrupts. 432 */ 433 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 434 softint_schedule(zsc->zsc_sih); 435 436 return (1); 437 } 438 439 /* 440 * Software-level interrupt (character processing, lower priority). 441 */ 442 static void 443 zs_ioasic_softintr(void *arg) 444 { 445 struct zsc_softc *zsc = arg; 446 int s; 447 448 s = spltty(); 449 (void)zsc_intr_soft(zsc); 450 splx(s); 451 } 452 453 /* 454 * MD functions for setting the baud rate and control modes. 455 */ 456 int 457 zs_set_speed(struct zs_chanstate *cs, int bps /*bits per second*/) 458 { 459 int tconst, real_bps; 460 461 if (bps == 0) 462 return (0); 463 464 #ifdef DIAGNOSTIC 465 if (cs->cs_brg_clk == 0) 466 panic("zs_set_speed"); 467 #endif 468 469 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 470 if (tconst < 0) 471 return (EINVAL); 472 473 /* Convert back to make sure we can do it. */ 474 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 475 476 /* XXX - Allow some tolerance here? */ 477 if (real_bps != bps) 478 return (EINVAL); 479 480 cs->cs_preg[12] = tconst; 481 cs->cs_preg[13] = tconst >> 8; 482 483 /* Caller will stuff the pending registers. */ 484 return (0); 485 } 486 487 int 488 zs_set_modes(struct zs_chanstate *cs, int cflag) 489 { 490 u_long privflags = (u_long)cs->cs_private; 491 int s; 492 493 /* 494 * Output hardware flow control on the chip is horrendous: 495 * if carrier detect drops, the receiver is disabled, and if 496 * CTS drops, the transmitter is stoped IN MID CHARACTER! 497 * Therefore, NEVER set the HFC bit, and instead use the 498 * status interrupt to detect CTS changes. 499 */ 500 s = splzs(); 501 if ((cflag & (CLOCAL | MDMBUF)) != 0) 502 cs->cs_rr0_dcd = 0; 503 else 504 cs->cs_rr0_dcd = ZSRR0_DCD; 505 if ((cflag & CRTSCTS) != 0) { 506 cs->cs_wr5_dtr = ZSWR5_DTR; 507 cs->cs_wr5_rts = ZSWR5_RTS; 508 cs->cs_rr0_cts = ZSRR0_CTS; 509 } else if ((cflag & CDTRCTS) != 0) { 510 cs->cs_wr5_dtr = 0; 511 cs->cs_wr5_rts = ZSWR5_DTR; 512 cs->cs_rr0_cts = ZSRR0_CTS; 513 } else if ((cflag & MDMBUF) != 0) { 514 cs->cs_wr5_dtr = 0; 515 cs->cs_wr5_rts = ZSWR5_DTR; 516 cs->cs_rr0_cts = ZSRR0_DCD; 517 } else { 518 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 519 cs->cs_wr5_rts = 0; 520 cs->cs_rr0_cts = 0; 521 } 522 523 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 524 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 525 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 526 } 527 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) { 528 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR); 529 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR); 530 } 531 splx(s); 532 533 /* Caller will stuff the pending registers. */ 534 return (0); 535 } 536 537 /* 538 * Functions to read and write individual registers in a channel. 539 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 540 * and the Alpha TC hardware does NOT take care of this for you. 541 * The delay is now handled inside the chip access functions. 542 * These could be inlines, but with the delay, speed is moot. 543 */ 544 #if defined(pmax) 545 #undef DELAY 546 #define DELAY(x) 547 #endif 548 549 u_int 550 zs_read_reg(struct zs_chanstate *cs, u_int reg) 551 { 552 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 553 unsigned val; 554 555 zc->zc_csr = reg << 8; 556 tc_wmb(); 557 DELAY(5); 558 val = (zc->zc_csr >> 8) & 0xff; 559 /* tc_mb(); */ 560 DELAY(5); 561 return (val); 562 } 563 564 void 565 zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val) 566 { 567 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 568 569 zc->zc_csr = reg << 8; 570 tc_wmb(); 571 DELAY(5); 572 zc->zc_csr = val << 8; 573 tc_wmb(); 574 DELAY(5); 575 } 576 577 u_int 578 zs_read_csr(struct zs_chanstate *cs) 579 { 580 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 581 unsigned val; 582 583 val = (zc->zc_csr >> 8) & 0xff; 584 /* tc_mb(); */ 585 DELAY(5); 586 return (val); 587 } 588 589 void 590 zs_write_csr(struct zs_chanstate *cs, u_int val) 591 { 592 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 593 594 zc->zc_csr = val << 8; 595 tc_wmb(); 596 DELAY(5); 597 } 598 599 u_int 600 zs_read_data(struct zs_chanstate *cs) 601 { 602 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 603 unsigned val; 604 605 val = (zc->zc_data) >> 8 & 0xff; 606 /* tc_mb(); */ 607 DELAY(5); 608 return (val); 609 } 610 611 void 612 zs_write_data(struct zs_chanstate *cs, u_int val) 613 { 614 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 615 616 zc->zc_data = val << 8; 617 tc_wmb(); 618 DELAY(5); 619 } 620 621 /**************************************************************** 622 * Console support functions 623 ****************************************************************/ 624 625 /* 626 * Handle user request to enter kernel debugger. 627 */ 628 void 629 zs_abort(struct zs_chanstate *cs) 630 { 631 u_int rr0; 632 633 /* Wait for end of break. */ 634 /* XXX - Limit the wait? */ 635 do { 636 rr0 = zs_read_csr(cs); 637 } while (rr0 & ZSRR0_BREAK); 638 639 #if defined(KGDB) 640 zskgdb(cs); 641 #elif defined(DDB) 642 Debugger(); 643 #else 644 printf("zs_abort: ignoring break on console\n"); 645 #endif 646 } 647 648 /* 649 * Polled input char. 650 */ 651 int 652 zs_getc(struct zs_chanstate *cs) 653 { 654 int s, c; 655 u_int rr0; 656 657 s = splhigh(); 658 /* Wait for a character to arrive. */ 659 do { 660 rr0 = zs_read_csr(cs); 661 } while ((rr0 & ZSRR0_RX_READY) == 0); 662 663 c = zs_read_data(cs); 664 splx(s); 665 666 /* 667 * This is used by the kd driver to read scan codes, 668 * so don't translate '\r' ==> '\n' here... 669 */ 670 return (c); 671 } 672 673 /* 674 * Polled output char. 675 */ 676 static void 677 zs_putc(struct zs_chanstate *cs, int c) 678 { 679 int s; 680 u_int rr0; 681 682 s = splhigh(); 683 /* Wait for transmitter to become ready. */ 684 do { 685 rr0 = zs_read_csr(cs); 686 } while ((rr0 & ZSRR0_TX_READY) == 0); 687 688 zs_write_data(cs, c); 689 690 /* Wait for the character to be transmitted. */ 691 do { 692 rr0 = zs_read_csr(cs); 693 } while ((rr0 & ZSRR0_TX_READY) == 0); 694 splx(s); 695 } 696 697 /*****************************************************************/ 698 699 /* 700 * zs_ioasic_cninit -- 701 * Initialize the serial channel for either a keyboard or 702 * a serial console. 703 */ 704 static void 705 zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 706 { 707 struct zs_chanstate *cs; 708 tc_addr_t zs_addr; 709 struct zshan *zc; 710 u_long zflg; 711 712 /* 713 * Initialize the console finder helpers. 714 */ 715 zs_ioasic_console_offset = zs_offset; 716 zs_ioasic_console_channel = channel; 717 zs_ioasic_console = 1; 718 719 /* 720 * Pointer to channel state. 721 */ 722 cs = &zs_ioasic_conschanstate_store; 723 724 /* 725 * Compute the physical address of the chip, "map" it via 726 * K0SEG, and then get the address of the actual channel. 727 */ 728 #if defined(__alpha__) || defined(alpha) 729 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 730 #endif 731 #if defined(pmax) 732 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 733 #endif 734 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 735 736 /* Setup temporary chanstate. */ 737 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 738 739 cs->cs_channel = channel; 740 cs->cs_ops = &zsops_null; 741 cs->cs_brg_clk = PCLK / 16; 742 743 /* Initialize the pending registers. */ 744 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 745 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */ 746 747 /* 748 * DCD and CTS interrupts are only meaningful on 749 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 750 * 751 * XXX This is sorta gross. 752 */ 753 if (zs_offset == 0x00100000 && channel == 1) 754 zflg = ZIP_FLAGS_DCDCTS; 755 else 756 zflg = 0; 757 if (channel == 1) 758 zflg |= ZIP_FLAGS_DTRRTS; 759 cs->cs_private = (void *)zflg; 760 761 /* Clear the master interrupt enable. */ 762 zs_write_reg(cs, 9, 0); 763 764 /* Reset the whole SCC chip. */ 765 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 766 767 /* Copy "pending" to "current" and H/W. */ 768 zs_loadchannelregs(cs); 769 } 770 771 /* 772 * zs_ioasic_cnattach -- 773 * Initialize and attach a serial console. 774 */ 775 void 776 zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 777 { 778 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 779 extern const struct cdevsw zstty_cdevsw; 780 781 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 782 zs_lock_init(cs); 783 cs->cs_defspeed = 9600; 784 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 785 786 /* Point the console at the SCC. */ 787 cn_tab = &zs_ioasic_cons; 788 cn_tab->cn_pri = CN_REMOTE; 789 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 790 (zs_offset == 0x100000) ? 0 : 1); 791 } 792 793 /* 794 * zs_ioasic_lk201_cnattach -- 795 * Initialize and attach a keyboard. 796 */ 797 int 798 zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, 799 int channel) 800 { 801 #if (NZSKBD > 0) 802 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 803 804 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 805 zs_lock_init(cs); 806 cs->cs_defspeed = 4800; 807 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 808 return (zskbd_cnattach(cs)); 809 #else 810 return (ENXIO); 811 #endif 812 } 813 814 static int 815 zs_ioasic_isconsole(tc_offset_t offset, int channel) 816 { 817 818 if (zs_ioasic_console && 819 offset == zs_ioasic_console_offset && 820 channel == zs_ioasic_console_channel) 821 return (1); 822 823 return (0); 824 } 825 826 /* 827 * Polled console input putchar. 828 */ 829 static int 830 zs_ioasic_cngetc(dev_t dev) 831 { 832 833 return (zs_getc(&zs_ioasic_conschanstate_store)); 834 } 835 836 /* 837 * Polled console output putchar. 838 */ 839 static void 840 zs_ioasic_cnputc(dev_t dev, int c) 841 { 842 843 zs_putc(&zs_ioasic_conschanstate_store, c); 844 } 845 846 /* 847 * Set polling/no polling on console. 848 */ 849 static void 850 zs_ioasic_cnpollc(dev_t dev, int onoff) 851 { 852 853 /* XXX ??? */ 854 } 855