1 /* $NetBSD: zs_ioasic.c,v 1.8 2001/09/14 11:58:39 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 41 42 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.8 2001/09/14 11:58:39 ad Exp $"); 43 44 /* 45 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 46 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 47 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 48 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 49 * 50 * Runs two serial lines per chip using slave drivers. 51 * Plain tty/async lines use the zstty slave. 52 */ 53 54 #include "opt_ddb.h" 55 #include "opt_kgdb.h" 56 #include "zskbd.h" 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/conf.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 #include <sys/file.h> 64 #include <sys/ioctl.h> 65 #include <sys/kernel.h> 66 #include <sys/proc.h> 67 #include <sys/tty.h> 68 #include <sys/time.h> 69 #include <sys/syslog.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/intr.h> 73 #include <machine/z8530var.h> 74 75 #include <dev/cons.h> 76 #include <dev/ic/z8530reg.h> 77 78 #include <dev/tc/tcvar.h> 79 #include <dev/tc/ioasicreg.h> 80 #include <dev/tc/ioasicvar.h> 81 82 #include <dev/tc/zs_ioasicvar.h> 83 84 #if defined(__alpha__) || defined(alpha) 85 #include <machine/rpb.h> 86 #endif 87 #if defined(pmax) 88 #include <pmax/pmax/pmaxtype.h> 89 #endif 90 91 /* 92 * Helpers for console support. 93 */ 94 void zs_ioasic_cninit __P((tc_addr_t, tc_offset_t, int)); 95 int zs_ioasic_cngetc __P((dev_t)); 96 void zs_ioasic_cnputc __P((dev_t, int)); 97 void zs_ioasic_cnpollc __P((dev_t, int)); 98 99 struct consdev zs_ioasic_cons = { 100 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 101 zs_ioasic_cnpollc, NULL, NODEV, CN_NORMAL, 102 }; 103 104 tc_offset_t zs_ioasic_console_offset; 105 int zs_ioasic_console_channel; 106 int zs_ioasic_console; 107 struct zs_chanstate zs_ioasic_conschanstate_store; 108 109 int zs_ioasic_isconsole __P((tc_offset_t, int)); 110 int zs_getc __P((struct zs_chanstate *)); 111 void zs_putc __P((struct zs_chanstate *, int)); 112 113 /* 114 * Some warts needed by z8530tty.c 115 */ 116 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 117 #if defined(__alpha__) || defined(alpha) 118 int zs_major = 15; 119 #endif 120 #if defined(pmax) 121 int zs_major = 17; 122 #endif 123 124 /* 125 * ZS chips are feeded a 7.372 MHz clock. 126 */ 127 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 128 129 /* The layout of this is hardware-dependent (padding, order). */ 130 struct zshan { 131 #if defined(__alpha__) || defined(alpha) 132 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 133 u_int zc_pad0; 134 volatile u_int zc_data; /* data */ 135 u_int sc_pad1; 136 #endif 137 #if defined(pmax) 138 volatile u_int16_t zc_csr; /* ctrl,status, and indirect access */ 139 unsigned : 16; 140 volatile u_int16_t zc_data; /* data */ 141 unsigned : 16; 142 #endif 143 }; 144 145 struct zsdevice { 146 /* Yes, they are backwards. */ 147 struct zshan zs_chan_b; 148 struct zshan zs_chan_a; 149 }; 150 151 static u_char zs_ioasic_init_reg[16] = { 152 0, /* 0: CMD (reset, etc.) */ 153 0, /* 1: No interrupts yet. */ 154 0xf0, /* 2: IVECT */ 155 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 156 ZSWR4_CLK_X16 | ZSWR4_ONESB, 157 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 158 0, /* 6: TXSYNC/SYNCLO */ 159 0, /* 7: RXSYNC/SYNCHI */ 160 0, /* 8: alias for data port */ 161 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 162 0, /*10: Misc. TX/RX control bits */ 163 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 164 22, /*12: BAUDLO (default=9600) */ 165 0, /*13: BAUDHI (default=9600) */ 166 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 167 ZSWR15_BREAK_IE, 168 }; 169 170 struct zshan *zs_ioasic_get_chan_addr __P((tc_addr_t, int)); 171 172 struct zshan * 173 zs_ioasic_get_chan_addr(zsaddr, channel) 174 tc_addr_t zsaddr; 175 int channel; 176 { 177 struct zsdevice *addr; 178 struct zshan *zc; 179 180 #if defined(__alpha__) || defined(alpha) 181 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 182 #endif 183 #if defined(pmax) 184 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 185 #endif 186 187 if (channel == 0) 188 zc = &addr->zs_chan_a; 189 else 190 zc = &addr->zs_chan_b; 191 192 return (zc); 193 } 194 195 196 /**************************************************************** 197 * Autoconfig 198 ****************************************************************/ 199 200 /* Definition of the driver for autoconfig. */ 201 int zs_ioasic_match __P((struct device *, struct cfdata *, void *)); 202 void zs_ioasic_attach __P((struct device *, struct device *, void *)); 203 int zs_ioasic_print __P((void *, const char *name)); 204 int zs_ioasic_submatch __P((struct device *, struct cfdata *, void *)); 205 206 struct cfattach zsc_ioasic_ca = { 207 sizeof(struct zsc_softc), zs_ioasic_match, zs_ioasic_attach 208 }; 209 210 /* Interrupt handlers. */ 211 int zs_ioasic_hardintr __P((void *)); 212 void zs_ioasic_softintr __P((void *)); 213 214 extern struct cfdriver ioasic_cd; 215 216 /* 217 * Is the zs chip present? 218 */ 219 int 220 zs_ioasic_match(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 struct ioasicdev_attach_args *d = aux; 226 tc_addr_t zs_addr; 227 228 if (parent->dv_cfdata->cf_driver != &ioasic_cd) 229 return (0); 230 231 /* 232 * Make sure that we're looking for the right kind of device. 233 */ 234 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 235 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 236 return (0); 237 238 /* 239 * Check user-specified offset against the ioasic offset. 240 * Allow it to be wildcarded. 241 */ 242 if (cf->cf_loc[IOASICCF_OFFSET] != IOASICCF_OFFSET_DEFAULT && 243 cf->cf_loc[IOASICCF_OFFSET] != d->iada_offset) 244 return (0); 245 246 /* 247 * Find out the device address, and check it for validity. 248 */ 249 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 250 if (tc_badaddr(zs_addr)) 251 return (0); 252 253 return (1); 254 } 255 256 /* 257 * Attach a found zs. 258 */ 259 void 260 zs_ioasic_attach(parent, self, aux) 261 struct device *parent; 262 struct device *self; 263 void *aux; 264 { 265 struct zsc_softc *zs = (void *) self; 266 struct zsc_attach_args zs_args; 267 struct zs_chanstate *cs; 268 struct ioasicdev_attach_args *d = aux; 269 struct zshan *zc; 270 int s, channel; 271 272 printf("\n"); 273 274 /* 275 * Initialize software state for each channel. 276 */ 277 for (channel = 0; channel < 2; channel++) { 278 zs_args.channel = channel; 279 zs_args.hwflags = 0; 280 281 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 282 cs = &zs_ioasic_conschanstate_store; 283 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 284 } else { 285 cs = malloc(sizeof(struct zs_chanstate), 286 M_DEVBUF, M_NOWAIT); 287 memset(cs, 0, sizeof(struct zs_chanstate)); 288 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 289 cs->cs_reg_csr = (void *)&zc->zc_csr; 290 291 bcopy(zs_ioasic_init_reg, cs->cs_creg, 16); 292 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 293 294 cs->cs_defcflag = zs_def_cflag; 295 cs->cs_defspeed = 9600; /* XXX */ 296 (void) zs_set_modes(cs, cs->cs_defcflag); 297 } 298 299 zs->zsc_cs[channel] = cs; 300 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 301 cs->cs_channel = channel; 302 cs->cs_ops = &zsops_null; 303 cs->cs_brg_clk = PCLK / 16; 304 305 /* 306 * DCD and CTS interrupts are only meaningful on 307 * SCC 0/B. 308 * 309 * XXX This is sorta gross. 310 */ 311 if (d->iada_offset == 0x00100000 && channel == 1) { 312 cs->cs_creg[15] |= ZSWR15_DCD_IE; 313 cs->cs_preg[15] |= ZSWR15_DCD_IE; 314 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 315 } 316 else 317 cs->cs_private = NULL; 318 319 /* 320 * Clear the master interrupt enable. 321 * The INTENA is common to both channels, 322 * so just do it on the A channel. 323 */ 324 if (channel == 0) { 325 zs_write_reg(cs, 9, 0); 326 } 327 328 #ifdef notyet /* XXX thorpej */ 329 /* 330 * Set up the flow/modem control channel pointer to 331 * deal with the weird wiring on the TC Alpha and 332 * DECstation. 333 */ 334 if (channel == 1) 335 cs->cs_ctl_chan = zs->zsc_cs[0]; 336 else 337 cs->cs_ctl_chan = NULL; 338 #endif 339 340 /* 341 * Look for a child driver for this channel. 342 * The child attach will setup the hardware. 343 */ 344 if (config_found_sm(self, (void *)&zs_args, 345 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 346 /* No sub-driver. Just reset it. */ 347 u_char reset = (channel == 0) ? 348 ZSWR9_A_RESET : ZSWR9_B_RESET; 349 s = splhigh(); 350 zs_write_reg(cs, 9, reset); 351 splx(s); 352 } 353 } 354 355 /* 356 * Set up the ioasic interrupt handler. 357 */ 358 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 359 zs_ioasic_hardintr, zs); 360 zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, 361 zs_ioasic_softintr, zs); 362 if (zs->zsc_sih == NULL) 363 panic("zs_ioasic_attach: unable to register softintr"); 364 365 /* 366 * Set the master interrupt enable and interrupt vector. The 367 * Sun does this only on one channel. The old Alpha SCC driver 368 * did it on both. We'll do it on both. 369 */ 370 s = splhigh(); 371 /* interrupt vector */ 372 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 373 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 374 375 /* master interrupt control (enable) */ 376 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 377 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 378 #if defined(__alpha__) || defined(alpha) 379 /* ioasic interrupt enable */ 380 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 381 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 382 tc_mb(); 383 #endif 384 splx(s); 385 } 386 387 int 388 zs_ioasic_print(aux, name) 389 void *aux; 390 const char *name; 391 { 392 struct zsc_attach_args *args = aux; 393 394 if (name != NULL) 395 printf("%s:", name); 396 397 if (args->channel != -1) 398 printf(" channel %d", args->channel); 399 400 return (UNCONF); 401 } 402 403 int 404 zs_ioasic_submatch(parent, cf, aux) 405 struct device *parent; 406 struct cfdata *cf; 407 void *aux; 408 { 409 struct zsc_softc *zs = (void *)parent; 410 struct zsc_attach_args *pa = aux; 411 char *defname = ""; 412 413 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 414 cf->cf_loc[ZSCCF_CHANNEL] != pa->channel) 415 return (0); 416 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 417 if (pa->channel == 0) { 418 #if defined(pmax) 419 if (systype == DS_MAXINE) 420 return (0); 421 #endif 422 if (zs->zsc_addroffset == 0x100000) 423 defname = "vsms"; 424 else 425 defname = "lkkbd"; 426 } 427 else if (zs->zsc_addroffset == 0x100000) 428 defname = "zstty"; 429 #if defined(pmax) 430 else if (systype == DS_MAXINE) 431 return (0); 432 #endif 433 #if defined(__alpha__) || defined(alpha) 434 else if (cputype == ST_DEC_3000_300) 435 return (0); 436 #endif 437 else 438 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 439 440 if (strcmp(cf->cf_driver->cd_name, defname)) 441 return (0); 442 } 443 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 444 } 445 446 /* 447 * Hardware interrupt handler. 448 */ 449 int 450 zs_ioasic_hardintr(arg) 451 void *arg; 452 { 453 struct zsc_softc *zsc = arg; 454 455 /* 456 * Call the upper-level MI hardware interrupt handler. 457 */ 458 zsc_intr_hard(zsc); 459 460 /* 461 * Check to see if we need to schedule any software-level 462 * processing interrupts. 463 */ 464 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 465 softintr_schedule(zsc->zsc_sih); 466 467 return (1); 468 } 469 470 /* 471 * Software-level interrupt (character processing, lower priority). 472 */ 473 void 474 zs_ioasic_softintr(arg) 475 void *arg; 476 { 477 struct zsc_softc *zsc = arg; 478 int s; 479 480 s = spltty(); 481 (void) zsc_intr_soft(zsc); 482 splx(s); 483 } 484 485 /* 486 * MD functions for setting the baud rate and control modes. 487 */ 488 int 489 zs_set_speed(cs, bps) 490 struct zs_chanstate *cs; 491 int bps; /* bits per second */ 492 { 493 int tconst, real_bps; 494 495 if (bps == 0) 496 return (0); 497 498 #ifdef DIAGNOSTIC 499 if (cs->cs_brg_clk == 0) 500 panic("zs_set_speed"); 501 #endif 502 503 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 504 if (tconst < 0) 505 return (EINVAL); 506 507 /* Convert back to make sure we can do it. */ 508 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 509 510 /* XXX - Allow some tolerance here? */ 511 if (real_bps != bps) 512 return (EINVAL); 513 514 cs->cs_preg[12] = tconst; 515 cs->cs_preg[13] = tconst >> 8; 516 517 /* Caller will stuff the pending registers. */ 518 return (0); 519 } 520 521 int 522 zs_set_modes(cs, cflag) 523 struct zs_chanstate *cs; 524 int cflag; /* bits per second */ 525 { 526 u_long privflags = (u_long)cs->cs_private; 527 int s; 528 529 /* 530 * Output hardware flow control on the chip is horrendous: 531 * if carrier detect drops, the receiver is disabled, and if 532 * CTS drops, the transmitter is stoped IN MID CHARACTER! 533 * Therefore, NEVER set the HFC bit, and instead use the 534 * status interrupt to detect CTS changes. 535 */ 536 s = splzs(); 537 if ((cflag & (CLOCAL | MDMBUF)) != 0) 538 cs->cs_rr0_dcd = 0; 539 else 540 cs->cs_rr0_dcd = ZSRR0_DCD; 541 if ((cflag & CRTSCTS) != 0) { 542 cs->cs_wr5_dtr = ZSWR5_DTR; 543 cs->cs_wr5_rts = ZSWR5_RTS; 544 cs->cs_rr0_cts = ZSRR0_CTS; 545 } else if ((cflag & CDTRCTS) != 0) { 546 cs->cs_wr5_dtr = 0; 547 cs->cs_wr5_rts = ZSWR5_DTR; 548 cs->cs_rr0_cts = ZSRR0_CTS; 549 } else if ((cflag & MDMBUF) != 0) { 550 cs->cs_wr5_dtr = 0; 551 cs->cs_wr5_rts = ZSWR5_DTR; 552 cs->cs_rr0_cts = ZSRR0_DCD; 553 } else { 554 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 555 cs->cs_wr5_rts = 0; 556 cs->cs_rr0_cts = 0; 557 } 558 559 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 560 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 561 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 562 } 563 splx(s); 564 565 /* Caller will stuff the pending registers. */ 566 return (0); 567 } 568 569 /* 570 * Functions to read and write individual registers in a channel. 571 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 572 * and the Alpha TC hardware does NOT take care of this for you. 573 * The delay is now handled inside the chip access functions. 574 * These could be inlines, but with the delay, speed is moot. 575 */ 576 #if defined(pmax) 577 #undef DELAY 578 #define DELAY(x) 579 #endif 580 581 u_int 582 zs_read_reg(cs, reg) 583 struct zs_chanstate *cs; 584 u_int reg; 585 { 586 struct zshan *zc = (void *)cs->cs_reg_csr; 587 unsigned val; 588 589 zc->zc_csr = reg << 8; 590 tc_wmb(); 591 DELAY(5); 592 val = (zc->zc_csr >> 8) & 0xff; 593 /* tc_mb(); */ 594 DELAY(5); 595 return (val); 596 } 597 598 void 599 zs_write_reg(cs, reg, val) 600 struct zs_chanstate *cs; 601 u_int reg, val; 602 { 603 struct zshan *zc = (void *)cs->cs_reg_csr; 604 605 zc->zc_csr = reg << 8; 606 tc_wmb(); 607 DELAY(5); 608 zc->zc_csr = val << 8; 609 tc_wmb(); 610 DELAY(5); 611 } 612 613 u_int 614 zs_read_csr(cs) 615 struct zs_chanstate *cs; 616 { 617 struct zshan *zc = (void *)cs->cs_reg_csr; 618 unsigned val; 619 620 val = (zc->zc_csr >> 8) & 0xff; 621 /* tc_mb(); */ 622 DELAY(5); 623 return (val); 624 } 625 626 void 627 zs_write_csr(cs, val) 628 struct zs_chanstate *cs; 629 u_int val; 630 { 631 struct zshan *zc = (void *)cs->cs_reg_csr; 632 633 zc->zc_csr = val << 8; 634 tc_wmb(); 635 DELAY(5); 636 } 637 638 u_int 639 zs_read_data(cs) 640 struct zs_chanstate *cs; 641 { 642 struct zshan *zc = (void *)cs->cs_reg_csr; 643 unsigned val; 644 645 val = (zc->zc_data) >> 8 & 0xff; 646 /* tc_mb(); */ 647 DELAY(5); 648 return (val); 649 } 650 651 void 652 zs_write_data(cs, val) 653 struct zs_chanstate *cs; 654 u_int val; 655 { 656 struct zshan *zc = (void *)cs->cs_reg_csr; 657 658 zc->zc_data = val << 8; 659 tc_wmb(); 660 DELAY(5); 661 } 662 663 /**************************************************************** 664 * Console support functions 665 ****************************************************************/ 666 667 /* 668 * Handle user request to enter kernel debugger. 669 */ 670 void 671 zs_abort(cs) 672 struct zs_chanstate *cs; 673 { 674 int rr0; 675 676 /* Wait for end of break. */ 677 /* XXX - Limit the wait? */ 678 do { 679 rr0 = zs_read_csr(cs); 680 } while (rr0 & ZSRR0_BREAK); 681 682 #if defined(KGDB) 683 zskgdb(cs); 684 #elif defined(DDB) 685 Debugger(); 686 #else 687 printf("zs_abort: ignoring break on console\n"); 688 #endif 689 } 690 691 /* 692 * Polled input char. 693 */ 694 int 695 zs_getc(cs) 696 struct zs_chanstate *cs; 697 { 698 int s, c, rr0; 699 700 s = splhigh(); 701 /* Wait for a character to arrive. */ 702 do { 703 rr0 = zs_read_csr(cs); 704 } while ((rr0 & ZSRR0_RX_READY) == 0); 705 706 c = zs_read_data(cs); 707 splx(s); 708 709 /* 710 * This is used by the kd driver to read scan codes, 711 * so don't translate '\r' ==> '\n' here... 712 */ 713 return (c); 714 } 715 716 /* 717 * Polled output char. 718 */ 719 void 720 zs_putc(cs, c) 721 struct zs_chanstate *cs; 722 int c; 723 { 724 register int s, rr0; 725 726 s = splhigh(); 727 /* Wait for transmitter to become ready. */ 728 do { 729 rr0 = zs_read_csr(cs); 730 } while ((rr0 & ZSRR0_TX_READY) == 0); 731 732 zs_write_data(cs, c); 733 734 /* Wait for the character to be transmitted. */ 735 do { 736 rr0 = zs_read_csr(cs); 737 } while ((rr0 & ZSRR0_TX_READY) == 0); 738 splx(s); 739 } 740 741 /*****************************************************************/ 742 743 /* 744 * zs_ioasic_cninit -- 745 * Initialize the serial channel for either a keyboard or 746 * a serial console. 747 */ 748 void 749 zs_ioasic_cninit(ioasic_addr, zs_offset, channel) 750 tc_addr_t ioasic_addr; 751 tc_offset_t zs_offset; 752 int channel; 753 { 754 struct zs_chanstate *cs; 755 tc_addr_t zs_addr; 756 struct zshan *zc; 757 758 /* 759 * Initialize the console finder helpers. 760 */ 761 zs_ioasic_console_offset = zs_offset; 762 zs_ioasic_console_channel = channel; 763 zs_ioasic_console = 1; 764 765 /* 766 * Pointer to channel state. 767 */ 768 cs = &zs_ioasic_conschanstate_store; 769 770 /* 771 * Compute the physical address of the chip, "map" it via 772 * K0SEG, and then get the address of the actual channel. 773 */ 774 #if defined(__alpha__) || defined(alpha) 775 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 776 #endif 777 #if defined(pmax) 778 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 779 #endif 780 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 781 782 /* Setup temporary chanstate. */ 783 cs->cs_reg_csr = (void *)&zc->zc_csr; 784 785 cs->cs_channel = channel; 786 cs->cs_ops = &zsops_null; 787 cs->cs_brg_clk = PCLK / 16; 788 789 /* Initialize the pending registers. */ 790 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 791 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 792 793 /* 794 * DCD and CTS interrupts are only meaningful on 795 * SCC 0/B. 796 * 797 * XXX This is sorta gross. 798 */ 799 if (zs_offset == 0x00100000 && channel == 1) 800 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 801 else 802 cs->cs_private = NULL; 803 804 /* Clear the master interrupt enable. */ 805 zs_write_reg(cs, 9, 0); 806 807 /* Reset the whole SCC chip. */ 808 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 809 810 /* Copy "pending" to "current" and H/W. */ 811 zs_loadchannelregs(cs); 812 } 813 814 /* 815 * zs_ioasic_cnattach -- 816 * Initialize and attach a serial console. 817 */ 818 void 819 zs_ioasic_cnattach(ioasic_addr, zs_offset, channel) 820 tc_addr_t ioasic_addr; 821 tc_offset_t zs_offset; 822 int channel; 823 { 824 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 825 826 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 827 cs->cs_defspeed = 9600; 828 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 829 830 /* Point the console at the SCC. */ 831 cn_tab = &zs_ioasic_cons; 832 cn_tab->cn_pri = CN_REMOTE; 833 cn_tab->cn_dev = makedev(zs_major, (zs_offset == 0x100000) ? 0 : 1); 834 } 835 836 /* 837 * zs_ioasic_lk201_cnattach -- 838 * Initialize and attach a keyboard. 839 */ 840 int 841 zs_ioasic_lk201_cnattach(ioasic_addr, zs_offset, channel) 842 tc_addr_t ioasic_addr; 843 tc_offset_t zs_offset; 844 int channel; 845 { 846 #if (NZSKBD > 0) 847 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 848 849 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 850 cs->cs_defspeed = 4800; 851 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 852 return (zskbd_cnattach(cs)); 853 #else 854 return (ENXIO); 855 #endif 856 } 857 858 int 859 zs_ioasic_isconsole(offset, channel) 860 tc_offset_t offset; 861 int channel; 862 { 863 864 if (zs_ioasic_console && 865 offset == zs_ioasic_console_offset && 866 channel == zs_ioasic_console_channel) 867 return (1); 868 869 return (0); 870 } 871 872 /* 873 * Polled console input putchar. 874 */ 875 int 876 zs_ioasic_cngetc(dev) 877 dev_t dev; 878 { 879 880 return (zs_getc(&zs_ioasic_conschanstate_store)); 881 } 882 883 /* 884 * Polled console output putchar. 885 */ 886 void 887 zs_ioasic_cnputc(dev, c) 888 dev_t dev; 889 int c; 890 { 891 892 zs_putc(&zs_ioasic_conschanstate_store, c); 893 } 894 895 /* 896 * Set polling/no polling on console. 897 */ 898 void 899 zs_ioasic_cnpollc(dev, onoff) 900 dev_t dev; 901 int onoff; 902 { 903 904 /* XXX ??? */ 905 } 906