1 /* $NetBSD: zs_ioasic.c,v 1.42 2021/04/24 23:36:59 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 35 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 36 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 37 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 38 * 39 * Runs two serial lines per chip using slave drivers. 40 * Plain tty/async lines use the zstty slave. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.42 2021/04/24 23:36:59 thorpej Exp $"); 45 46 #include "opt_ddb.h" 47 #include "opt_kgdb.h" 48 #include "zskbd.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/conf.h> 53 #include <sys/device.h> 54 #include <sys/malloc.h> 55 #include <sys/file.h> 56 #include <sys/ioctl.h> 57 #include <sys/kernel.h> 58 #include <sys/proc.h> 59 #include <sys/tty.h> 60 #include <sys/time.h> 61 #include <sys/syslog.h> 62 #include <sys/intr.h> 63 64 #include <machine/autoconf.h> 65 #include <machine/z8530var.h> 66 67 #include <dev/cons.h> 68 #include <dev/ic/z8530reg.h> 69 70 #include <dev/tc/tcvar.h> 71 #include <dev/tc/ioasicreg.h> 72 #include <dev/tc/ioasicvar.h> 73 74 #include <dev/tc/zs_ioasicvar.h> 75 76 #if defined(__alpha__) || defined(alpha) 77 #include <machine/rpb.h> 78 #endif 79 #if defined(pmax) 80 #include <pmax/pmax/pmaxtype.h> 81 #endif 82 83 /* 84 * Helpers for console support. 85 */ 86 static void zs_ioasic_cninit(tc_addr_t, tc_offset_t, int); 87 static int zs_ioasic_cngetc(dev_t); 88 static void zs_ioasic_cnputc(dev_t, int); 89 static void zs_ioasic_cnpollc(dev_t, int); 90 91 struct consdev zs_ioasic_cons = { 92 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 93 zs_ioasic_cnpollc, NULL, NULL, NULL, NODEV, CN_NORMAL, 94 }; 95 96 static tc_offset_t zs_ioasic_console_offset; 97 static int zs_ioasic_console_channel; 98 static int zs_ioasic_console; 99 static struct zs_chanstate zs_ioasic_conschanstate_store; 100 101 static int zs_ioasic_isconsole(tc_offset_t, int); 102 static void zs_putc(struct zs_chanstate *, int); 103 104 /* 105 * Some warts needed by z8530tty.c 106 */ 107 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 108 109 /* 110 * ZS chips are feeded a 7.372 MHz clock. 111 */ 112 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 113 114 /* The layout of this is hardware-dependent (padding, order). */ 115 struct zshan { 116 #if defined(__alpha__) || defined(alpha) 117 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 118 u_int zc_pad0; 119 volatile u_int zc_data; /* data */ 120 u_int sc_pad1; 121 #endif 122 #if defined(pmax) 123 volatile uint16_t zc_csr; /* ctrl,status, and indirect access */ 124 unsigned : 16; 125 volatile uint16_t zc_data; /* data */ 126 unsigned : 16; 127 #endif 128 }; 129 130 struct zsdevice { 131 /* Yes, they are backwards. */ 132 struct zshan zs_chan_b; 133 struct zshan zs_chan_a; 134 }; 135 136 static const u_char zs_ioasic_init_reg[16] = { 137 0, /* 0: CMD (reset, etc.) */ 138 0, /* 1: No interrupts yet. */ 139 0xf0, /* 2: IVECT */ 140 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 141 ZSWR4_CLK_X16 | ZSWR4_ONESB, 142 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 143 0, /* 6: TXSYNC/SYNCLO */ 144 0, /* 7: RXSYNC/SYNCHI */ 145 0, /* 8: alias for data port */ 146 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 147 0, /*10: Misc. TX/RX control bits */ 148 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 149 22, /*12: BAUDLO (default=9600) */ 150 0, /*13: BAUDHI (default=9600) */ 151 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 152 ZSWR15_BREAK_IE, 153 }; 154 155 static struct zshan * 156 zs_ioasic_get_chan_addr(tc_addr_t zsaddr, int channel) 157 { 158 struct zsdevice *addr; 159 struct zshan *zc; 160 161 #if defined(__alpha__) || defined(alpha) 162 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 163 #endif 164 #if defined(pmax) 165 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 166 #endif 167 168 if (channel == 0) 169 zc = &addr->zs_chan_a; 170 else 171 zc = &addr->zs_chan_b; 172 173 return (zc); 174 } 175 176 177 /**************************************************************** 178 * Autoconfig 179 ****************************************************************/ 180 181 /* Definition of the driver for autoconfig. */ 182 static int zs_ioasic_match(device_t, cfdata_t, void *); 183 static void zs_ioasic_attach(device_t, device_t, void *); 184 static int zs_ioasic_print(void *, const char *name); 185 static int zs_ioasic_submatch(device_t, cfdata_t, 186 const int *, void *); 187 188 CFATTACH_DECL_NEW(zsc_ioasic, sizeof(struct zsc_softc), 189 zs_ioasic_match, zs_ioasic_attach, NULL, NULL); 190 191 /* Interrupt handlers. */ 192 static int zs_ioasic_hardintr(void *); 193 static void zs_ioasic_softintr(void *); 194 195 /* 196 * Is the zs chip present? 197 */ 198 static int 199 zs_ioasic_match(device_t parent, cfdata_t cf, void *aux) 200 { 201 struct ioasicdev_attach_args *d = aux; 202 tc_addr_t zs_addr; 203 204 /* 205 * Make sure that we're looking for the right kind of device. 206 */ 207 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 208 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 209 return (0); 210 211 /* 212 * Find out the device address, and check it for validity. 213 */ 214 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 215 if (tc_badaddr(zs_addr)) 216 return (0); 217 218 return (1); 219 } 220 221 /* 222 * Attach a found zs. 223 */ 224 static void 225 zs_ioasic_attach(device_t parent, device_t self, void *aux) 226 { 227 struct zsc_softc *zs = device_private(self); 228 struct zsc_attach_args zs_args; 229 struct zs_chanstate *cs; 230 struct ioasicdev_attach_args *d = aux; 231 struct zshan *zc; 232 int s, channel; 233 u_long zflg; 234 int locs[ZSCCF_NLOCS]; 235 236 zs->zsc_dev = self; 237 aprint_normal("\n"); 238 239 /* 240 * Initialize software state for each channel. 241 */ 242 for (channel = 0; channel < 2; channel++) { 243 zs_args.channel = channel; 244 zs_args.hwflags = 0; 245 246 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 247 cs = &zs_ioasic_conschanstate_store; 248 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 249 } else { 250 cs = malloc(sizeof(struct zs_chanstate), 251 M_DEVBUF, M_WAITOK | M_ZERO); 252 zs_lock_init(cs); 253 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 254 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 255 256 memcpy(cs->cs_creg, zs_ioasic_init_reg, 16); 257 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16); 258 259 cs->cs_defcflag = zs_def_cflag; 260 cs->cs_defspeed = 9600; /* XXX */ 261 (void)zs_set_modes(cs, cs->cs_defcflag); 262 } 263 264 zs->zsc_cs[channel] = cs; 265 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 266 cs->cs_channel = channel; 267 cs->cs_ops = &zsops_null; 268 cs->cs_brg_clk = PCLK / 16; 269 270 /* 271 * DCD and CTS interrupts are only meaningful on 272 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 273 * 274 * XXX This is sorta gross. 275 */ 276 if (d->iada_offset == 0x00100000 && channel == 1) { 277 cs->cs_creg[15] |= ZSWR15_DCD_IE; 278 cs->cs_preg[15] |= ZSWR15_DCD_IE; 279 zflg = ZIP_FLAGS_DCDCTS; 280 } else 281 zflg = 0; 282 if (channel == 1) 283 zflg |= ZIP_FLAGS_DTRRTS; 284 cs->cs_private = (void *)zflg; 285 286 /* 287 * Clear the master interrupt enable. 288 * The INTENA is common to both channels, 289 * so just do it on the A channel. 290 */ 291 if (channel == 0) { 292 zs_write_reg(cs, 9, 0); 293 } 294 295 /* 296 * Set up the flow/modem control channel pointer to 297 * deal with the weird wiring on the TC Alpha and 298 * DECstation. 299 */ 300 if (channel == 1) 301 cs->cs_ctl_chan = zs->zsc_cs[0]; 302 else 303 cs->cs_ctl_chan = NULL; 304 305 locs[ZSCCF_CHANNEL] = channel; 306 307 /* 308 * Look for a child driver for this channel. 309 * The child attach will setup the hardware. 310 */ 311 if (config_found(self, (void *)&zs_args, zs_ioasic_print, 312 CFARG_SUBMATCH, zs_ioasic_submatch, 313 CFARG_LOCATORS, locs, 314 CFARG_EOL) == NULL) { 315 /* No sub-driver. Just reset it. */ 316 uint8_t reset = (channel == 0) ? 317 ZSWR9_A_RESET : ZSWR9_B_RESET; 318 s = splhigh(); 319 zs_write_reg(cs, 9, reset); 320 splx(s); 321 } 322 } 323 324 /* 325 * Set up the ioasic interrupt handler. 326 */ 327 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 328 zs_ioasic_hardintr, zs); 329 zs->zsc_sih = softint_establish(SOFTINT_SERIAL, 330 zs_ioasic_softintr, zs); 331 if (zs->zsc_sih == NULL) 332 panic("%s: unable to register softintr", __func__); 333 334 /* 335 * Set the master interrupt enable and interrupt vector. The 336 * Sun does this only on one channel. The old Alpha SCC driver 337 * did it on both. We'll do it on both. 338 */ 339 s = splhigh(); 340 /* interrupt vector */ 341 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 342 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 343 344 /* master interrupt control (enable) */ 345 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 346 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 347 #if defined(__alpha__) || defined(alpha) 348 /* ioasic interrupt enable */ 349 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 350 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 351 tc_mb(); 352 #endif 353 splx(s); 354 } 355 356 static int 357 zs_ioasic_print(void *aux, const char *name) 358 { 359 struct zsc_attach_args *args = aux; 360 361 if (name != NULL) 362 aprint_normal("%s:", name); 363 364 if (args->channel != -1) 365 aprint_normal(" channel %d", args->channel); 366 367 return (UNCONF); 368 } 369 370 static int 371 zs_ioasic_submatch(device_t parent, cfdata_t cf, const int *locs, void *aux) 372 { 373 struct zsc_softc *zs = device_private(parent); 374 struct zsc_attach_args *pa = aux; 375 const char *defname = ""; 376 377 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 378 cf->cf_loc[ZSCCF_CHANNEL] != locs[ZSCCF_CHANNEL]) 379 return (0); 380 381 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 382 if (pa->channel == 0) { 383 #if defined(pmax) 384 if (systype == DS_MAXINE) 385 return (0); 386 #endif 387 if (zs->zsc_addroffset == 0x100000) 388 defname = "vsms"; 389 else 390 defname = "lkkbd"; 391 } 392 else if (zs->zsc_addroffset == 0x100000) 393 defname = "zstty"; 394 #if defined(pmax) 395 else if (systype == DS_MAXINE) 396 return (0); 397 #endif 398 #if defined(__alpha__) || defined(alpha) 399 else if (cputype == ST_DEC_3000_300) 400 return (0); 401 #endif 402 else 403 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 404 405 if (strcmp(cf->cf_name, defname)) 406 return (0); 407 } 408 return (config_match(parent, cf, aux)); 409 } 410 411 /* 412 * Hardware interrupt handler. 413 */ 414 static int 415 zs_ioasic_hardintr(void *arg) 416 { 417 struct zsc_softc *zsc = arg; 418 419 /* 420 * Call the upper-level MI hardware interrupt handler. 421 */ 422 zsc_intr_hard(zsc); 423 424 /* 425 * Check to see if we need to schedule any software-level 426 * processing interrupts. 427 */ 428 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 429 softint_schedule(zsc->zsc_sih); 430 431 return (1); 432 } 433 434 /* 435 * Software-level interrupt (character processing, lower priority). 436 */ 437 static void 438 zs_ioasic_softintr(void *arg) 439 { 440 struct zsc_softc *zsc = arg; 441 int s; 442 443 s = spltty(); 444 (void)zsc_intr_soft(zsc); 445 splx(s); 446 } 447 448 /* 449 * MD functions for setting the baud rate and control modes. 450 */ 451 int 452 zs_set_speed(struct zs_chanstate *cs, int bps /*bits per second*/) 453 { 454 int tconst, real_bps; 455 456 if (bps == 0) 457 return (0); 458 459 #ifdef DIAGNOSTIC 460 if (cs->cs_brg_clk == 0) 461 panic("zs_set_speed"); 462 #endif 463 464 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 465 if (tconst < 0) 466 return (EINVAL); 467 468 /* Convert back to make sure we can do it. */ 469 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 470 471 /* XXX - Allow some tolerance here? */ 472 if (real_bps != bps) 473 return (EINVAL); 474 475 cs->cs_preg[12] = tconst; 476 cs->cs_preg[13] = tconst >> 8; 477 478 /* Caller will stuff the pending registers. */ 479 return (0); 480 } 481 482 int 483 zs_set_modes(struct zs_chanstate *cs, int cflag) 484 { 485 u_long privflags = (u_long)cs->cs_private; 486 int s; 487 488 /* 489 * Output hardware flow control on the chip is horrendous: 490 * if carrier detect drops, the receiver is disabled, and if 491 * CTS drops, the transmitter is stoped IN MID CHARACTER! 492 * Therefore, NEVER set the HFC bit, and instead use the 493 * status interrupt to detect CTS changes. 494 */ 495 s = splzs(); 496 if ((cflag & (CLOCAL | MDMBUF)) != 0) 497 cs->cs_rr0_dcd = 0; 498 else 499 cs->cs_rr0_dcd = ZSRR0_DCD; 500 if ((cflag & CRTSCTS) != 0) { 501 cs->cs_wr5_dtr = ZSWR5_DTR; 502 cs->cs_wr5_rts = ZSWR5_RTS; 503 cs->cs_rr0_cts = ZSRR0_CTS; 504 } else if ((cflag & CDTRCTS) != 0) { 505 cs->cs_wr5_dtr = 0; 506 cs->cs_wr5_rts = ZSWR5_DTR; 507 cs->cs_rr0_cts = ZSRR0_CTS; 508 } else if ((cflag & MDMBUF) != 0) { 509 cs->cs_wr5_dtr = 0; 510 cs->cs_wr5_rts = ZSWR5_DTR; 511 cs->cs_rr0_cts = ZSRR0_DCD; 512 } else { 513 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 514 cs->cs_wr5_rts = 0; 515 cs->cs_rr0_cts = 0; 516 } 517 518 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 519 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 520 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 521 } 522 if ((privflags & ZIP_FLAGS_DTRRTS) == 0) { 523 cs->cs_wr5_dtr &= ~(ZSWR5_RTS|ZSWR5_DTR); 524 cs->cs_wr5_rts &= ~(ZSWR5_RTS|ZSWR5_DTR); 525 } 526 splx(s); 527 528 /* Caller will stuff the pending registers. */ 529 return (0); 530 } 531 532 /* 533 * Functions to read and write individual registers in a channel. 534 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 535 * and the Alpha TC hardware does NOT take care of this for you. 536 * The delay is now handled inside the chip access functions. 537 * These could be inlines, but with the delay, speed is moot. 538 */ 539 #if defined(pmax) 540 #undef DELAY 541 #define DELAY(x) 542 #endif 543 544 u_int 545 zs_read_reg(struct zs_chanstate *cs, u_int reg) 546 { 547 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 548 unsigned val; 549 550 zc->zc_csr = reg << 8; 551 tc_wmb(); 552 DELAY(5); 553 val = (zc->zc_csr >> 8) & 0xff; 554 /* tc_mb(); */ 555 DELAY(5); 556 return (val); 557 } 558 559 void 560 zs_write_reg(struct zs_chanstate *cs, u_int reg, u_int val) 561 { 562 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 563 564 zc->zc_csr = reg << 8; 565 tc_wmb(); 566 DELAY(5); 567 zc->zc_csr = val << 8; 568 tc_wmb(); 569 DELAY(5); 570 } 571 572 u_int 573 zs_read_csr(struct zs_chanstate *cs) 574 { 575 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 576 unsigned val; 577 578 val = (zc->zc_csr >> 8) & 0xff; 579 /* tc_mb(); */ 580 DELAY(5); 581 return (val); 582 } 583 584 void 585 zs_write_csr(struct zs_chanstate *cs, u_int val) 586 { 587 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 588 589 zc->zc_csr = val << 8; 590 tc_wmb(); 591 DELAY(5); 592 } 593 594 u_int 595 zs_read_data(struct zs_chanstate *cs) 596 { 597 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 598 unsigned val; 599 600 val = (zc->zc_data) >> 8 & 0xff; 601 /* tc_mb(); */ 602 DELAY(5); 603 return (val); 604 } 605 606 void 607 zs_write_data(struct zs_chanstate *cs, u_int val) 608 { 609 volatile struct zshan *zc = (volatile void *)cs->cs_reg_csr; 610 611 zc->zc_data = val << 8; 612 tc_wmb(); 613 DELAY(5); 614 } 615 616 /**************************************************************** 617 * Console support functions 618 ****************************************************************/ 619 620 /* 621 * Handle user request to enter kernel debugger. 622 */ 623 void 624 zs_abort(struct zs_chanstate *cs) 625 { 626 u_int rr0; 627 628 /* Wait for end of break. */ 629 /* XXX - Limit the wait? */ 630 do { 631 rr0 = zs_read_csr(cs); 632 } while (rr0 & ZSRR0_BREAK); 633 634 #if defined(KGDB) 635 zskgdb(cs); 636 #elif defined(DDB) 637 Debugger(); 638 #else 639 printf("zs_abort: ignoring break on console\n"); 640 #endif 641 } 642 643 /* 644 * Polled input char. 645 */ 646 int 647 zs_getc(struct zs_chanstate *cs) 648 { 649 int s, c; 650 u_int rr0; 651 652 s = splhigh(); 653 /* Wait for a character to arrive. */ 654 do { 655 rr0 = zs_read_csr(cs); 656 } while ((rr0 & ZSRR0_RX_READY) == 0); 657 658 c = zs_read_data(cs); 659 splx(s); 660 661 /* 662 * This is used by the kd driver to read scan codes, 663 * so don't translate '\r' ==> '\n' here... 664 */ 665 return (c); 666 } 667 668 /* 669 * Polled output char. 670 */ 671 static void 672 zs_putc(struct zs_chanstate *cs, int c) 673 { 674 int s; 675 u_int rr0; 676 677 s = splhigh(); 678 /* Wait for transmitter to become ready. */ 679 do { 680 rr0 = zs_read_csr(cs); 681 } while ((rr0 & ZSRR0_TX_READY) == 0); 682 683 zs_write_data(cs, c); 684 685 /* Wait for the character to be transmitted. */ 686 do { 687 rr0 = zs_read_csr(cs); 688 } while ((rr0 & ZSRR0_TX_READY) == 0); 689 splx(s); 690 } 691 692 /*****************************************************************/ 693 694 /* 695 * zs_ioasic_cninit -- 696 * Initialize the serial channel for either a keyboard or 697 * a serial console. 698 */ 699 static void 700 zs_ioasic_cninit(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 701 { 702 struct zs_chanstate *cs; 703 tc_addr_t zs_addr; 704 struct zshan *zc; 705 u_long zflg; 706 707 /* 708 * Initialize the console finder helpers. 709 */ 710 zs_ioasic_console_offset = zs_offset; 711 zs_ioasic_console_channel = channel; 712 zs_ioasic_console = 1; 713 714 /* 715 * Pointer to channel state. 716 */ 717 cs = &zs_ioasic_conschanstate_store; 718 719 /* 720 * Compute the physical address of the chip, "map" it via 721 * K0SEG, and then get the address of the actual channel. 722 */ 723 #if defined(__alpha__) || defined(alpha) 724 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 725 #endif 726 #if defined(pmax) 727 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 728 #endif 729 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 730 731 /* Setup temporary chanstate. */ 732 cs->cs_reg_csr = (volatile void *)&zc->zc_csr; 733 734 cs->cs_channel = channel; 735 cs->cs_ops = &zsops_null; 736 cs->cs_brg_clk = PCLK / 16; 737 738 /* Initialize the pending registers. */ 739 memcpy(cs->cs_preg, zs_ioasic_init_reg, 16); 740 /* cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); */ 741 742 /* 743 * DCD and CTS interrupts are only meaningful on 744 * SCC 0/B, and RTS and DTR only on B of SCC 0 & 1. 745 * 746 * XXX This is sorta gross. 747 */ 748 if (zs_offset == 0x00100000 && channel == 1) 749 zflg = ZIP_FLAGS_DCDCTS; 750 else 751 zflg = 0; 752 if (channel == 1) 753 zflg |= ZIP_FLAGS_DTRRTS; 754 cs->cs_private = (void *)zflg; 755 756 /* Clear the master interrupt enable. */ 757 zs_write_reg(cs, 9, 0); 758 759 /* Reset the whole SCC chip. */ 760 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 761 762 /* Copy "pending" to "current" and H/W. */ 763 zs_loadchannelregs(cs); 764 } 765 766 /* 767 * zs_ioasic_cnattach -- 768 * Initialize and attach a serial console. 769 */ 770 void 771 zs_ioasic_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, int channel) 772 { 773 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 774 extern const struct cdevsw zstty_cdevsw; 775 776 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 777 zs_lock_init(cs); 778 cs->cs_defspeed = 9600; 779 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 780 781 /* Point the console at the SCC. */ 782 cn_tab = &zs_ioasic_cons; 783 cn_tab->cn_pri = CN_REMOTE; 784 cn_tab->cn_dev = makedev(cdevsw_lookup_major(&zstty_cdevsw), 785 (zs_offset == 0x100000) ? 0 : 1); 786 } 787 788 /* 789 * zs_ioasic_lk201_cnattach -- 790 * Initialize and attach a keyboard. 791 */ 792 int 793 zs_ioasic_lk201_cnattach(tc_addr_t ioasic_addr, tc_offset_t zs_offset, 794 int channel) 795 { 796 #if (NZSKBD > 0) 797 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 798 799 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 800 zs_lock_init(cs); 801 cs->cs_defspeed = 4800; 802 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 803 return (zskbd_cnattach(cs)); 804 #else 805 return (ENXIO); 806 #endif 807 } 808 809 static int 810 zs_ioasic_isconsole(tc_offset_t offset, int channel) 811 { 812 813 if (zs_ioasic_console && 814 offset == zs_ioasic_console_offset && 815 channel == zs_ioasic_console_channel) 816 return (1); 817 818 return (0); 819 } 820 821 /* 822 * Polled console input putchar. 823 */ 824 static int 825 zs_ioasic_cngetc(dev_t dev) 826 { 827 828 return (zs_getc(&zs_ioasic_conschanstate_store)); 829 } 830 831 /* 832 * Polled console output putchar. 833 */ 834 static void 835 zs_ioasic_cnputc(dev_t dev, int c) 836 { 837 838 zs_putc(&zs_ioasic_conschanstate_store, c); 839 } 840 841 /* 842 * Set polling/no polling on console. 843 */ 844 static void 845 zs_ioasic_cnpollc(dev_t dev, int onoff) 846 { 847 848 /* XXX ??? */ 849 } 850