1 /* $NetBSD: zs_ioasic.c,v 1.10 2002/01/12 16:29:31 tsutsui Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 42 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 43 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 44 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 45 * 46 * Runs two serial lines per chip using slave drivers. 47 * Plain tty/async lines use the zstty slave. 48 */ 49 50 #include <sys/cdefs.h> 51 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.10 2002/01/12 16:29:31 tsutsui Exp $"); 52 53 #include "opt_ddb.h" 54 #include "opt_kgdb.h" 55 #include "zskbd.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/conf.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/file.h> 63 #include <sys/ioctl.h> 64 #include <sys/kernel.h> 65 #include <sys/proc.h> 66 #include <sys/tty.h> 67 #include <sys/time.h> 68 #include <sys/syslog.h> 69 70 #include <machine/autoconf.h> 71 #include <machine/intr.h> 72 #include <machine/z8530var.h> 73 74 #include <dev/cons.h> 75 #include <dev/ic/z8530reg.h> 76 77 #include <dev/tc/tcvar.h> 78 #include <dev/tc/ioasicreg.h> 79 #include <dev/tc/ioasicvar.h> 80 81 #include <dev/tc/zs_ioasicvar.h> 82 83 #if defined(__alpha__) || defined(alpha) 84 #include <machine/rpb.h> 85 #endif 86 #if defined(pmax) 87 #include <pmax/pmax/pmaxtype.h> 88 #endif 89 90 /* 91 * Helpers for console support. 92 */ 93 void zs_ioasic_cninit __P((tc_addr_t, tc_offset_t, int)); 94 int zs_ioasic_cngetc __P((dev_t)); 95 void zs_ioasic_cnputc __P((dev_t, int)); 96 void zs_ioasic_cnpollc __P((dev_t, int)); 97 98 struct consdev zs_ioasic_cons = { 99 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 100 zs_ioasic_cnpollc, NULL, NODEV, CN_NORMAL, 101 }; 102 103 tc_offset_t zs_ioasic_console_offset; 104 int zs_ioasic_console_channel; 105 int zs_ioasic_console; 106 struct zs_chanstate zs_ioasic_conschanstate_store; 107 108 int zs_ioasic_isconsole __P((tc_offset_t, int)); 109 int zs_getc __P((struct zs_chanstate *)); 110 void zs_putc __P((struct zs_chanstate *, int)); 111 112 /* 113 * Some warts needed by z8530tty.c 114 */ 115 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 116 #if defined(__alpha__) || defined(alpha) 117 int zs_major = 15; 118 #endif 119 #if defined(pmax) 120 int zs_major = 17; 121 #endif 122 123 /* 124 * ZS chips are feeded a 7.372 MHz clock. 125 */ 126 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 127 128 /* The layout of this is hardware-dependent (padding, order). */ 129 struct zshan { 130 #if defined(__alpha__) || defined(alpha) 131 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 132 u_int zc_pad0; 133 volatile u_int zc_data; /* data */ 134 u_int sc_pad1; 135 #endif 136 #if defined(pmax) 137 volatile u_int16_t zc_csr; /* ctrl,status, and indirect access */ 138 unsigned : 16; 139 volatile u_int16_t zc_data; /* data */ 140 unsigned : 16; 141 #endif 142 }; 143 144 struct zsdevice { 145 /* Yes, they are backwards. */ 146 struct zshan zs_chan_b; 147 struct zshan zs_chan_a; 148 }; 149 150 static u_char zs_ioasic_init_reg[16] = { 151 0, /* 0: CMD (reset, etc.) */ 152 0, /* 1: No interrupts yet. */ 153 0xf0, /* 2: IVECT */ 154 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 155 ZSWR4_CLK_X16 | ZSWR4_ONESB, 156 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 157 0, /* 6: TXSYNC/SYNCLO */ 158 0, /* 7: RXSYNC/SYNCHI */ 159 0, /* 8: alias for data port */ 160 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 161 0, /*10: Misc. TX/RX control bits */ 162 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 163 22, /*12: BAUDLO (default=9600) */ 164 0, /*13: BAUDHI (default=9600) */ 165 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 166 ZSWR15_BREAK_IE, 167 }; 168 169 struct zshan *zs_ioasic_get_chan_addr __P((tc_addr_t, int)); 170 171 struct zshan * 172 zs_ioasic_get_chan_addr(zsaddr, channel) 173 tc_addr_t zsaddr; 174 int channel; 175 { 176 struct zsdevice *addr; 177 struct zshan *zc; 178 179 #if defined(__alpha__) || defined(alpha) 180 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 181 #endif 182 #if defined(pmax) 183 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 184 #endif 185 186 if (channel == 0) 187 zc = &addr->zs_chan_a; 188 else 189 zc = &addr->zs_chan_b; 190 191 return (zc); 192 } 193 194 195 /**************************************************************** 196 * Autoconfig 197 ****************************************************************/ 198 199 /* Definition of the driver for autoconfig. */ 200 int zs_ioasic_match __P((struct device *, struct cfdata *, void *)); 201 void zs_ioasic_attach __P((struct device *, struct device *, void *)); 202 int zs_ioasic_print __P((void *, const char *name)); 203 int zs_ioasic_submatch __P((struct device *, struct cfdata *, void *)); 204 205 struct cfattach zsc_ioasic_ca = { 206 sizeof(struct zsc_softc), zs_ioasic_match, zs_ioasic_attach 207 }; 208 209 /* Interrupt handlers. */ 210 int zs_ioasic_hardintr __P((void *)); 211 void zs_ioasic_softintr __P((void *)); 212 213 extern struct cfdriver ioasic_cd; 214 215 /* 216 * Is the zs chip present? 217 */ 218 int 219 zs_ioasic_match(parent, cf, aux) 220 struct device *parent; 221 struct cfdata *cf; 222 void *aux; 223 { 224 struct ioasicdev_attach_args *d = aux; 225 tc_addr_t zs_addr; 226 227 if (parent->dv_cfdata->cf_driver != &ioasic_cd) 228 return (0); 229 230 /* 231 * Make sure that we're looking for the right kind of device. 232 */ 233 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 234 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 235 return (0); 236 237 /* 238 * Check user-specified offset against the ioasic offset. 239 * Allow it to be wildcarded. 240 */ 241 if (cf->cf_loc[IOASICCF_OFFSET] != IOASICCF_OFFSET_DEFAULT && 242 cf->cf_loc[IOASICCF_OFFSET] != d->iada_offset) 243 return (0); 244 245 /* 246 * Find out the device address, and check it for validity. 247 */ 248 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 249 if (tc_badaddr(zs_addr)) 250 return (0); 251 252 return (1); 253 } 254 255 /* 256 * Attach a found zs. 257 */ 258 void 259 zs_ioasic_attach(parent, self, aux) 260 struct device *parent; 261 struct device *self; 262 void *aux; 263 { 264 struct zsc_softc *zs = (void *) self; 265 struct zsc_attach_args zs_args; 266 struct zs_chanstate *cs; 267 struct ioasicdev_attach_args *d = aux; 268 struct zshan *zc; 269 int s, channel; 270 271 printf("\n"); 272 273 /* 274 * Initialize software state for each channel. 275 */ 276 for (channel = 0; channel < 2; channel++) { 277 zs_args.channel = channel; 278 zs_args.hwflags = 0; 279 280 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 281 cs = &zs_ioasic_conschanstate_store; 282 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 283 } else { 284 cs = malloc(sizeof(struct zs_chanstate), 285 M_DEVBUF, M_NOWAIT|M_ZERO); 286 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 287 cs->cs_reg_csr = (void *)&zc->zc_csr; 288 289 bcopy(zs_ioasic_init_reg, cs->cs_creg, 16); 290 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 291 292 cs->cs_defcflag = zs_def_cflag; 293 cs->cs_defspeed = 9600; /* XXX */ 294 (void) zs_set_modes(cs, cs->cs_defcflag); 295 } 296 297 zs->zsc_cs[channel] = cs; 298 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 299 cs->cs_channel = channel; 300 cs->cs_ops = &zsops_null; 301 cs->cs_brg_clk = PCLK / 16; 302 303 /* 304 * DCD and CTS interrupts are only meaningful on 305 * SCC 0/B. 306 * 307 * XXX This is sorta gross. 308 */ 309 if (d->iada_offset == 0x00100000 && channel == 1) { 310 cs->cs_creg[15] |= ZSWR15_DCD_IE; 311 cs->cs_preg[15] |= ZSWR15_DCD_IE; 312 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 313 } 314 else 315 cs->cs_private = NULL; 316 317 /* 318 * Clear the master interrupt enable. 319 * The INTENA is common to both channels, 320 * so just do it on the A channel. 321 */ 322 if (channel == 0) { 323 zs_write_reg(cs, 9, 0); 324 } 325 326 #ifdef notyet /* XXX thorpej */ 327 /* 328 * Set up the flow/modem control channel pointer to 329 * deal with the weird wiring on the TC Alpha and 330 * DECstation. 331 */ 332 if (channel == 1) 333 cs->cs_ctl_chan = zs->zsc_cs[0]; 334 else 335 cs->cs_ctl_chan = NULL; 336 #endif 337 338 /* 339 * Look for a child driver for this channel. 340 * The child attach will setup the hardware. 341 */ 342 if (config_found_sm(self, (void *)&zs_args, 343 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 344 /* No sub-driver. Just reset it. */ 345 u_char reset = (channel == 0) ? 346 ZSWR9_A_RESET : ZSWR9_B_RESET; 347 s = splhigh(); 348 zs_write_reg(cs, 9, reset); 349 splx(s); 350 } 351 } 352 353 /* 354 * Set up the ioasic interrupt handler. 355 */ 356 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 357 zs_ioasic_hardintr, zs); 358 zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, 359 zs_ioasic_softintr, zs); 360 if (zs->zsc_sih == NULL) 361 panic("zs_ioasic_attach: unable to register softintr"); 362 363 /* 364 * Set the master interrupt enable and interrupt vector. The 365 * Sun does this only on one channel. The old Alpha SCC driver 366 * did it on both. We'll do it on both. 367 */ 368 s = splhigh(); 369 /* interrupt vector */ 370 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 371 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 372 373 /* master interrupt control (enable) */ 374 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 375 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 376 #if defined(__alpha__) || defined(alpha) 377 /* ioasic interrupt enable */ 378 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 379 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 380 tc_mb(); 381 #endif 382 splx(s); 383 } 384 385 int 386 zs_ioasic_print(aux, name) 387 void *aux; 388 const char *name; 389 { 390 struct zsc_attach_args *args = aux; 391 392 if (name != NULL) 393 printf("%s:", name); 394 395 if (args->channel != -1) 396 printf(" channel %d", args->channel); 397 398 return (UNCONF); 399 } 400 401 int 402 zs_ioasic_submatch(parent, cf, aux) 403 struct device *parent; 404 struct cfdata *cf; 405 void *aux; 406 { 407 struct zsc_softc *zs = (void *)parent; 408 struct zsc_attach_args *pa = aux; 409 char *defname = ""; 410 411 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 412 cf->cf_loc[ZSCCF_CHANNEL] != pa->channel) 413 return (0); 414 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 415 if (pa->channel == 0) { 416 #if defined(pmax) 417 if (systype == DS_MAXINE) 418 return (0); 419 #endif 420 if (zs->zsc_addroffset == 0x100000) 421 defname = "vsms"; 422 else 423 defname = "lkkbd"; 424 } 425 else if (zs->zsc_addroffset == 0x100000) 426 defname = "zstty"; 427 #if defined(pmax) 428 else if (systype == DS_MAXINE) 429 return (0); 430 #endif 431 #if defined(__alpha__) || defined(alpha) 432 else if (cputype == ST_DEC_3000_300) 433 return (0); 434 #endif 435 else 436 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 437 438 if (strcmp(cf->cf_driver->cd_name, defname)) 439 return (0); 440 } 441 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 442 } 443 444 /* 445 * Hardware interrupt handler. 446 */ 447 int 448 zs_ioasic_hardintr(arg) 449 void *arg; 450 { 451 struct zsc_softc *zsc = arg; 452 453 /* 454 * Call the upper-level MI hardware interrupt handler. 455 */ 456 zsc_intr_hard(zsc); 457 458 /* 459 * Check to see if we need to schedule any software-level 460 * processing interrupts. 461 */ 462 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 463 softintr_schedule(zsc->zsc_sih); 464 465 return (1); 466 } 467 468 /* 469 * Software-level interrupt (character processing, lower priority). 470 */ 471 void 472 zs_ioasic_softintr(arg) 473 void *arg; 474 { 475 struct zsc_softc *zsc = arg; 476 int s; 477 478 s = spltty(); 479 (void) zsc_intr_soft(zsc); 480 splx(s); 481 } 482 483 /* 484 * MD functions for setting the baud rate and control modes. 485 */ 486 int 487 zs_set_speed(cs, bps) 488 struct zs_chanstate *cs; 489 int bps; /* bits per second */ 490 { 491 int tconst, real_bps; 492 493 if (bps == 0) 494 return (0); 495 496 #ifdef DIAGNOSTIC 497 if (cs->cs_brg_clk == 0) 498 panic("zs_set_speed"); 499 #endif 500 501 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 502 if (tconst < 0) 503 return (EINVAL); 504 505 /* Convert back to make sure we can do it. */ 506 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 507 508 /* XXX - Allow some tolerance here? */ 509 if (real_bps != bps) 510 return (EINVAL); 511 512 cs->cs_preg[12] = tconst; 513 cs->cs_preg[13] = tconst >> 8; 514 515 /* Caller will stuff the pending registers. */ 516 return (0); 517 } 518 519 int 520 zs_set_modes(cs, cflag) 521 struct zs_chanstate *cs; 522 int cflag; /* bits per second */ 523 { 524 u_long privflags = (u_long)cs->cs_private; 525 int s; 526 527 /* 528 * Output hardware flow control on the chip is horrendous: 529 * if carrier detect drops, the receiver is disabled, and if 530 * CTS drops, the transmitter is stoped IN MID CHARACTER! 531 * Therefore, NEVER set the HFC bit, and instead use the 532 * status interrupt to detect CTS changes. 533 */ 534 s = splzs(); 535 if ((cflag & (CLOCAL | MDMBUF)) != 0) 536 cs->cs_rr0_dcd = 0; 537 else 538 cs->cs_rr0_dcd = ZSRR0_DCD; 539 if ((cflag & CRTSCTS) != 0) { 540 cs->cs_wr5_dtr = ZSWR5_DTR; 541 cs->cs_wr5_rts = ZSWR5_RTS; 542 cs->cs_rr0_cts = ZSRR0_CTS; 543 } else if ((cflag & CDTRCTS) != 0) { 544 cs->cs_wr5_dtr = 0; 545 cs->cs_wr5_rts = ZSWR5_DTR; 546 cs->cs_rr0_cts = ZSRR0_CTS; 547 } else if ((cflag & MDMBUF) != 0) { 548 cs->cs_wr5_dtr = 0; 549 cs->cs_wr5_rts = ZSWR5_DTR; 550 cs->cs_rr0_cts = ZSRR0_DCD; 551 } else { 552 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 553 cs->cs_wr5_rts = 0; 554 cs->cs_rr0_cts = 0; 555 } 556 557 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 558 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 559 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 560 } 561 splx(s); 562 563 /* Caller will stuff the pending registers. */ 564 return (0); 565 } 566 567 /* 568 * Functions to read and write individual registers in a channel. 569 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 570 * and the Alpha TC hardware does NOT take care of this for you. 571 * The delay is now handled inside the chip access functions. 572 * These could be inlines, but with the delay, speed is moot. 573 */ 574 #if defined(pmax) 575 #undef DELAY 576 #define DELAY(x) 577 #endif 578 579 u_int 580 zs_read_reg(cs, reg) 581 struct zs_chanstate *cs; 582 u_int reg; 583 { 584 struct zshan *zc = (void *)cs->cs_reg_csr; 585 unsigned val; 586 587 zc->zc_csr = reg << 8; 588 tc_wmb(); 589 DELAY(5); 590 val = (zc->zc_csr >> 8) & 0xff; 591 /* tc_mb(); */ 592 DELAY(5); 593 return (val); 594 } 595 596 void 597 zs_write_reg(cs, reg, val) 598 struct zs_chanstate *cs; 599 u_int reg, val; 600 { 601 struct zshan *zc = (void *)cs->cs_reg_csr; 602 603 zc->zc_csr = reg << 8; 604 tc_wmb(); 605 DELAY(5); 606 zc->zc_csr = val << 8; 607 tc_wmb(); 608 DELAY(5); 609 } 610 611 u_int 612 zs_read_csr(cs) 613 struct zs_chanstate *cs; 614 { 615 struct zshan *zc = (void *)cs->cs_reg_csr; 616 unsigned val; 617 618 val = (zc->zc_csr >> 8) & 0xff; 619 /* tc_mb(); */ 620 DELAY(5); 621 return (val); 622 } 623 624 void 625 zs_write_csr(cs, val) 626 struct zs_chanstate *cs; 627 u_int val; 628 { 629 struct zshan *zc = (void *)cs->cs_reg_csr; 630 631 zc->zc_csr = val << 8; 632 tc_wmb(); 633 DELAY(5); 634 } 635 636 u_int 637 zs_read_data(cs) 638 struct zs_chanstate *cs; 639 { 640 struct zshan *zc = (void *)cs->cs_reg_csr; 641 unsigned val; 642 643 val = (zc->zc_data) >> 8 & 0xff; 644 /* tc_mb(); */ 645 DELAY(5); 646 return (val); 647 } 648 649 void 650 zs_write_data(cs, val) 651 struct zs_chanstate *cs; 652 u_int val; 653 { 654 struct zshan *zc = (void *)cs->cs_reg_csr; 655 656 zc->zc_data = val << 8; 657 tc_wmb(); 658 DELAY(5); 659 } 660 661 /**************************************************************** 662 * Console support functions 663 ****************************************************************/ 664 665 /* 666 * Handle user request to enter kernel debugger. 667 */ 668 void 669 zs_abort(cs) 670 struct zs_chanstate *cs; 671 { 672 int rr0; 673 674 /* Wait for end of break. */ 675 /* XXX - Limit the wait? */ 676 do { 677 rr0 = zs_read_csr(cs); 678 } while (rr0 & ZSRR0_BREAK); 679 680 #if defined(KGDB) 681 zskgdb(cs); 682 #elif defined(DDB) 683 Debugger(); 684 #else 685 printf("zs_abort: ignoring break on console\n"); 686 #endif 687 } 688 689 /* 690 * Polled input char. 691 */ 692 int 693 zs_getc(cs) 694 struct zs_chanstate *cs; 695 { 696 int s, c, rr0; 697 698 s = splhigh(); 699 /* Wait for a character to arrive. */ 700 do { 701 rr0 = zs_read_csr(cs); 702 } while ((rr0 & ZSRR0_RX_READY) == 0); 703 704 c = zs_read_data(cs); 705 splx(s); 706 707 /* 708 * This is used by the kd driver to read scan codes, 709 * so don't translate '\r' ==> '\n' here... 710 */ 711 return (c); 712 } 713 714 /* 715 * Polled output char. 716 */ 717 void 718 zs_putc(cs, c) 719 struct zs_chanstate *cs; 720 int c; 721 { 722 register int s, rr0; 723 724 s = splhigh(); 725 /* Wait for transmitter to become ready. */ 726 do { 727 rr0 = zs_read_csr(cs); 728 } while ((rr0 & ZSRR0_TX_READY) == 0); 729 730 zs_write_data(cs, c); 731 732 /* Wait for the character to be transmitted. */ 733 do { 734 rr0 = zs_read_csr(cs); 735 } while ((rr0 & ZSRR0_TX_READY) == 0); 736 splx(s); 737 } 738 739 /*****************************************************************/ 740 741 /* 742 * zs_ioasic_cninit -- 743 * Initialize the serial channel for either a keyboard or 744 * a serial console. 745 */ 746 void 747 zs_ioasic_cninit(ioasic_addr, zs_offset, channel) 748 tc_addr_t ioasic_addr; 749 tc_offset_t zs_offset; 750 int channel; 751 { 752 struct zs_chanstate *cs; 753 tc_addr_t zs_addr; 754 struct zshan *zc; 755 756 /* 757 * Initialize the console finder helpers. 758 */ 759 zs_ioasic_console_offset = zs_offset; 760 zs_ioasic_console_channel = channel; 761 zs_ioasic_console = 1; 762 763 /* 764 * Pointer to channel state. 765 */ 766 cs = &zs_ioasic_conschanstate_store; 767 768 /* 769 * Compute the physical address of the chip, "map" it via 770 * K0SEG, and then get the address of the actual channel. 771 */ 772 #if defined(__alpha__) || defined(alpha) 773 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 774 #endif 775 #if defined(pmax) 776 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 777 #endif 778 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 779 780 /* Setup temporary chanstate. */ 781 cs->cs_reg_csr = (void *)&zc->zc_csr; 782 783 cs->cs_channel = channel; 784 cs->cs_ops = &zsops_null; 785 cs->cs_brg_clk = PCLK / 16; 786 787 /* Initialize the pending registers. */ 788 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 789 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 790 791 /* 792 * DCD and CTS interrupts are only meaningful on 793 * SCC 0/B. 794 * 795 * XXX This is sorta gross. 796 */ 797 if (zs_offset == 0x00100000 && channel == 1) 798 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 799 else 800 cs->cs_private = NULL; 801 802 /* Clear the master interrupt enable. */ 803 zs_write_reg(cs, 9, 0); 804 805 /* Reset the whole SCC chip. */ 806 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 807 808 /* Copy "pending" to "current" and H/W. */ 809 zs_loadchannelregs(cs); 810 } 811 812 /* 813 * zs_ioasic_cnattach -- 814 * Initialize and attach a serial console. 815 */ 816 void 817 zs_ioasic_cnattach(ioasic_addr, zs_offset, channel) 818 tc_addr_t ioasic_addr; 819 tc_offset_t zs_offset; 820 int channel; 821 { 822 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 823 824 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 825 cs->cs_defspeed = 9600; 826 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 827 828 /* Point the console at the SCC. */ 829 cn_tab = &zs_ioasic_cons; 830 cn_tab->cn_pri = CN_REMOTE; 831 cn_tab->cn_dev = makedev(zs_major, (zs_offset == 0x100000) ? 0 : 1); 832 } 833 834 /* 835 * zs_ioasic_lk201_cnattach -- 836 * Initialize and attach a keyboard. 837 */ 838 int 839 zs_ioasic_lk201_cnattach(ioasic_addr, zs_offset, channel) 840 tc_addr_t ioasic_addr; 841 tc_offset_t zs_offset; 842 int channel; 843 { 844 #if (NZSKBD > 0) 845 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 846 847 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 848 cs->cs_defspeed = 4800; 849 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 850 return (zskbd_cnattach(cs)); 851 #else 852 return (ENXIO); 853 #endif 854 } 855 856 int 857 zs_ioasic_isconsole(offset, channel) 858 tc_offset_t offset; 859 int channel; 860 { 861 862 if (zs_ioasic_console && 863 offset == zs_ioasic_console_offset && 864 channel == zs_ioasic_console_channel) 865 return (1); 866 867 return (0); 868 } 869 870 /* 871 * Polled console input putchar. 872 */ 873 int 874 zs_ioasic_cngetc(dev) 875 dev_t dev; 876 { 877 878 return (zs_getc(&zs_ioasic_conschanstate_store)); 879 } 880 881 /* 882 * Polled console output putchar. 883 */ 884 void 885 zs_ioasic_cnputc(dev, c) 886 dev_t dev; 887 int c; 888 { 889 890 zs_putc(&zs_ioasic_conschanstate_store, c); 891 } 892 893 /* 894 * Set polling/no polling on console. 895 */ 896 void 897 zs_ioasic_cnpollc(dev, onoff) 898 dev_t dev; 899 int onoff; 900 { 901 902 /* XXX ??? */ 903 } 904