1 /* $NetBSD: zs_ioasic.c,v 1.7 2001/05/30 15:24:25 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1996, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Gordon W. Ross, Ken Hornstein, and by Jason R. Thorpe of the 9 * Numerical Aerospace Simulation Facility, NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 41 42 __KERNEL_RCSID(0, "$NetBSD: zs_ioasic.c,v 1.7 2001/05/30 15:24:25 lukem Exp $"); 43 44 /* 45 * Zilog Z8530 Dual UART driver (machine-dependent part). This driver 46 * handles Z8530 chips attached to the DECstation/Alpha IOASIC. Modified 47 * for NetBSD/alpha by Ken Hornstein and Jason R. Thorpe. NetBSD/pmax 48 * adaption by Mattias Drochner. Merge work by Tohru Nishimura. 49 * 50 * Runs two serial lines per chip using slave drivers. 51 * Plain tty/async lines use the zstty slave. 52 */ 53 54 #include "opt_ddb.h" 55 #include "opt_kgdb.h" 56 #include "zskbd.h" 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/conf.h> 61 #include <sys/device.h> 62 #include <sys/malloc.h> 63 #include <sys/file.h> 64 #include <sys/ioctl.h> 65 #include <sys/kernel.h> 66 #include <sys/proc.h> 67 #include <sys/tty.h> 68 #include <sys/time.h> 69 #include <sys/syslog.h> 70 71 #include <machine/autoconf.h> 72 #include <machine/intr.h> 73 #include <machine/z8530var.h> 74 75 #include <dev/cons.h> 76 #include <dev/ic/z8530reg.h> 77 78 #include <dev/tc/tcvar.h> 79 #include <dev/tc/ioasicreg.h> 80 #include <dev/tc/ioasicvar.h> 81 82 #include <dev/tc/zs_ioasicvar.h> 83 84 #if defined(__alpha__) || defined(alpha) 85 #include <machine/rpb.h> 86 #endif 87 #if defined(pmax) 88 #include <pmax/pmax/pmaxtype.h> 89 #endif 90 91 /* 92 * Helpers for console support. 93 */ 94 void zs_ioasic_cninit __P((tc_addr_t, tc_offset_t, int)); 95 int zs_ioasic_cngetc __P((dev_t)); 96 void zs_ioasic_cnputc __P((dev_t, int)); 97 void zs_ioasic_cnpollc __P((dev_t, int)); 98 99 struct consdev zs_ioasic_cons = { 100 NULL, NULL, zs_ioasic_cngetc, zs_ioasic_cnputc, 101 zs_ioasic_cnpollc, NULL, NODEV, CN_NORMAL, 102 }; 103 104 tc_offset_t zs_ioasic_console_offset; 105 int zs_ioasic_console_channel; 106 int zs_ioasic_console; 107 struct zs_chanstate zs_ioasic_conschanstate_store; 108 109 int zs_ioasic_isconsole __P((tc_offset_t, int)); 110 int zs_getc __P((struct zs_chanstate *)); 111 void zs_putc __P((struct zs_chanstate *, int)); 112 113 /* 114 * Some warts needed by z8530tty.c 115 */ 116 int zs_def_cflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 117 #if defined(__alpha__) || defined(alpha) 118 int zs_major = 15; 119 #endif 120 #if defined(pmax) 121 int zs_major = 17; 122 #endif 123 124 /* 125 * ZS chips are feeded a 7.372 MHz clock. 126 */ 127 #define PCLK (9600 * 768) /* PCLK pin input clock rate */ 128 129 /* The layout of this is hardware-dependent (padding, order). */ 130 struct zshan { 131 #if defined(__alpha__) || defined(alpha) 132 volatile u_int zc_csr; /* ctrl,status, and indirect access */ 133 u_int zc_pad0; 134 volatile u_int zc_data; /* data */ 135 u_int sc_pad1; 136 #endif 137 #if defined(pmax) 138 volatile u_int16_t zc_csr; /* ctrl,status, and indirect access */ 139 unsigned : 16; 140 volatile u_int16_t zc_data; /* data */ 141 unsigned : 16; 142 #endif 143 }; 144 145 struct zsdevice { 146 /* Yes, they are backwards. */ 147 struct zshan zs_chan_b; 148 struct zshan zs_chan_a; 149 }; 150 151 static u_char zs_ioasic_init_reg[16] = { 152 0, /* 0: CMD (reset, etc.) */ 153 0, /* 1: No interrupts yet. */ 154 0xf0, /* 2: IVECT */ 155 ZSWR3_RX_8 | ZSWR3_RX_ENABLE, 156 ZSWR4_CLK_X16 | ZSWR4_ONESB, 157 ZSWR5_TX_8 | ZSWR5_TX_ENABLE, 158 0, /* 6: TXSYNC/SYNCLO */ 159 0, /* 7: RXSYNC/SYNCHI */ 160 0, /* 8: alias for data port */ 161 ZSWR9_MASTER_IE | ZSWR9_VECTOR_INCL_STAT, 162 0, /*10: Misc. TX/RX control bits */ 163 ZSWR11_TXCLK_BAUD | ZSWR11_RXCLK_BAUD, 164 22, /*12: BAUDLO (default=9600) */ 165 0, /*13: BAUDHI (default=9600) */ 166 ZSWR14_BAUD_ENA | ZSWR14_BAUD_FROM_PCLK, 167 ZSWR15_BREAK_IE, 168 }; 169 170 struct zshan *zs_ioasic_get_chan_addr __P((tc_addr_t, int)); 171 172 struct zshan * 173 zs_ioasic_get_chan_addr(zsaddr, channel) 174 tc_addr_t zsaddr; 175 int channel; 176 { 177 struct zsdevice *addr; 178 struct zshan *zc; 179 180 #if defined(__alpha__) || defined(alpha) 181 addr = (struct zsdevice *)TC_DENSE_TO_SPARSE(zsaddr); 182 #endif 183 #if defined(pmax) 184 addr = (struct zsdevice *)MIPS_PHYS_TO_KSEG1(zsaddr); 185 #endif 186 187 if (channel == 0) 188 zc = &addr->zs_chan_a; 189 else 190 zc = &addr->zs_chan_b; 191 192 return (zc); 193 } 194 195 196 /**************************************************************** 197 * Autoconfig 198 ****************************************************************/ 199 200 /* Definition of the driver for autoconfig. */ 201 int zs_ioasic_match __P((struct device *, struct cfdata *, void *)); 202 void zs_ioasic_attach __P((struct device *, struct device *, void *)); 203 int zs_ioasic_print __P((void *, const char *name)); 204 int zs_ioasic_submatch __P((struct device *, struct cfdata *, void *)); 205 206 struct cfattach zsc_ioasic_ca = { 207 sizeof(struct zsc_softc), zs_ioasic_match, zs_ioasic_attach 208 }; 209 210 /* Interrupt handlers. */ 211 int zs_ioasic_hardintr __P((void *)); 212 void zs_ioasic_softintr __P((void *)); 213 214 extern struct cfdriver ioasic_cd; 215 216 /* 217 * Is the zs chip present? 218 */ 219 int 220 zs_ioasic_match(parent, cf, aux) 221 struct device *parent; 222 struct cfdata *cf; 223 void *aux; 224 { 225 struct ioasicdev_attach_args *d = aux; 226 tc_addr_t zs_addr; 227 228 if (parent->dv_cfdata->cf_driver != &ioasic_cd) 229 return (0); 230 231 /* 232 * Make sure that we're looking for the right kind of device. 233 */ 234 if (strncmp(d->iada_modname, "z8530 ", TC_ROM_LLEN) != 0 && 235 strncmp(d->iada_modname, "scc", TC_ROM_LLEN) != 0) 236 return (0); 237 238 /* 239 * Check user-specified offset against the ioasic offset. 240 * Allow it to be wildcarded. 241 */ 242 if (cf->cf_loc[IOASICCF_OFFSET] != IOASICCF_OFFSET_DEFAULT && 243 cf->cf_loc[IOASICCF_OFFSET] != d->iada_offset) 244 return (0); 245 246 /* 247 * Find out the device address, and check it for validity. 248 */ 249 zs_addr = TC_DENSE_TO_SPARSE((tc_addr_t)d->iada_addr); 250 if (tc_badaddr(zs_addr)) 251 return (0); 252 253 return (1); 254 } 255 256 /* 257 * Attach a found zs. 258 */ 259 void 260 zs_ioasic_attach(parent, self, aux) 261 struct device *parent; 262 struct device *self; 263 void *aux; 264 { 265 struct zsc_softc *zs = (void *) self; 266 struct zsc_attach_args zs_args; 267 struct zs_chanstate *cs; 268 struct ioasicdev_attach_args *d = aux; 269 struct zshan *zc; 270 int s, channel; 271 272 printf("\n"); 273 274 /* 275 * Initialize software state for each channel. 276 */ 277 for (channel = 0; channel < 2; channel++) { 278 zs_args.channel = channel; 279 zs_args.hwflags = 0; 280 281 if (zs_ioasic_isconsole(d->iada_offset, channel)) { 282 cs = &zs_ioasic_conschanstate_store; 283 zs_args.hwflags |= ZS_HWFLAG_CONSOLE; 284 } else { 285 cs = malloc(sizeof(struct zs_chanstate), 286 M_DEVBUF, M_NOWAIT); 287 zc = zs_ioasic_get_chan_addr(d->iada_addr, channel); 288 cs->cs_reg_csr = (void *)&zc->zc_csr; 289 290 bcopy(zs_ioasic_init_reg, cs->cs_creg, 16); 291 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 292 293 cs->cs_defcflag = zs_def_cflag; 294 cs->cs_defspeed = 9600; /* XXX */ 295 (void) zs_set_modes(cs, cs->cs_defcflag); 296 } 297 298 zs->zsc_cs[channel] = cs; 299 zs->zsc_addroffset = d->iada_offset; /* cookie only */ 300 cs->cs_channel = channel; 301 cs->cs_ops = &zsops_null; 302 cs->cs_brg_clk = PCLK / 16; 303 304 /* 305 * DCD and CTS interrupts are only meaningful on 306 * SCC 0/B. 307 * 308 * XXX This is sorta gross. 309 */ 310 if (d->iada_offset == 0x00100000 && channel == 1) { 311 cs->cs_creg[15] |= ZSWR15_DCD_IE; 312 cs->cs_preg[15] |= ZSWR15_DCD_IE; 313 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 314 } 315 else 316 cs->cs_private = NULL; 317 318 /* 319 * Clear the master interrupt enable. 320 * The INTENA is common to both channels, 321 * so just do it on the A channel. 322 */ 323 if (channel == 0) { 324 zs_write_reg(cs, 9, 0); 325 } 326 327 #ifdef notyet /* XXX thorpej */ 328 /* 329 * Set up the flow/modem control channel pointer to 330 * deal with the weird wiring on the TC Alpha and 331 * DECstation. 332 */ 333 if (channel == 1) 334 cs->cs_ctl_chan = zs->zsc_cs[0]; 335 else 336 cs->cs_ctl_chan = NULL; 337 #endif 338 339 /* 340 * Look for a child driver for this channel. 341 * The child attach will setup the hardware. 342 */ 343 if (config_found_sm(self, (void *)&zs_args, 344 zs_ioasic_print, zs_ioasic_submatch) == NULL) { 345 /* No sub-driver. Just reset it. */ 346 u_char reset = (channel == 0) ? 347 ZSWR9_A_RESET : ZSWR9_B_RESET; 348 s = splhigh(); 349 zs_write_reg(cs, 9, reset); 350 splx(s); 351 } 352 } 353 354 /* 355 * Set up the ioasic interrupt handler. 356 */ 357 ioasic_intr_establish(parent, d->iada_cookie, TC_IPL_TTY, 358 zs_ioasic_hardintr, zs); 359 zs->zsc_sih = softintr_establish(IPL_SOFTSERIAL, 360 zs_ioasic_softintr, zs); 361 if (zs->zsc_sih == NULL) 362 panic("zs_ioasic_attach: unable to register softintr"); 363 364 /* 365 * Set the master interrupt enable and interrupt vector. The 366 * Sun does this only on one channel. The old Alpha SCC driver 367 * did it on both. We'll do it on both. 368 */ 369 s = splhigh(); 370 /* interrupt vector */ 371 zs_write_reg(zs->zsc_cs[0], 2, zs_ioasic_init_reg[2]); 372 zs_write_reg(zs->zsc_cs[1], 2, zs_ioasic_init_reg[2]); 373 374 /* master interrupt control (enable) */ 375 zs_write_reg(zs->zsc_cs[0], 9, zs_ioasic_init_reg[9]); 376 zs_write_reg(zs->zsc_cs[1], 9, zs_ioasic_init_reg[9]); 377 #if defined(__alpha__) || defined(alpha) 378 /* ioasic interrupt enable */ 379 *(volatile u_int *)(ioasic_base + IOASIC_IMSK) |= 380 IOASIC_INTR_SCC_1 | IOASIC_INTR_SCC_0; 381 tc_mb(); 382 #endif 383 splx(s); 384 } 385 386 int 387 zs_ioasic_print(aux, name) 388 void *aux; 389 const char *name; 390 { 391 struct zsc_attach_args *args = aux; 392 393 if (name != NULL) 394 printf("%s:", name); 395 396 if (args->channel != -1) 397 printf(" channel %d", args->channel); 398 399 return (UNCONF); 400 } 401 402 int 403 zs_ioasic_submatch(parent, cf, aux) 404 struct device *parent; 405 struct cfdata *cf; 406 void *aux; 407 { 408 struct zsc_softc *zs = (void *)parent; 409 struct zsc_attach_args *pa = aux; 410 char *defname = ""; 411 412 if (cf->cf_loc[ZSCCF_CHANNEL] != ZSCCF_CHANNEL_DEFAULT && 413 cf->cf_loc[ZSCCF_CHANNEL] != pa->channel) 414 return (0); 415 if (cf->cf_loc[ZSCCF_CHANNEL] == ZSCCF_CHANNEL_DEFAULT) { 416 if (pa->channel == 0) { 417 #if defined(pmax) 418 if (systype == DS_MAXINE) 419 return (0); 420 #endif 421 if (zs->zsc_addroffset == 0x100000) 422 defname = "vsms"; 423 else 424 defname = "lkkbd"; 425 } 426 else if (zs->zsc_addroffset == 0x100000) 427 defname = "zstty"; 428 #if defined(pmax) 429 else if (systype == DS_MAXINE) 430 return (0); 431 #endif 432 #if defined(__alpha__) || defined(alpha) 433 else if (cputype == ST_DEC_3000_300) 434 return (0); 435 #endif 436 else 437 defname = "zstty"; /* 3min/3max+, DEC3000/500 */ 438 439 if (strcmp(cf->cf_driver->cd_name, defname)) 440 return (0); 441 } 442 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 443 } 444 445 /* 446 * Hardware interrupt handler. 447 */ 448 int 449 zs_ioasic_hardintr(arg) 450 void *arg; 451 { 452 struct zsc_softc *zsc = arg; 453 454 /* 455 * Call the upper-level MI hardware interrupt handler. 456 */ 457 zsc_intr_hard(zsc); 458 459 /* 460 * Check to see if we need to schedule any software-level 461 * processing interrupts. 462 */ 463 if (zsc->zsc_cs[0]->cs_softreq | zsc->zsc_cs[1]->cs_softreq) 464 softintr_schedule(zsc->zsc_sih); 465 466 return (1); 467 } 468 469 /* 470 * Software-level interrupt (character processing, lower priority). 471 */ 472 void 473 zs_ioasic_softintr(arg) 474 void *arg; 475 { 476 struct zsc_softc *zsc = arg; 477 int s; 478 479 s = spltty(); 480 (void) zsc_intr_soft(zsc); 481 splx(s); 482 } 483 484 /* 485 * MD functions for setting the baud rate and control modes. 486 */ 487 int 488 zs_set_speed(cs, bps) 489 struct zs_chanstate *cs; 490 int bps; /* bits per second */ 491 { 492 int tconst, real_bps; 493 494 if (bps == 0) 495 return (0); 496 497 #ifdef DIAGNOSTIC 498 if (cs->cs_brg_clk == 0) 499 panic("zs_set_speed"); 500 #endif 501 502 tconst = BPS_TO_TCONST(cs->cs_brg_clk, bps); 503 if (tconst < 0) 504 return (EINVAL); 505 506 /* Convert back to make sure we can do it. */ 507 real_bps = TCONST_TO_BPS(cs->cs_brg_clk, tconst); 508 509 /* XXX - Allow some tolerance here? */ 510 if (real_bps != bps) 511 return (EINVAL); 512 513 cs->cs_preg[12] = tconst; 514 cs->cs_preg[13] = tconst >> 8; 515 516 /* Caller will stuff the pending registers. */ 517 return (0); 518 } 519 520 int 521 zs_set_modes(cs, cflag) 522 struct zs_chanstate *cs; 523 int cflag; /* bits per second */ 524 { 525 u_long privflags = (u_long)cs->cs_private; 526 int s; 527 528 /* 529 * Output hardware flow control on the chip is horrendous: 530 * if carrier detect drops, the receiver is disabled, and if 531 * CTS drops, the transmitter is stoped IN MID CHARACTER! 532 * Therefore, NEVER set the HFC bit, and instead use the 533 * status interrupt to detect CTS changes. 534 */ 535 s = splzs(); 536 if ((cflag & (CLOCAL | MDMBUF)) != 0) 537 cs->cs_rr0_dcd = 0; 538 else 539 cs->cs_rr0_dcd = ZSRR0_DCD; 540 if ((cflag & CRTSCTS) != 0) { 541 cs->cs_wr5_dtr = ZSWR5_DTR; 542 cs->cs_wr5_rts = ZSWR5_RTS; 543 cs->cs_rr0_cts = ZSRR0_CTS; 544 } else if ((cflag & CDTRCTS) != 0) { 545 cs->cs_wr5_dtr = 0; 546 cs->cs_wr5_rts = ZSWR5_DTR; 547 cs->cs_rr0_cts = ZSRR0_CTS; 548 } else if ((cflag & MDMBUF) != 0) { 549 cs->cs_wr5_dtr = 0; 550 cs->cs_wr5_rts = ZSWR5_DTR; 551 cs->cs_rr0_cts = ZSRR0_DCD; 552 } else { 553 cs->cs_wr5_dtr = ZSWR5_DTR | ZSWR5_RTS; 554 cs->cs_wr5_rts = 0; 555 cs->cs_rr0_cts = 0; 556 } 557 558 if ((privflags & ZIP_FLAGS_DCDCTS) == 0) { 559 cs->cs_rr0_dcd &= ~(ZSRR0_CTS|ZSRR0_DCD); 560 cs->cs_rr0_cts &= ~(ZSRR0_CTS|ZSRR0_DCD); 561 } 562 splx(s); 563 564 /* Caller will stuff the pending registers. */ 565 return (0); 566 } 567 568 /* 569 * Functions to read and write individual registers in a channel. 570 * The ZS chip requires a 1.6 uSec. recovery time between accesses, 571 * and the Alpha TC hardware does NOT take care of this for you. 572 * The delay is now handled inside the chip access functions. 573 * These could be inlines, but with the delay, speed is moot. 574 */ 575 #if defined(pmax) 576 #undef DELAY 577 #define DELAY(x) 578 #endif 579 580 u_int 581 zs_read_reg(cs, reg) 582 struct zs_chanstate *cs; 583 u_int reg; 584 { 585 struct zshan *zc = (void *)cs->cs_reg_csr; 586 unsigned val; 587 588 zc->zc_csr = reg << 8; 589 tc_wmb(); 590 DELAY(5); 591 val = (zc->zc_csr >> 8) & 0xff; 592 /* tc_mb(); */ 593 DELAY(5); 594 return (val); 595 } 596 597 void 598 zs_write_reg(cs, reg, val) 599 struct zs_chanstate *cs; 600 u_int reg, val; 601 { 602 struct zshan *zc = (void *)cs->cs_reg_csr; 603 604 zc->zc_csr = reg << 8; 605 tc_wmb(); 606 DELAY(5); 607 zc->zc_csr = val << 8; 608 tc_wmb(); 609 DELAY(5); 610 } 611 612 u_int 613 zs_read_csr(cs) 614 struct zs_chanstate *cs; 615 { 616 struct zshan *zc = (void *)cs->cs_reg_csr; 617 unsigned val; 618 619 val = (zc->zc_csr >> 8) & 0xff; 620 /* tc_mb(); */ 621 DELAY(5); 622 return (val); 623 } 624 625 void 626 zs_write_csr(cs, val) 627 struct zs_chanstate *cs; 628 u_int val; 629 { 630 struct zshan *zc = (void *)cs->cs_reg_csr; 631 632 zc->zc_csr = val << 8; 633 tc_wmb(); 634 DELAY(5); 635 } 636 637 u_int 638 zs_read_data(cs) 639 struct zs_chanstate *cs; 640 { 641 struct zshan *zc = (void *)cs->cs_reg_csr; 642 unsigned val; 643 644 val = (zc->zc_data) >> 8 & 0xff; 645 /* tc_mb(); */ 646 DELAY(5); 647 return (val); 648 } 649 650 void 651 zs_write_data(cs, val) 652 struct zs_chanstate *cs; 653 u_int val; 654 { 655 struct zshan *zc = (void *)cs->cs_reg_csr; 656 657 zc->zc_data = val << 8; 658 tc_wmb(); 659 DELAY(5); 660 } 661 662 /**************************************************************** 663 * Console support functions 664 ****************************************************************/ 665 666 /* 667 * Handle user request to enter kernel debugger. 668 */ 669 void 670 zs_abort(cs) 671 struct zs_chanstate *cs; 672 { 673 int rr0; 674 675 /* Wait for end of break. */ 676 /* XXX - Limit the wait? */ 677 do { 678 rr0 = zs_read_csr(cs); 679 } while (rr0 & ZSRR0_BREAK); 680 681 #if defined(KGDB) 682 zskgdb(cs); 683 #elif defined(DDB) 684 Debugger(); 685 #else 686 printf("zs_abort: ignoring break on console\n"); 687 #endif 688 } 689 690 /* 691 * Polled input char. 692 */ 693 int 694 zs_getc(cs) 695 struct zs_chanstate *cs; 696 { 697 int s, c, rr0; 698 699 s = splhigh(); 700 /* Wait for a character to arrive. */ 701 do { 702 rr0 = zs_read_csr(cs); 703 } while ((rr0 & ZSRR0_RX_READY) == 0); 704 705 c = zs_read_data(cs); 706 splx(s); 707 708 /* 709 * This is used by the kd driver to read scan codes, 710 * so don't translate '\r' ==> '\n' here... 711 */ 712 return (c); 713 } 714 715 /* 716 * Polled output char. 717 */ 718 void 719 zs_putc(cs, c) 720 struct zs_chanstate *cs; 721 int c; 722 { 723 register int s, rr0; 724 725 s = splhigh(); 726 /* Wait for transmitter to become ready. */ 727 do { 728 rr0 = zs_read_csr(cs); 729 } while ((rr0 & ZSRR0_TX_READY) == 0); 730 731 zs_write_data(cs, c); 732 733 /* Wait for the character to be transmitted. */ 734 do { 735 rr0 = zs_read_csr(cs); 736 } while ((rr0 & ZSRR0_TX_READY) == 0); 737 splx(s); 738 } 739 740 /*****************************************************************/ 741 742 /* 743 * zs_ioasic_cninit -- 744 * Initialize the serial channel for either a keyboard or 745 * a serial console. 746 */ 747 void 748 zs_ioasic_cninit(ioasic_addr, zs_offset, channel) 749 tc_addr_t ioasic_addr; 750 tc_offset_t zs_offset; 751 int channel; 752 { 753 struct zs_chanstate *cs; 754 tc_addr_t zs_addr; 755 struct zshan *zc; 756 757 /* 758 * Initialize the console finder helpers. 759 */ 760 zs_ioasic_console_offset = zs_offset; 761 zs_ioasic_console_channel = channel; 762 zs_ioasic_console = 1; 763 764 /* 765 * Pointer to channel state. 766 */ 767 cs = &zs_ioasic_conschanstate_store; 768 769 /* 770 * Compute the physical address of the chip, "map" it via 771 * K0SEG, and then get the address of the actual channel. 772 */ 773 #if defined(__alpha__) || defined(alpha) 774 zs_addr = ALPHA_PHYS_TO_K0SEG(ioasic_addr + zs_offset); 775 #endif 776 #if defined(pmax) 777 zs_addr = MIPS_PHYS_TO_KSEG1(ioasic_addr + zs_offset); 778 #endif 779 zc = zs_ioasic_get_chan_addr(zs_addr, channel); 780 781 /* Setup temporary chanstate. */ 782 cs->cs_reg_csr = (void *)&zc->zc_csr; 783 784 cs->cs_channel = channel; 785 cs->cs_ops = &zsops_null; 786 cs->cs_brg_clk = PCLK / 16; 787 788 /* Initialize the pending registers. */ 789 bcopy(zs_ioasic_init_reg, cs->cs_preg, 16); 790 cs->cs_preg[5] |= (ZSWR5_DTR | ZSWR5_RTS); 791 792 /* 793 * DCD and CTS interrupts are only meaningful on 794 * SCC 0/B. 795 * 796 * XXX This is sorta gross. 797 */ 798 if (zs_offset == 0x00100000 && channel == 1) 799 (u_long)cs->cs_private = ZIP_FLAGS_DCDCTS; 800 else 801 cs->cs_private = NULL; 802 803 /* Clear the master interrupt enable. */ 804 zs_write_reg(cs, 9, 0); 805 806 /* Reset the whole SCC chip. */ 807 zs_write_reg(cs, 9, ZSWR9_HARD_RESET); 808 809 /* Copy "pending" to "current" and H/W. */ 810 zs_loadchannelregs(cs); 811 } 812 813 /* 814 * zs_ioasic_cnattach -- 815 * Initialize and attach a serial console. 816 */ 817 void 818 zs_ioasic_cnattach(ioasic_addr, zs_offset, channel) 819 tc_addr_t ioasic_addr; 820 tc_offset_t zs_offset; 821 int channel; 822 { 823 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 824 825 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 826 cs->cs_defspeed = 9600; 827 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 828 829 /* Point the console at the SCC. */ 830 cn_tab = &zs_ioasic_cons; 831 cn_tab->cn_pri = CN_REMOTE; 832 cn_tab->cn_dev = makedev(zs_major, (zs_offset == 0x100000) ? 0 : 1); 833 } 834 835 /* 836 * zs_ioasic_lk201_cnattach -- 837 * Initialize and attach a keyboard. 838 */ 839 int 840 zs_ioasic_lk201_cnattach(ioasic_addr, zs_offset, channel) 841 tc_addr_t ioasic_addr; 842 tc_offset_t zs_offset; 843 int channel; 844 { 845 #if (NZSKBD > 0) 846 struct zs_chanstate *cs = &zs_ioasic_conschanstate_store; 847 848 zs_ioasic_cninit(ioasic_addr, zs_offset, channel); 849 cs->cs_defspeed = 4800; 850 cs->cs_defcflag = (TTYDEF_CFLAG & ~(CSIZE | PARENB)) | CS8; 851 return (zskbd_cnattach(cs)); 852 #else 853 return (ENXIO); 854 #endif 855 } 856 857 int 858 zs_ioasic_isconsole(offset, channel) 859 tc_offset_t offset; 860 int channel; 861 { 862 863 if (zs_ioasic_console && 864 offset == zs_ioasic_console_offset && 865 channel == zs_ioasic_console_channel) 866 return (1); 867 868 return (0); 869 } 870 871 /* 872 * Polled console input putchar. 873 */ 874 int 875 zs_ioasic_cngetc(dev) 876 dev_t dev; 877 { 878 879 return (zs_getc(&zs_ioasic_conschanstate_store)); 880 } 881 882 /* 883 * Polled console output putchar. 884 */ 885 void 886 zs_ioasic_cnputc(dev, c) 887 dev_t dev; 888 int c; 889 { 890 891 zs_putc(&zs_ioasic_conschanstate_store, c); 892 } 893 894 /* 895 * Set polling/no polling on console. 896 */ 897 void 898 zs_ioasic_cnpollc(dev, onoff) 899 dev_t dev; 900 int onoff; 901 { 902 903 /* XXX ??? */ 904 } 905