1 /* $NetBSD: if_xi.c,v 1.56 2006/04/14 17:46:29 christos Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.56 2006/04/14 17:46:29 christos Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 #ifdef NS 94 #include <netns/ns.h> 95 #include <netns/ns_if.h> 96 #endif 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 /* 104 * Maximum number of bytes to read per interrupt. Linux recommends 105 * somewhere between 2000-22000. 106 * XXX This is currently a hard maximum. 107 */ 108 #define MAX_BYTES_INTR 12000 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 113 #include <dev/pcmcia/pcmciareg.h> 114 #include <dev/pcmcia/pcmciavar.h> 115 #include <dev/pcmcia/pcmciadevs.h> 116 117 #include <dev/pcmcia/if_xireg.h> 118 #include <dev/pcmcia/if_xivar.h> 119 120 #ifdef __GNUC__ 121 #define INLINE inline 122 #else 123 #define INLINE 124 #endif /* __GNUC__ */ 125 126 #define XIDEBUG 127 #define XIDEBUG_VALUE 0 128 129 #ifdef XIDEBUG 130 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 131 132 #define XID_CONFIG 0x01 133 #define XID_MII 0x02 134 #define XID_INTR 0x04 135 #define XID_FIFO 0x08 136 #define XID_MCAST 0x10 137 138 #ifdef XIDEBUG_VALUE 139 int xidebug = XIDEBUG_VALUE; 140 #else 141 int xidebug = 0; 142 #endif 143 #else 144 #define DPRINTF(cat, x) (void)0 145 #endif 146 147 #define STATIC 148 149 STATIC int xi_enable(struct xi_softc *); 150 STATIC void xi_disable(struct xi_softc *); 151 STATIC void xi_cycle_power(struct xi_softc *); 152 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, caddr_t); 153 STATIC void xi_full_reset(struct xi_softc *); 154 STATIC void xi_init(struct xi_softc *); 155 STATIC int xi_ioctl(struct ifnet *, u_long, caddr_t); 156 STATIC int xi_mdi_read(struct device *, int, int); 157 STATIC void xi_mdi_write(struct device *, int, int, int); 158 STATIC int xi_mediachange(struct ifnet *); 159 STATIC void xi_mediastatus(struct ifnet *, struct ifmediareq *); 160 STATIC u_int16_t xi_get(struct xi_softc *); 161 STATIC void xi_reset(struct xi_softc *); 162 STATIC void xi_set_address(struct xi_softc *); 163 STATIC void xi_start(struct ifnet *); 164 STATIC void xi_statchg(struct device *); 165 STATIC void xi_stop(struct xi_softc *); 166 STATIC void xi_watchdog(struct ifnet *); 167 168 void 169 xi_attach(sc, myea) 170 struct xi_softc *sc; 171 u_int8_t *myea; 172 { 173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 174 175 #if 0 176 /* 177 * Configuration as advised by DINGO documentation. 178 * Dingo has some extra configuration registers in the CCR space. 179 */ 180 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 181 struct pcmcia_mem_handle pcmh; 182 int ccr_window; 183 bus_size_t ccr_offset; 184 185 /* get access to the DINGO CCR space */ 186 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 187 &pcmh)) { 188 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 189 goto fail; 190 } 191 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 192 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 193 &pcmh, &ccr_offset, &ccr_window)) { 194 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 195 pcmcia_mem_free(psc->sc_pf, &pcmh); 196 goto fail; 197 } 198 199 /* enable the second function - usually modem */ 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR1, 204 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 205 bus_space_write_1(pcmh.memt, pcmh.memh, 206 ccr_offset + PCMCIA_CCR_DCOR2, 0); 207 bus_space_write_1(pcmh.memt, pcmh.memh, 208 ccr_offset + PCMCIA_CCR_DCOR3, 0); 209 bus_space_write_1(pcmh.memt, pcmh.memh, 210 ccr_offset + PCMCIA_CCR_DCOR4, 0); 211 212 /* We don't need them anymore and can free them (I think). */ 213 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 214 pcmcia_mem_free(psc->sc_pf, &pcmh); 215 } 216 #endif 217 218 /* Reset and initialize the card. */ 219 xi_full_reset(sc); 220 221 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, ether_sprintf(myea)); 222 223 ifp = &sc->sc_ethercom.ec_if; 224 /* Initialize the ifnet structure. */ 225 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 226 ifp->if_softc = sc; 227 ifp->if_start = xi_start; 228 ifp->if_ioctl = xi_ioctl; 229 ifp->if_watchdog = xi_watchdog; 230 ifp->if_flags = 231 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 232 IFQ_SET_READY(&ifp->if_snd); 233 234 /* 802.1q capability */ 235 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 236 237 /* Attach the interface. */ 238 if_attach(ifp); 239 ether_ifattach(ifp, myea); 240 241 /* 242 * Initialize our media structures and probe the MII. 243 */ 244 sc->sc_mii.mii_ifp = ifp; 245 sc->sc_mii.mii_readreg = xi_mdi_read; 246 sc->sc_mii.mii_writereg = xi_mdi_write; 247 sc->sc_mii.mii_statchg = xi_statchg; 248 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 249 xi_mediastatus); 250 DPRINTF(XID_MII | XID_CONFIG, 251 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 252 253 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 254 MII_OFFSET_ANY, 0); 255 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 256 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 257 NULL); 258 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 259 260 #if NRND > 0 261 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET, 0); 262 #endif 263 } 264 265 int 266 xi_detach(self, flags) 267 struct device *self; 268 int flags; 269 { 270 struct xi_softc *sc = (void *)self; 271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 272 273 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 274 275 xi_disable(sc); 276 277 #if NRND > 0 278 rnd_detach_source(&sc->sc_rnd_source); 279 #endif 280 281 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 282 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 283 ether_ifdetach(ifp); 284 if_detach(ifp); 285 286 return 0; 287 } 288 289 int 290 xi_activate(self, act) 291 struct device *self; 292 enum devact act; 293 { 294 struct xi_softc *sc = (void *)self; 295 int s, rv = 0; 296 297 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 298 299 s = splnet(); 300 switch (act) { 301 case DVACT_ACTIVATE: 302 rv = EOPNOTSUPP; 303 break; 304 305 case DVACT_DEACTIVATE: 306 if_deactivate(&sc->sc_ethercom.ec_if); 307 break; 308 } 309 splx(s); 310 return (rv); 311 } 312 313 int 314 xi_intr(arg) 315 void *arg; 316 { 317 struct xi_softc *sc = arg; 318 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 319 u_int8_t esr, rsr, isr, rx_status; 320 u_int16_t tx_status, recvcount = 0, tempint; 321 322 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 323 324 if (sc->sc_enabled == 0 || 325 !device_is_active(&sc->sc_dev)) 326 return (0); 327 328 ifp->if_timer = 0; /* turn watchdog timer off */ 329 330 PAGE(sc, 0); 331 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 332 /* Disable interrupt (Linux does it). */ 333 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 334 } 335 336 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 337 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 338 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 339 340 /* Check to see if card has been ejected. */ 341 if (isr == 0xff) { 342 #ifdef DIAGNOSTIC 343 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 344 #endif 345 goto end; 346 } 347 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 348 349 PAGE(sc, 0x40); 350 rx_status = 351 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 352 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 353 tx_status = 354 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 355 tx_status |= 356 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 357 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 358 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 359 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 360 tx_status)); 361 362 PAGE(sc, 0); 363 while (esr & FULL_PKT_RCV) { 364 if (!(rsr & RSR_RX_OK)) 365 break; 366 367 /* Compare bytes read this interrupt to hard maximum. */ 368 if (recvcount > MAX_BYTES_INTR) { 369 DPRINTF(XID_INTR, 370 ("xi: too many bytes this interrupt\n")); 371 ifp->if_iqdrops++; 372 /* Drop packet. */ 373 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 374 DO_SKIP_RX_PKT); 375 } 376 tempint = xi_get(sc); /* XXX doesn't check the error! */ 377 recvcount += tempint; 378 ifp->if_ibytes += tempint; 379 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 380 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 381 } 382 383 /* Packet too long? */ 384 if (rsr & RSR_TOO_LONG) { 385 ifp->if_ierrors++; 386 DPRINTF(XID_INTR, ("xi: packet too long\n")); 387 } 388 389 /* CRC error? */ 390 if (rsr & RSR_CRCERR) { 391 ifp->if_ierrors++; 392 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 393 } 394 395 /* Alignment error? */ 396 if (rsr & RSR_ALIGNERR) { 397 ifp->if_ierrors++; 398 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 399 } 400 401 /* Check for rx overrun. */ 402 if (rx_status & RX_OVERRUN) { 403 ifp->if_ierrors++; 404 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 405 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 406 } 407 408 /* Try to start more packets transmitting. */ 409 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 410 xi_start(ifp); 411 412 /* Detected excessive collisions? */ 413 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 414 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 415 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 416 ifp->if_oerrors++; 417 } 418 419 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 420 ifp->if_oerrors++; 421 422 /* have handled the interrupt */ 423 #if NRND > 0 424 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 425 #endif 426 427 end: 428 /* Reenable interrupts. */ 429 PAGE(sc, 0); 430 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 431 432 return (1); 433 } 434 435 /* 436 * Pull a packet from the card into an mbuf chain. 437 */ 438 STATIC u_int16_t 439 xi_get(sc) 440 struct xi_softc *sc; 441 { 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 struct mbuf *top, **mp, *m; 444 u_int16_t pktlen, len, recvcount = 0; 445 u_int8_t *data; 446 447 DPRINTF(XID_CONFIG, ("xi_get()\n")); 448 449 PAGE(sc, 0); 450 pktlen = 451 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 452 453 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 454 455 if (pktlen == 0) { 456 /* 457 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 458 * when MPE is set. It is not known why. 459 */ 460 return (0); 461 } 462 463 /* XXX should this be incremented now ? */ 464 recvcount += pktlen; 465 466 MGETHDR(m, M_DONTWAIT, MT_DATA); 467 if (m == NULL) 468 return (recvcount); 469 m->m_pkthdr.rcvif = ifp; 470 m->m_pkthdr.len = pktlen; 471 len = MHLEN; 472 top = NULL; 473 mp = ⊤ 474 475 while (pktlen > 0) { 476 if (top) { 477 MGET(m, M_DONTWAIT, MT_DATA); 478 if (m == NULL) { 479 m_freem(top); 480 return (recvcount); 481 } 482 len = MLEN; 483 } 484 if (pktlen >= MINCLSIZE) { 485 MCLGET(m, M_DONTWAIT); 486 if (!(m->m_flags & M_EXT)) { 487 m_freem(m); 488 m_freem(top); 489 return (recvcount); 490 } 491 len = MCLBYTES; 492 } 493 if (top == NULL) { 494 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 495 sizeof(struct ether_header)) - 496 sizeof(struct ether_header); 497 len -= newdata - m->m_data; 498 m->m_data = newdata; 499 } 500 len = min(pktlen, len); 501 data = mtod(m, u_int8_t *); 502 if (len > 1) { 503 len &= ~1; 504 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 505 (u_int16_t *)data, len>>1); 506 } else 507 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 508 m->m_len = len; 509 pktlen -= len; 510 *mp = m; 511 mp = &m->m_next; 512 } 513 514 /* Skip Rx packet. */ 515 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 516 517 if (top == NULL) 518 return recvcount; 519 520 /* Trim the CRC off the end of the packet. */ 521 m_adj(top, -ETHER_CRC_LEN); 522 523 ifp->if_ipackets++; 524 525 #if NBPFILTER > 0 526 if (ifp->if_bpf) 527 bpf_mtap(ifp->if_bpf, top); 528 #endif 529 530 (*ifp->if_input)(ifp, top); 531 return (recvcount); 532 } 533 534 /* 535 * Serial management for the MII. 536 * The DELAY's below stem from the fact that the maximum frequency 537 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 538 * go much faster than that. 539 */ 540 541 /* Let the MII serial management be idle for one period. */ 542 static INLINE void xi_mdi_idle(struct xi_softc *); 543 static INLINE void 544 xi_mdi_idle(sc) 545 struct xi_softc *sc; 546 { 547 bus_space_tag_t bst = sc->sc_bst; 548 bus_space_handle_t bsh = sc->sc_bsh; 549 550 /* Drive MDC low... */ 551 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 552 DELAY(1); 553 554 /* and high again. */ 555 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 556 DELAY(1); 557 } 558 559 /* Pulse out one bit of data. */ 560 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 561 static INLINE void 562 xi_mdi_pulse(sc, data) 563 struct xi_softc *sc; 564 int data; 565 { 566 bus_space_tag_t bst = sc->sc_bst; 567 bus_space_handle_t bsh = sc->sc_bsh; 568 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 569 570 /* First latch the data bit MDIO with clock bit MDC low...*/ 571 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 572 DELAY(1); 573 574 /* then raise the clock again, preserving the data bit. */ 575 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 576 DELAY(1); 577 } 578 579 /* Probe one bit of data. */ 580 static INLINE int xi_mdi_probe(struct xi_softc *sc); 581 static INLINE int 582 xi_mdi_probe(sc) 583 struct xi_softc *sc; 584 { 585 bus_space_tag_t bst = sc->sc_bst; 586 bus_space_handle_t bsh = sc->sc_bsh; 587 u_int8_t x; 588 589 /* Pull clock bit MDCK low... */ 590 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 591 DELAY(1); 592 593 /* Read data and drive clock high again. */ 594 x = bus_space_read_1(bst, bsh, GP2); 595 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 596 DELAY(1); 597 598 return (x & MDIO); 599 } 600 601 /* Pulse out a sequence of data bits. */ 602 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 603 static INLINE void 604 xi_mdi_pulse_bits(sc, data, len) 605 struct xi_softc *sc; 606 u_int32_t data; 607 int len; 608 { 609 u_int32_t mask; 610 611 for (mask = 1 << (len - 1); mask; mask >>= 1) 612 xi_mdi_pulse(sc, data & mask); 613 } 614 615 /* Read a PHY register. */ 616 STATIC int 617 xi_mdi_read(self, phy, reg) 618 struct device *self; 619 int phy; 620 int reg; 621 { 622 struct xi_softc *sc = (struct xi_softc *)self; 623 int i; 624 u_int32_t mask; 625 u_int32_t data = 0; 626 627 PAGE(sc, 2); 628 for (i = 0; i < 32; i++) /* Synchronize. */ 629 xi_mdi_pulse(sc, 1); 630 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 631 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 632 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 633 xi_mdi_idle(sc); /* Turn around. */ 634 xi_mdi_probe(sc); /* Drop initial zero bit. */ 635 636 for (mask = 1 << 15; mask; mask >>= 1) { 637 if (xi_mdi_probe(sc)) 638 data |= mask; 639 } 640 xi_mdi_idle(sc); 641 642 DPRINTF(XID_MII, 643 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 644 645 return (data); 646 } 647 648 /* Write a PHY register. */ 649 STATIC void 650 xi_mdi_write(self, phy, reg, value) 651 struct device *self; 652 int phy; 653 int reg; 654 int value; 655 { 656 struct xi_softc *sc = (struct xi_softc *)self; 657 int i; 658 659 PAGE(sc, 2); 660 for (i = 0; i < 32; i++) /* Synchronize. */ 661 xi_mdi_pulse(sc, 1); 662 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 663 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 664 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 665 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 666 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 667 xi_mdi_idle(sc); /* Idle away. */ 668 669 DPRINTF(XID_MII, 670 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 671 } 672 673 STATIC void 674 xi_statchg(self) 675 struct device *self; 676 { 677 /* XXX Update ifp->if_baudrate */ 678 } 679 680 /* 681 * Change media according to request. 682 */ 683 STATIC int 684 xi_mediachange(ifp) 685 struct ifnet *ifp; 686 { 687 int s; 688 689 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 690 691 if (ifp->if_flags & IFF_UP) { 692 s = splnet(); 693 xi_init(ifp->if_softc); 694 splx(s); 695 } 696 return (0); 697 } 698 699 /* 700 * Notify the world which media we're using. 701 */ 702 STATIC void 703 xi_mediastatus(ifp, ifmr) 704 struct ifnet *ifp; 705 struct ifmediareq *ifmr; 706 { 707 struct xi_softc *sc = ifp->if_softc; 708 709 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 710 711 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 712 mii_pollstat(&sc->sc_mii); 713 ifmr->ifm_status = sc->sc_mii.mii_media_status; 714 ifmr->ifm_active = sc->sc_mii.mii_media_active; 715 } 716 } 717 718 STATIC void 719 xi_reset(sc) 720 struct xi_softc *sc; 721 { 722 int s; 723 724 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 725 726 s = splnet(); 727 xi_stop(sc); 728 xi_init(sc); 729 splx(s); 730 } 731 732 STATIC void 733 xi_watchdog(ifp) 734 struct ifnet *ifp; 735 { 736 struct xi_softc *sc = ifp->if_softc; 737 738 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 739 ++ifp->if_oerrors; 740 741 xi_reset(sc); 742 } 743 744 STATIC void 745 xi_stop(sc) 746 register struct xi_softc *sc; 747 { 748 bus_space_tag_t bst = sc->sc_bst; 749 bus_space_handle_t bsh = sc->sc_bsh; 750 751 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 752 753 PAGE(sc, 0x40); 754 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 755 756 /* Disable interrupts. */ 757 PAGE(sc, 0); 758 bus_space_write_1(bst, bsh, CR, 0); 759 760 PAGE(sc, 1); 761 bus_space_write_1(bst, bsh, IMR0, 0); 762 763 /* Cancel watchdog timer. */ 764 sc->sc_ethercom.ec_if.if_timer = 0; 765 } 766 767 STATIC int 768 xi_enable(sc) 769 struct xi_softc *sc; 770 { 771 int error; 772 773 if (!sc->sc_enabled) { 774 error = (*sc->sc_enable)(sc); 775 if (error) 776 return (error); 777 sc->sc_enabled = 1; 778 xi_full_reset(sc); 779 } 780 return (0); 781 } 782 783 STATIC void 784 xi_disable(sc) 785 struct xi_softc *sc; 786 { 787 788 if (sc->sc_enabled) { 789 sc->sc_enabled = 0; 790 (*sc->sc_disable)(sc); 791 } 792 } 793 794 STATIC void 795 xi_init(sc) 796 struct xi_softc *sc; 797 { 798 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 799 bus_space_tag_t bst = sc->sc_bst; 800 bus_space_handle_t bsh = sc->sc_bsh; 801 802 DPRINTF(XID_CONFIG, ("xi_init()\n")); 803 804 /* Setup the ethernet interrupt mask. */ 805 PAGE(sc, 1); 806 bus_space_write_1(bst, bsh, IMR0, 807 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 808 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 809 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 810 /* XXX What is this? Not for Dingo at least. */ 811 /* Unmask TX underrun detection */ 812 bus_space_write_1(bst, bsh, IMR1, 1); 813 } 814 815 /* Enable interrupts. */ 816 PAGE(sc, 0); 817 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 818 819 xi_set_address(sc); 820 821 PAGE(sc, 0x40); 822 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 823 824 PAGE(sc, 0); 825 826 /* Set current media. */ 827 mii_mediachg(&sc->sc_mii); 828 829 ifp->if_flags |= IFF_RUNNING; 830 ifp->if_flags &= ~IFF_OACTIVE; 831 832 xi_start(ifp); 833 } 834 835 /* 836 * Start outputting on the interface. 837 * Always called as splnet(). 838 */ 839 STATIC void 840 xi_start(ifp) 841 struct ifnet *ifp; 842 { 843 struct xi_softc *sc = ifp->if_softc; 844 bus_space_tag_t bst = sc->sc_bst; 845 bus_space_handle_t bsh = sc->sc_bsh; 846 unsigned int s, len, pad = 0; 847 struct mbuf *m0, *m; 848 u_int16_t space; 849 850 DPRINTF(XID_CONFIG, ("xi_start()\n")); 851 852 /* Don't transmit if interface is busy or not running. */ 853 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 854 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 855 return; 856 } 857 858 /* Peek at the next packet. */ 859 IFQ_POLL(&ifp->if_snd, m0); 860 if (m0 == 0) 861 return; 862 863 /* We need to use m->m_pkthdr.len, so require the header. */ 864 if (!(m0->m_flags & M_PKTHDR)) 865 panic("xi_start: no header mbuf"); 866 867 len = m0->m_pkthdr.len; 868 869 #if 1 870 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 871 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 872 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 873 #else 874 pad = 0; 875 #endif 876 877 PAGE(sc, 0); 878 879 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 880 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 881 if (len + pad + 2 > space) { 882 DPRINTF(XID_FIFO, 883 ("xi: not enough space in output FIFO (%d > %d)\n", 884 len + pad + 2, space)); 885 return; 886 } 887 888 IFQ_DEQUEUE(&ifp->if_snd, m0); 889 890 #if NBPFILTER > 0 891 if (ifp->if_bpf) 892 bpf_mtap(ifp->if_bpf, m0); 893 #endif 894 895 /* 896 * Do the output at splhigh() so that an interrupt from another device 897 * won't cause a FIFO underrun. 898 */ 899 s = splhigh(); 900 901 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 902 for (m = m0; m; ) { 903 if (m->m_len > 1) 904 bus_space_write_multi_2(bst, bsh, EDP, 905 mtod(m, u_int16_t *), m->m_len>>1); 906 if (m->m_len & 1) { 907 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 908 bus_space_write_1(bst, bsh, EDP, 909 *(mtod(m, u_int8_t *) + m->m_len - 1)); 910 } 911 MFREE(m, m0); 912 m = m0; 913 } 914 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 915 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 916 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 917 else { 918 for (; pad > 1; pad -= 2) 919 bus_space_write_2(bst, bsh, EDP, 0); 920 if (pad == 1) 921 bus_space_write_1(bst, bsh, EDP, 0); 922 } 923 924 splx(s); 925 926 ifp->if_timer = 5; 927 ++ifp->if_opackets; 928 } 929 930 STATIC int 931 xi_ether_ioctl(ifp, cmd, data) 932 struct ifnet *ifp; 933 u_long cmd; 934 caddr_t data; 935 { 936 struct ifaddr *ifa = (struct ifaddr *)data; 937 struct xi_softc *sc = ifp->if_softc; 938 int error; 939 940 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 941 942 switch (cmd) { 943 case SIOCSIFADDR: 944 if ((error = xi_enable(sc)) != 0) 945 break; 946 947 ifp->if_flags |= IFF_UP; 948 949 switch (ifa->ifa_addr->sa_family) { 950 #ifdef INET 951 case AF_INET: 952 xi_init(sc); 953 arp_ifinit(ifp, ifa); 954 break; 955 #endif /* INET */ 956 957 #ifdef NS 958 case AF_NS: 959 { 960 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 961 962 if (ns_nullhost(*ina)) 963 ina->x_host = *(union ns_host *) 964 LLADDR(ifp->if_sadl); 965 else 966 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 967 ifp->if_addrlen); 968 /* Set new address. */ 969 xi_init(sc); 970 break; 971 } 972 #endif /* NS */ 973 974 default: 975 xi_init(sc); 976 break; 977 } 978 break; 979 980 default: 981 return (EINVAL); 982 } 983 984 return (0); 985 } 986 987 STATIC int 988 xi_ioctl(ifp, cmd, data) 989 struct ifnet *ifp; 990 u_long cmd; 991 caddr_t data; 992 { 993 struct xi_softc *sc = ifp->if_softc; 994 struct ifreq *ifr = (struct ifreq *)data; 995 int s, error = 0; 996 997 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 998 999 s = splnet(); 1000 1001 switch (cmd) { 1002 case SIOCSIFADDR: 1003 error = xi_ether_ioctl(ifp, cmd, data); 1004 break; 1005 1006 case SIOCSIFFLAGS: 1007 if ((ifp->if_flags & IFF_UP) == 0 && 1008 (ifp->if_flags & IFF_RUNNING) != 0) { 1009 /* 1010 * If interface is marked down and it is running, 1011 * stop it. 1012 */ 1013 xi_stop(sc); 1014 ifp->if_flags &= ~IFF_RUNNING; 1015 xi_disable(sc); 1016 } else if ((ifp->if_flags & IFF_UP) != 0 && 1017 (ifp->if_flags & IFF_RUNNING) == 0) { 1018 /* 1019 * If interface is marked up and it is stopped, 1020 * start it. 1021 */ 1022 if ((error = xi_enable(sc)) != 0) 1023 break; 1024 xi_init(sc); 1025 } else if ((ifp->if_flags & IFF_UP) != 0) { 1026 /* 1027 * Reset the interface to pick up changes in any 1028 * other flags that affect hardware registers. 1029 */ 1030 xi_set_address(sc); 1031 } 1032 break; 1033 1034 case SIOCADDMULTI: 1035 case SIOCDELMULTI: 1036 if (sc->sc_enabled == 0) { 1037 error = EIO; 1038 break; 1039 } 1040 1041 error = (cmd == SIOCADDMULTI) ? 1042 ether_addmulti(ifr, &sc->sc_ethercom) : 1043 ether_delmulti(ifr, &sc->sc_ethercom); 1044 if (error == ENETRESET) { 1045 /* 1046 * Multicast list has changed; set the hardware 1047 * filter accordingly. 1048 */ 1049 if (ifp->if_flags & IFF_RUNNING) 1050 xi_set_address(sc); 1051 error = 0; 1052 } 1053 break; 1054 1055 case SIOCSIFMEDIA: 1056 case SIOCGIFMEDIA: 1057 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1058 break; 1059 1060 default: 1061 error = EINVAL; 1062 break; 1063 } 1064 1065 splx(s); 1066 return (error); 1067 } 1068 1069 STATIC void 1070 xi_set_address(sc) 1071 struct xi_softc *sc; 1072 { 1073 bus_space_tag_t bst = sc->sc_bst; 1074 bus_space_handle_t bsh = sc->sc_bsh; 1075 struct ethercom *ether = &sc->sc_ethercom; 1076 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1077 struct ether_multistep step; 1078 struct ether_multi *enm; 1079 int page, num; 1080 int i; 1081 u_int8_t x; 1082 u_int8_t *enaddr; 1083 u_int8_t indaddr[64]; 1084 1085 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1086 1087 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 1088 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1089 for (i = 0; i < 6; i++) 1090 indaddr[i] = enaddr[5 - i]; 1091 else 1092 for (i = 0; i < 6; i++) 1093 indaddr[i] = enaddr[i]; 1094 num = 1; 1095 1096 if (ether->ec_multicnt > 9) { 1097 ifp->if_flags |= IFF_ALLMULTI; 1098 goto done; 1099 } 1100 1101 ETHER_FIRST_MULTI(step, ether, enm); 1102 for (; enm; num++) { 1103 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1104 sizeof(enm->enm_addrlo)) != 0) { 1105 /* 1106 * The multicast address is really a range; 1107 * it's easier just to accept all multicasts. 1108 * XXX should we be setting IFF_ALLMULTI here? 1109 */ 1110 ifp->if_flags |= IFF_ALLMULTI; 1111 goto done; 1112 } 1113 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1114 for (i = 0; i < 6; i++) 1115 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1116 else 1117 for (i = 0; i < 6; i++) 1118 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1119 ETHER_NEXT_MULTI(step, enm); 1120 } 1121 ifp->if_flags &= ~IFF_ALLMULTI; 1122 1123 done: 1124 if (num < 10) 1125 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1126 1127 for (page = 0; page < 8; page++) { 1128 #ifdef XIDEBUG 1129 if (xidebug & XID_MCAST) { 1130 printf("page %d before:", page); 1131 for (i = 0; i < 8; i++) 1132 printf(" %02x", indaddr[page * 8 + i]); 1133 printf("\n"); 1134 } 1135 #endif 1136 1137 PAGE(sc, 0x50 + page); 1138 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1139 page == 7 ? 4 : 8); 1140 /* 1141 * XXX 1142 * Without this delay, the address registers on my CE2 get 1143 * trashed the first and I have to cycle it. I have no idea 1144 * why. - mycroft, 2004/08/09 1145 */ 1146 DELAY(50); 1147 1148 #ifdef XIDEBUG 1149 if (xidebug & XID_MCAST) { 1150 bus_space_read_region_1(bst, bsh, IA, 1151 &indaddr[page * 8], page == 7 ? 4 : 8); 1152 printf("page %d after: ", page); 1153 for (i = 0; i < 8; i++) 1154 printf(" %02x", indaddr[page * 8 + i]); 1155 printf("\n"); 1156 } 1157 #endif 1158 } 1159 1160 PAGE(sc, 0x42); 1161 x = SWC1_IND_ADDR; 1162 if (ifp->if_flags & IFF_PROMISC) 1163 x |= SWC1_PROMISC; 1164 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1165 x |= SWC1_MCAST_PROM; 1166 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1167 x |= SWC1_AUTO_MEDIA; 1168 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1169 } 1170 1171 STATIC void 1172 xi_cycle_power(sc) 1173 struct xi_softc *sc; 1174 { 1175 bus_space_tag_t bst = sc->sc_bst; 1176 bus_space_handle_t bsh = sc->sc_bsh; 1177 1178 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1179 1180 PAGE(sc, 4); 1181 DELAY(1); 1182 bus_space_write_1(bst, bsh, GP1, 0); 1183 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1184 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1185 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1186 else 1187 /* XXX What is bit 2 (aka AIC)? */ 1188 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1189 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1190 } 1191 1192 STATIC void 1193 xi_full_reset(sc) 1194 struct xi_softc *sc; 1195 { 1196 bus_space_tag_t bst = sc->sc_bst; 1197 bus_space_handle_t bsh = sc->sc_bsh; 1198 u_int8_t x; 1199 1200 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1201 1202 /* Do an as extensive reset as possible on all functions. */ 1203 xi_cycle_power(sc); 1204 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1205 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1206 bus_space_write_1(bst, bsh, CR, 0); 1207 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1208 PAGE(sc, 4); 1209 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1210 /* 1211 * Drive GP1 low to power up ML6692 and GP2 high to power up 1212 * the 10MHz chip. XXX What chip is that? The phy? 1213 */ 1214 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1215 } 1216 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1217 1218 /* Get revision information. XXX Symbolic constants. */ 1219 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1220 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1221 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1222 1223 /* Media selection. XXX Maybe manual overriding too? */ 1224 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1225 /* 1226 * XXX I have no idea what this really does, it is from the 1227 * Linux driver. 1228 */ 1229 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1230 } 1231 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1232 1233 /* 1234 * Disable source insertion. 1235 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1236 */ 1237 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1238 PAGE(sc, 0x42); 1239 bus_space_write_1(bst, bsh, SWC0, 0x20); 1240 } 1241 1242 /* Set the local memory dividing line. */ 1243 if (sc->sc_rev != 1) { 1244 PAGE(sc, 2); 1245 /* XXX Symbolic constant preferrable. */ 1246 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1247 } 1248 1249 /* 1250 * Apparently the receive byte pointer can be bad after a reset, so 1251 * we hardwire it correctly. 1252 */ 1253 PAGE(sc, 0); 1254 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1255 1256 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1257 PAGE(sc, 0x40); 1258 bus_space_write_1(bst, bsh, RX0MSK, 1259 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1260 bus_space_write_1(bst, bsh, TX0MSK, 1261 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1262 SQE | TX_ABORT | TX_OK); 1263 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1264 /* XXX From Linux, dunno what 0xb0 means. */ 1265 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1266 bus_space_write_1(bst, bsh, RXST0, 0); 1267 bus_space_write_1(bst, bsh, TXST0, 0); 1268 bus_space_write_1(bst, bsh, TXST1, 0); 1269 1270 PAGE(sc, 2); 1271 1272 /* Enable MII function if available. */ 1273 x = 0; 1274 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1275 x |= SELECT_MII; 1276 bus_space_write_1(bst, bsh, MSR, x); 1277 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1278 1279 /* Configure the LED registers. */ 1280 /* XXX This is not good for 10base2. */ 1281 bus_space_write_1(bst, bsh, LED, 1282 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1283 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1284 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1285 1286 /* 1287 * The Linux driver says this: 1288 * We should switch back to page 0 to avoid a bug in revision 0 1289 * where regs with offset below 8 can't be read after an access 1290 * to the MAC registers. 1291 */ 1292 PAGE(sc, 0); 1293 } 1294