1 /* $NetBSD: if_xi.c,v 1.96 2022/09/25 21:53:54 thorpej Exp $ */
2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */
3
4 /*
5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 */
21
22 /*
23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas
24 * All rights reserved.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 * 1. Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer.
31 * 2. Redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution.
34 * 3. All advertising materials mentioning features or use of this software
35 * must display the following acknowledgement:
36 * This product includes software developed by Niklas Hallqvist,
37 * Brandon Creighton and Job de Haas.
38 * 4. The name of the author may not be used to endorse or promote products
39 * derived from this software without specific prior written permission
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 */
52
53 /*
54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters.
55 */
56
57 #include <sys/cdefs.h>
58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.96 2022/09/25 21:53:54 thorpej Exp $");
59
60 #include "opt_inet.h"
61
62 #include <sys/param.h>
63 #include <sys/systm.h>
64 #include <sys/device.h>
65 #include <sys/ioctl.h>
66 #include <sys/mbuf.h>
67 #include <sys/socket.h>
68 #include <sys/kernel.h>
69 #include <sys/proc.h>
70
71 #include <net/if.h>
72 #include <net/if_dl.h>
73 #include <net/if_media.h>
74 #include <net/if_types.h>
75 #include <net/if_ether.h>
76 #include <net/bpf.h>
77
78 #ifdef INET
79 #include <netinet/in.h>
80 #include <netinet/in_systm.h>
81 #include <netinet/in_var.h>
82 #include <netinet/ip.h>
83 #include <netinet/if_inarp.h>
84 #endif
85
86 /*
87 * Maximum number of bytes to read per interrupt. Linux recommends
88 * somewhere between 2000-22000.
89 * XXX This is currently a hard maximum.
90 */
91 #define MAX_BYTES_INTR 12000
92
93 #include <dev/mii/mii.h>
94 #include <dev/mii/miivar.h>
95
96 #include <dev/pcmcia/pcmciareg.h>
97 #include <dev/pcmcia/pcmciavar.h>
98 #include <dev/pcmcia/pcmciadevs.h>
99
100 #include <dev/pcmcia/if_xireg.h>
101 #include <dev/pcmcia/if_xivar.h>
102
103 #ifdef __GNUC__
104 #define INLINE inline
105 #else
106 #define INLINE
107 #endif /* __GNUC__ */
108
109 #define XIDEBUG
110 #define XIDEBUG_VALUE 0
111
112 #ifdef XIDEBUG
113 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x
114
115 #define XID_CONFIG 0x01
116 #define XID_MII 0x02
117 #define XID_INTR 0x04
118 #define XID_FIFO 0x08
119 #define XID_MCAST 0x10
120
121 #ifdef XIDEBUG_VALUE
122 int xidebug = XIDEBUG_VALUE;
123 #else
124 int xidebug = 0;
125 #endif
126 #else
127 #define DPRINTF(cat, x) (void)0
128 #endif
129
130 #define STATIC static
131
132 STATIC int xi_enable(struct xi_softc *);
133 STATIC void xi_disable(struct xi_softc *);
134 STATIC void xi_cycle_power(struct xi_softc *);
135 STATIC int xi_ether_ioctl(struct ifnet *, u_long, void *);
136 STATIC void xi_full_reset(struct xi_softc *);
137 STATIC void xi_init(struct xi_softc *);
138 STATIC int xi_ioctl(struct ifnet *, u_long, void *);
139 STATIC int xi_mdi_read(device_t, int, int, uint16_t *);
140 STATIC int xi_mdi_write(device_t, int, int, uint16_t);
141 STATIC int xi_mediachange(struct ifnet *);
142 STATIC uint16_t xi_get(struct xi_softc *);
143 STATIC void xi_reset(struct xi_softc *);
144 STATIC void xi_set_address(struct xi_softc *);
145 STATIC void xi_start(struct ifnet *);
146 STATIC void xi_statchg(struct ifnet *);
147 STATIC void xi_stop(struct xi_softc *);
148 STATIC void xi_watchdog(struct ifnet *);
149
150 void
xi_attach(struct xi_softc * sc,uint8_t * myea)151 xi_attach(struct xi_softc *sc, uint8_t *myea)
152 {
153 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
154 struct mii_data * const mii = &sc->sc_mii;
155 #ifdef XIDEBUG
156 uint16_t bmsr;
157 #endif
158 #if 0
159 /*
160 * Configuration as advised by DINGO documentation.
161 * Dingo has some extra configuration registers in the CCR space.
162 */
163 if (sc->sc_chipset >= XI_CHIPSET_DINGO) {
164 struct pcmcia_mem_handle pcmh;
165 int ccr_window;
166 bus_size_t ccr_offset;
167
168 /* get access to the DINGO CCR space */
169 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO,
170 &pcmh)) {
171 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n"));
172 goto fail;
173 }
174 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR,
175 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO,
176 &pcmh, &ccr_offset, &ccr_window)) {
177 DPRINTF(XID_CONFIG, ("xi: bad mem map\n"));
178 pcmcia_mem_free(psc->sc_pf, &pcmh);
179 goto fail;
180 }
181
182 /* enable the second function - usually modem */
183 bus_space_write_1(pcmh.memt, pcmh.memh,
184 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT);
185 bus_space_write_1(pcmh.memt, pcmh.memh,
186 ccr_offset + PCMCIA_CCR_DCOR1,
187 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6);
188 bus_space_write_1(pcmh.memt, pcmh.memh,
189 ccr_offset + PCMCIA_CCR_DCOR2, 0);
190 bus_space_write_1(pcmh.memt, pcmh.memh,
191 ccr_offset + PCMCIA_CCR_DCOR3, 0);
192 bus_space_write_1(pcmh.memt, pcmh.memh,
193 ccr_offset + PCMCIA_CCR_DCOR4, 0);
194
195 /* We don't need them anymore and can free them (I think). */
196 pcmcia_mem_unmap(psc->sc_pf, ccr_window);
197 pcmcia_mem_free(psc->sc_pf, &pcmh);
198 }
199 #endif
200
201 /* Reset and initialize the card. */
202 xi_full_reset(sc);
203
204 device_printf(sc->sc_dev, "MAC address %s\n", ether_sprintf(myea));
205
206 ifp = &sc->sc_ethercom.ec_if;
207 /* Initialize the ifnet structure. */
208 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ);
209 ifp->if_softc = sc;
210 ifp->if_start = xi_start;
211 ifp->if_ioctl = xi_ioctl;
212 ifp->if_watchdog = xi_watchdog;
213 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
214 IFQ_SET_READY(&ifp->if_snd);
215
216 /* 802.1q capability */
217 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU;
218
219 /* Attach the interface. */
220 if_attach(ifp);
221 if_deferred_start_init(ifp, NULL);
222 ether_ifattach(ifp, myea);
223
224 /*
225 * Initialize our media structures and probe the MII.
226 */
227 mii->mii_ifp = ifp;
228 mii->mii_readreg = xi_mdi_read;
229 mii->mii_writereg = xi_mdi_write;
230 mii->mii_statchg = xi_statchg;
231 sc->sc_ethercom.ec_mii = mii;
232 ifmedia_init(&mii->mii_media, 0, xi_mediachange, ether_mediastatus);
233 #ifdef XIDEBUG
234 xi_mdi_read(sc->sc_dev, 0, 1, &bmsr);
235 DPRINTF(XID_MII | XID_CONFIG, ("xi: bmsr %x\n", bmsr));
236 #endif
237
238 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY,
239 MII_OFFSET_ANY, 0);
240 if (LIST_FIRST(&mii->mii_phys) == NULL)
241 ifmedia_add(&mii->mii_media, IFM_ETHER | IFM_AUTO, 0, NULL);
242 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO);
243
244 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev),
245 RND_TYPE_NET, RND_FLAG_DEFAULT);
246 }
247
248 int
xi_detach(device_t self,int flags)249 xi_detach(device_t self, int flags)
250 {
251 struct xi_softc *sc = device_private(self);
252 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
253
254 DPRINTF(XID_CONFIG, ("xi_detach()\n"));
255
256 xi_disable(sc);
257
258 rnd_detach_source(&sc->sc_rnd_source);
259
260 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY);
261 ether_ifdetach(ifp);
262 if_detach(ifp);
263 ifmedia_fini(&sc->sc_mii.mii_media);
264
265 return 0;
266 }
267
268 int
xi_intr(void * arg)269 xi_intr(void *arg)
270 {
271 struct xi_softc *sc = arg;
272 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
273 uint8_t esr, rsr, isr, rx_status;
274 uint16_t tx_status, recvcount = 0, tempint;
275
276 DPRINTF(XID_CONFIG, ("xi_intr()\n"));
277
278 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev))
279 return (0);
280
281 ifp->if_timer = 0; /* turn watchdog timer off */
282
283 PAGE(sc, 0);
284 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
285 /* Disable interrupt (Linux does it). */
286 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0);
287 }
288
289 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
290 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0);
291 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
292
293 /* Check to see if card has been ejected. */
294 if (isr == 0xff) {
295 #ifdef DIAGNOSTIC
296 printf("%s: interrupt for dead card\n",
297 device_xname(sc->sc_dev));
298 #endif
299 goto end;
300 }
301 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr));
302
303 PAGE(sc, 0x40);
304 rx_status =
305 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0);
306 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff);
307 tx_status =
308 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0);
309 tx_status |=
310 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8;
311 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0);
312 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0);
313 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status,
314 tx_status));
315
316 PAGE(sc, 0);
317 while (esr & FULL_PKT_RCV) {
318 if (!(rsr & RSR_RX_OK))
319 break;
320
321 /* Compare bytes read this interrupt to hard maximum. */
322 if (recvcount > MAX_BYTES_INTR) {
323 DPRINTF(XID_INTR,
324 ("xi: too many bytes this interrupt\n"));
325 if_statinc(ifp, if_iqdrops);
326 /* Drop packet. */
327 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0,
328 DO_SKIP_RX_PKT);
329 }
330 tempint = xi_get(sc); /* XXX doesn't check the error! */
331 recvcount += tempint;
332 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR);
333 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR);
334 }
335
336 /* Packet too long? */
337 if (rsr & RSR_TOO_LONG) {
338 if_statinc(ifp, if_ierrors);
339 DPRINTF(XID_INTR, ("xi: packet too long\n"));
340 }
341
342 /* CRC error? */
343 if (rsr & RSR_CRCERR) {
344 if_statinc(ifp, if_ierrors);
345 DPRINTF(XID_INTR, ("xi: CRC error detected\n"));
346 }
347
348 /* Alignment error? */
349 if (rsr & RSR_ALIGNERR) {
350 if_statinc(ifp, if_ierrors);
351 DPRINTF(XID_INTR, ("xi: alignment error detected\n"));
352 }
353
354 /* Check for rx overrun. */
355 if (rx_status & RX_OVERRUN) {
356 if_statinc(ifp, if_ierrors);
357 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN);
358 DPRINTF(XID_INTR, ("xi: overrun cleared\n"));
359 }
360
361 /* Try to start more packets transmitting. */
362 if_schedule_deferred_start(ifp);
363
364 /* Detected excessive collisions? */
365 if ((tx_status & EXCESSIVE_COLL) /* XXX && ifp->if_opackets > 0 */) {
366 DPRINTF(XID_INTR, ("xi: excessive collisions\n"));
367 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX);
368 if_statinc(ifp, if_oerrors);
369 }
370
371 if ((tx_status & TX_ABORT) /* && XXX ifp->if_opackets > 0 */)
372 if_statinc(ifp, if_oerrors);
373
374 /* have handled the interrupt */
375 rnd_add_uint32(&sc->sc_rnd_source, tx_status);
376
377 end:
378 /* Reenable interrupts. */
379 PAGE(sc, 0);
380 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT);
381
382 return (1);
383 }
384
385 /*
386 * Pull a packet from the card into an mbuf chain.
387 */
388 STATIC uint16_t
xi_get(struct xi_softc * sc)389 xi_get(struct xi_softc *sc)
390 {
391 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
392 struct mbuf *top, **mp, *m;
393 uint16_t pktlen, len, recvcount = 0;
394 uint8_t *data;
395
396 DPRINTF(XID_CONFIG, ("xi_get()\n"));
397
398 PAGE(sc, 0);
399 pktlen =
400 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK;
401
402 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen));
403
404 if (pktlen == 0) {
405 /*
406 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only
407 * when MPE is set. It is not known why.
408 */
409 return (0);
410 }
411
412 /* XXX should this be incremented now ? */
413 recvcount += pktlen;
414
415 MGETHDR(m, M_DONTWAIT, MT_DATA);
416 if (m == NULL)
417 return (recvcount);
418 m_set_rcvif(m, ifp);
419 m->m_pkthdr.len = pktlen;
420 len = MHLEN;
421 top = NULL;
422 mp = ⊤
423
424 while (pktlen > 0) {
425 if (top) {
426 MGET(m, M_DONTWAIT, MT_DATA);
427 if (m == NULL) {
428 m_freem(top);
429 return (recvcount);
430 }
431 len = MLEN;
432 }
433 if (pktlen >= MINCLSIZE) {
434 MCLGET(m, M_DONTWAIT);
435 if (!(m->m_flags & M_EXT)) {
436 m_freem(m);
437 m_freem(top);
438 return (recvcount);
439 }
440 len = MCLBYTES;
441 }
442 if (top == NULL) {
443 char *newdata = (char *)ALIGN(m->m_data +
444 sizeof(struct ether_header)) -
445 sizeof(struct ether_header);
446 len -= newdata - m->m_data;
447 m->m_data = newdata;
448 }
449 len = uimin(pktlen, len);
450 data = mtod(m, uint8_t *);
451 if (len > 1) {
452 len &= ~1;
453 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP,
454 (uint16_t *)data, len>>1);
455 } else
456 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP);
457 m->m_len = len;
458 pktlen -= len;
459 *mp = m;
460 mp = &m->m_next;
461 }
462
463 /* Skip Rx packet. */
464 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT);
465
466 if (top == NULL)
467 return recvcount;
468
469 /* Trim the CRC off the end of the packet. */
470 m_adj(top, -ETHER_CRC_LEN);
471
472 if_percpuq_enqueue(ifp->if_percpuq, top);
473 return (recvcount);
474 }
475
476 /*
477 * Serial management for the MII.
478 * The DELAY's below stem from the fact that the maximum frequency
479 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily
480 * go much faster than that.
481 */
482
483 /* Let the MII serial management be idle for one period. */
484 static INLINE void xi_mdi_idle(struct xi_softc *);
485 static INLINE void
xi_mdi_idle(struct xi_softc * sc)486 xi_mdi_idle(struct xi_softc *sc)
487 {
488 bus_space_tag_t bst = sc->sc_bst;
489 bus_space_handle_t bsh = sc->sc_bsh;
490
491 /* Drive MDC low... */
492 bus_space_write_1(bst, bsh, GP2, MDC_LOW);
493 DELAY(1);
494
495 /* and high again. */
496 bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
497 DELAY(1);
498 }
499
500 /* Pulse out one bit of data. */
501 static INLINE void xi_mdi_pulse(struct xi_softc *, int);
502 static INLINE void
xi_mdi_pulse(struct xi_softc * sc,int data)503 xi_mdi_pulse(struct xi_softc *sc, int data)
504 {
505 bus_space_tag_t bst = sc->sc_bst;
506 bus_space_handle_t bsh = sc->sc_bsh;
507 uint8_t bit = data ? MDIO_HIGH : MDIO_LOW;
508
509 /* First latch the data bit MDIO with clock bit MDC low...*/
510 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW);
511 DELAY(1);
512
513 /* then raise the clock again, preserving the data bit. */
514 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH);
515 DELAY(1);
516 }
517
518 /* Probe one bit of data. */
519 static INLINE int xi_mdi_probe(struct xi_softc *sc);
520 static INLINE int
xi_mdi_probe(struct xi_softc * sc)521 xi_mdi_probe(struct xi_softc *sc)
522 {
523 bus_space_tag_t bst = sc->sc_bst;
524 bus_space_handle_t bsh = sc->sc_bsh;
525 uint8_t x;
526
527 /* Pull clock bit MDCK low... */
528 bus_space_write_1(bst, bsh, GP2, MDC_LOW);
529 DELAY(1);
530
531 /* Read data and drive clock high again. */
532 x = bus_space_read_1(bst, bsh, GP2);
533 bus_space_write_1(bst, bsh, GP2, MDC_HIGH);
534 DELAY(1);
535
536 return (x & MDIO);
537 }
538
539 /* Pulse out a sequence of data bits. */
540 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, uint32_t, int);
541 static INLINE void
xi_mdi_pulse_bits(struct xi_softc * sc,uint32_t data,int len)542 xi_mdi_pulse_bits(struct xi_softc *sc, uint32_t data, int len)
543 {
544 uint32_t mask;
545
546 for (mask = 1 << (len - 1); mask; mask >>= 1)
547 xi_mdi_pulse(sc, data & mask);
548 }
549
550 /* Read a PHY register. */
551 STATIC int
xi_mdi_read(device_t self,int phy,int reg,uint16_t * val)552 xi_mdi_read(device_t self, int phy, int reg, uint16_t *val)
553 {
554 struct xi_softc *sc = device_private(self);
555 int i;
556 uint32_t mask;
557 uint16_t data = 0;
558
559 PAGE(sc, 2);
560 for (i = 0; i < 32; i++) /* Synchronize. */
561 xi_mdi_pulse(sc, 1);
562 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */
563 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
564 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
565 xi_mdi_idle(sc); /* Turn around. */
566 xi_mdi_probe(sc); /* Drop initial zero bit. */
567
568 for (mask = 1 << 15; mask; mask >>= 1) {
569 if (xi_mdi_probe(sc))
570 data |= mask;
571 }
572 xi_mdi_idle(sc);
573
574 DPRINTF(XID_MII,
575 ("xi_mdi_read: phy %d reg %d -> %04hx\n", phy, reg, data));
576
577 *val = data;
578 return 0;
579 }
580
581 /* Write a PHY register. */
582 STATIC int
xi_mdi_write(device_t self,int phy,int reg,uint16_t val)583 xi_mdi_write(device_t self, int phy, int reg, uint16_t val)
584 {
585 struct xi_softc *sc = device_private(self);
586 int i;
587
588 PAGE(sc, 2);
589 for (i = 0; i < 32; i++) /* Synchronize. */
590 xi_mdi_pulse(sc, 1);
591 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */
592 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */
593 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */
594 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */
595 xi_mdi_pulse_bits(sc, val, 16); /* Write the data */
596 xi_mdi_idle(sc); /* Idle away. */
597
598 DPRINTF(XID_MII,
599 ("xi_mdi_write: phy %d reg %d val %04hx\n", phy, reg, val));
600
601 return 0;
602 }
603
604 STATIC void
xi_statchg(struct ifnet * ifp)605 xi_statchg(struct ifnet *ifp)
606 {
607 /* XXX Update ifp->if_baudrate */
608 }
609
610 /*
611 * Change media according to request.
612 */
613 STATIC int
xi_mediachange(struct ifnet * ifp)614 xi_mediachange(struct ifnet *ifp)
615 {
616 int s;
617
618 DPRINTF(XID_CONFIG, ("xi_mediachange()\n"));
619
620 if (ifp->if_flags & IFF_UP) {
621 s = splnet();
622 xi_init(ifp->if_softc);
623 splx(s);
624 }
625 return (0);
626 }
627
628 STATIC void
xi_reset(struct xi_softc * sc)629 xi_reset(struct xi_softc *sc)
630 {
631 int s;
632
633 DPRINTF(XID_CONFIG, ("xi_reset()\n"));
634
635 s = splnet();
636 xi_stop(sc);
637 xi_init(sc);
638 splx(s);
639 }
640
641 STATIC void
xi_watchdog(struct ifnet * ifp)642 xi_watchdog(struct ifnet *ifp)
643 {
644 struct xi_softc *sc = ifp->if_softc;
645
646 printf("%s: device timeout\n", device_xname(sc->sc_dev));
647 if_statinc(ifp, if_oerrors);
648
649 xi_reset(sc);
650 }
651
652 STATIC void
xi_stop(register struct xi_softc * sc)653 xi_stop(register struct xi_softc *sc)
654 {
655 bus_space_tag_t bst = sc->sc_bst;
656 bus_space_handle_t bsh = sc->sc_bsh;
657
658 DPRINTF(XID_CONFIG, ("xi_stop()\n"));
659
660 PAGE(sc, 0x40);
661 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX);
662
663 /* Disable interrupts. */
664 PAGE(sc, 0);
665 bus_space_write_1(bst, bsh, CR, 0);
666
667 PAGE(sc, 1);
668 bus_space_write_1(bst, bsh, IMR0, 0);
669
670 /* Cancel watchdog timer. */
671 sc->sc_ethercom.ec_if.if_timer = 0;
672 }
673
674 STATIC int
xi_enable(struct xi_softc * sc)675 xi_enable(struct xi_softc *sc)
676 {
677 int error;
678
679 if (!sc->sc_enabled) {
680 error = (*sc->sc_enable)(sc);
681 if (error)
682 return (error);
683 sc->sc_enabled = 1;
684 xi_full_reset(sc);
685 }
686 return (0);
687 }
688
689 STATIC void
xi_disable(struct xi_softc * sc)690 xi_disable(struct xi_softc *sc)
691 {
692
693 if (sc->sc_enabled) {
694 sc->sc_enabled = 0;
695 (*sc->sc_disable)(sc);
696 }
697 }
698
699 STATIC void
xi_init(struct xi_softc * sc)700 xi_init(struct xi_softc *sc)
701 {
702 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
703 bus_space_tag_t bst = sc->sc_bst;
704 bus_space_handle_t bsh = sc->sc_bsh;
705
706 DPRINTF(XID_CONFIG, ("xi_init()\n"));
707
708 /* Setup the ethernet interrupt mask. */
709 PAGE(sc, 1);
710 bus_space_write_1(bst, bsh, IMR0,
711 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */
712 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT);
713 if (sc->sc_chipset < XI_CHIPSET_DINGO) {
714 /* XXX What is this? Not for Dingo at least. */
715 /* Unmask TX underrun detection */
716 bus_space_write_1(bst, bsh, IMR1, 1);
717 }
718
719 /* Enable interrupts. */
720 PAGE(sc, 0);
721 bus_space_write_1(bst, bsh, CR, ENABLE_INT);
722
723 xi_set_address(sc);
724
725 PAGE(sc, 0x40);
726 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE);
727
728 PAGE(sc, 0);
729
730 /* Set current media. */
731 mii_mediachg(&sc->sc_mii);
732
733 ifp->if_flags |= IFF_RUNNING;
734 ifp->if_flags &= ~IFF_OACTIVE;
735
736 xi_start(ifp);
737 }
738
739 /*
740 * Start outputting on the interface.
741 * Always called as splnet().
742 */
743 STATIC void
xi_start(struct ifnet * ifp)744 xi_start(struct ifnet *ifp)
745 {
746 struct xi_softc *sc = ifp->if_softc;
747 bus_space_tag_t bst = sc->sc_bst;
748 bus_space_handle_t bsh = sc->sc_bsh;
749 unsigned int s, len, pad = 0;
750 struct mbuf *m0, *m;
751 uint16_t space;
752
753 DPRINTF(XID_CONFIG, ("xi_start()\n"));
754
755 /* Don't transmit if interface is busy or not running. */
756 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) {
757 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n"));
758 return;
759 }
760
761 /* Peek at the next packet. */
762 IFQ_POLL(&ifp->if_snd, m0);
763 if (m0 == 0)
764 return;
765
766 /* We need to use m->m_pkthdr.len, so require the header. */
767 if (!(m0->m_flags & M_PKTHDR))
768 panic("xi_start: no header mbuf");
769
770 len = m0->m_pkthdr.len;
771
772 #if 1
773 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */
774 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN)
775 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len;
776 #else
777 pad = 0;
778 #endif
779
780 PAGE(sc, 0);
781
782 bus_space_write_2(bst, bsh, TRS, (uint16_t)len + pad + 2);
783 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff;
784 if (len + pad + 2 > space) {
785 DPRINTF(XID_FIFO,
786 ("xi: not enough space in output FIFO (%d > %d)\n",
787 len + pad + 2, space));
788 return;
789 }
790
791 IFQ_DEQUEUE(&ifp->if_snd, m0);
792
793 bpf_mtap(ifp, m0, BPF_D_OUT);
794
795 /*
796 * Do the output at splhigh() so that an interrupt from another device
797 * won't cause a FIFO underrun.
798 */
799 s = splhigh();
800
801 bus_space_write_2(bst, bsh, EDP, (uint16_t)len + pad);
802 for (m = m0; m; ) {
803 if (m->m_len > 1)
804 bus_space_write_multi_2(bst, bsh, EDP,
805 mtod(m, uint16_t *), m->m_len>>1);
806 if (m->m_len & 1) {
807 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n"));
808 bus_space_write_1(bst, bsh, EDP,
809 *(mtod(m, uint8_t *) + m->m_len - 1));
810 }
811 m = m0 = m_free(m);
812 }
813 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4));
814 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
815 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT);
816 else {
817 for (; pad > 1; pad -= 2)
818 bus_space_write_2(bst, bsh, EDP, 0);
819 if (pad == 1)
820 bus_space_write_1(bst, bsh, EDP, 0);
821 }
822
823 splx(s);
824
825 ifp->if_timer = 5;
826 if_statinc(ifp, if_opackets);
827 }
828
829 STATIC int
xi_ether_ioctl(struct ifnet * ifp,u_long cmd,void * data)830 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data)
831 {
832 struct ifaddr *ifa = (struct ifaddr *)data;
833 struct xi_softc *sc = ifp->if_softc;
834 int error;
835
836 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n"));
837
838 switch (cmd) {
839 case SIOCINITIFADDR:
840 if ((error = xi_enable(sc)) != 0)
841 break;
842
843 ifp->if_flags |= IFF_UP;
844
845 xi_init(sc);
846 switch (ifa->ifa_addr->sa_family) {
847 #ifdef INET
848 case AF_INET:
849 arp_ifinit(ifp, ifa);
850 break;
851 #endif /* INET */
852
853
854 default:
855 break;
856 }
857 break;
858
859 default:
860 return (EINVAL);
861 }
862
863 return (0);
864 }
865
866 STATIC int
xi_ioctl(struct ifnet * ifp,u_long cmd,void * data)867 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data)
868 {
869 struct xi_softc *sc = ifp->if_softc;
870 int s, error = 0;
871
872 DPRINTF(XID_CONFIG, ("xi_ioctl()\n"));
873
874 s = splnet();
875
876 switch (cmd) {
877 case SIOCINITIFADDR:
878 error = xi_ether_ioctl(ifp, cmd, data);
879 break;
880
881 case SIOCSIFFLAGS:
882 if ((error = ifioctl_common(ifp, cmd, data)) != 0)
883 break;
884 /* XXX re-use ether_ioctl() */
885 switch (ifp->if_flags & (IFF_UP | IFF_RUNNING)) {
886 case IFF_RUNNING:
887 /*
888 * If interface is marked down and it is running,
889 * stop it.
890 */
891 xi_stop(sc);
892 ifp->if_flags &= ~IFF_RUNNING;
893 xi_disable(sc);
894 break;
895 case IFF_UP:
896 /*
897 * If interface is marked up and it is stopped,
898 * start it.
899 */
900 if ((error = xi_enable(sc)) != 0)
901 break;
902 xi_init(sc);
903 break;
904 case IFF_UP | IFF_RUNNING:
905 /*
906 * Reset the interface to pick up changes in any
907 * other flags that affect hardware registers.
908 */
909 xi_set_address(sc);
910 break;
911 case 0:
912 break;
913 }
914 break;
915
916 case SIOCADDMULTI:
917 case SIOCDELMULTI:
918 if (sc->sc_enabled == 0) {
919 error = EIO;
920 break;
921 }
922 /*FALLTHROUGH*/
923 default:
924 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) {
925 /*
926 * Multicast list has changed; set the hardware
927 * filter accordingly.
928 */
929 if (ifp->if_flags & IFF_RUNNING)
930 xi_set_address(sc);
931 error = 0;
932 }
933 break;
934 }
935
936 splx(s);
937 return (error);
938 }
939
940 STATIC void
xi_set_address(struct xi_softc * sc)941 xi_set_address(struct xi_softc *sc)
942 {
943 bus_space_tag_t bst = sc->sc_bst;
944 bus_space_handle_t bsh = sc->sc_bsh;
945 struct ethercom *ec = &sc->sc_ethercom;
946 struct ifnet *ifp = &sc->sc_ethercom.ec_if;
947 struct ether_multistep step;
948 struct ether_multi *enm;
949 int page, num;
950 int i;
951 uint8_t x;
952 const uint8_t *enaddr;
953 uint8_t indaddr[64];
954
955 DPRINTF(XID_CONFIG, ("xi_set_address()\n"));
956
957 enaddr = (const uint8_t *)CLLADDR(ifp->if_sadl);
958 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
959 for (i = 0; i < 6; i++)
960 indaddr[i] = enaddr[5 - i];
961 else
962 for (i = 0; i < 6; i++)
963 indaddr[i] = enaddr[i];
964 num = 1;
965
966 ETHER_LOCK(ec);
967 if (ec->ec_multicnt > 9) {
968 ifp->if_flags |= IFF_ALLMULTI;
969 goto done;
970 }
971
972 ETHER_FIRST_MULTI(step, ec, enm);
973 for (; enm; num++) {
974 if (memcmp(enm->enm_addrlo, enm->enm_addrhi,
975 sizeof(enm->enm_addrlo)) != 0) {
976 /*
977 * The multicast address is really a range;
978 * it's easier just to accept all multicasts.
979 * XXX should we be setting IFF_ALLMULTI here?
980 */
981 ifp->if_flags |= IFF_ALLMULTI;
982 goto done;
983 }
984 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
985 for (i = 0; i < 6; i++)
986 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i];
987 else
988 for (i = 0; i < 6; i++)
989 indaddr[num * 6 + i] = enm->enm_addrlo[i];
990 ETHER_NEXT_MULTI(step, enm);
991 }
992 ifp->if_flags &= ~IFF_ALLMULTI;
993
994 done:
995 ETHER_UNLOCK(ec);
996 if (num < 10)
997 memset(&indaddr[num * 6], 0xff, 6 * (10 - num));
998
999 for (page = 0; page < 8; page++) {
1000 #ifdef XIDEBUG
1001 if (xidebug & XID_MCAST) {
1002 printf("page %d before:", page);
1003 for (i = 0; i < 8; i++)
1004 printf(" %02x", indaddr[page * 8 + i]);
1005 printf("\n");
1006 }
1007 #endif
1008
1009 PAGE(sc, 0x50 + page);
1010 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8],
1011 page == 7 ? 4 : 8);
1012 /*
1013 * XXX
1014 * Without this delay, the address registers on my CE2 get
1015 * trashed the first and I have to cycle it. I have no idea
1016 * why. - mycroft, 2004/08/09
1017 */
1018 DELAY(50);
1019
1020 #ifdef XIDEBUG
1021 if (xidebug & XID_MCAST) {
1022 bus_space_read_region_1(bst, bsh, IA,
1023 &indaddr[page * 8], page == 7 ? 4 : 8);
1024 printf("page %d after: ", page);
1025 for (i = 0; i < 8; i++)
1026 printf(" %02x", indaddr[page * 8 + i]);
1027 printf("\n");
1028 }
1029 #endif
1030 }
1031
1032 PAGE(sc, 0x42);
1033 x = SWC1_IND_ADDR;
1034 if (ifp->if_flags & IFF_PROMISC)
1035 x |= SWC1_PROMISC;
1036 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))
1037 x |= SWC1_MCAST_PROM;
1038 if (!LIST_FIRST(&sc->sc_mii.mii_phys))
1039 x |= SWC1_AUTO_MEDIA;
1040 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x);
1041 }
1042
1043 STATIC void
xi_cycle_power(struct xi_softc * sc)1044 xi_cycle_power(struct xi_softc *sc)
1045 {
1046 bus_space_tag_t bst = sc->sc_bst;
1047 bus_space_handle_t bsh = sc->sc_bsh;
1048
1049 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n"));
1050
1051 PAGE(sc, 4);
1052 DELAY(1);
1053 bus_space_write_1(bst, bsh, GP1, 0);
1054 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000);
1055 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK)
1056 bus_space_write_1(bst, bsh, GP1, POWER_UP);
1057 else
1058 /* XXX What is bit 2 (aka AIC)? */
1059 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4);
1060 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000);
1061 }
1062
1063 STATIC void
xi_full_reset(struct xi_softc * sc)1064 xi_full_reset(struct xi_softc *sc)
1065 {
1066 bus_space_tag_t bst = sc->sc_bst;
1067 bus_space_handle_t bsh = sc->sc_bsh;
1068 uint8_t x;
1069
1070 DPRINTF(XID_CONFIG, ("xi_full_reset()\n"));
1071
1072 /* Do an as extensive reset as possible on all functions. */
1073 xi_cycle_power(sc);
1074 bus_space_write_1(bst, bsh, CR, SOFT_RESET);
1075 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000);
1076 bus_space_write_1(bst, bsh, CR, 0);
1077 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000);
1078 PAGE(sc, 4);
1079 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) {
1080 /*
1081 * Drive GP1 low to power up ML6692 and GP2 high to power up
1082 * the 10MHz chip. XXX What chip is that? The phy?
1083 */
1084 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR);
1085 }
1086 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000);
1087
1088 /* Get revision information. XXX Symbolic constants. */
1089 sc->sc_rev = bus_space_read_1(bst, bsh, BV) &
1090 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4;
1091 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev));
1092
1093 /* Media selection. XXX Maybe manual overriding too? */
1094 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) {
1095 /*
1096 * XXX I have no idea what this really does, it is from the
1097 * Linux driver.
1098 */
1099 bus_space_write_1(bst, bsh, GP0, GP1_OUT);
1100 }
1101 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000);
1102
1103 /*
1104 * Disable source insertion.
1105 * XXX Dingo does not have this bit, but Linux does it unconditionally.
1106 */
1107 if (sc->sc_chipset < XI_CHIPSET_DINGO) {
1108 PAGE(sc, 0x42);
1109 bus_space_write_1(bst, bsh, SWC0, 0x20);
1110 }
1111
1112 /* Set the local memory dividing line. */
1113 if (sc->sc_rev != 1) {
1114 PAGE(sc, 2);
1115 /* XXX Symbolic constant preferable. */
1116 bus_space_write_2(bst, bsh, RBS0, 0x2000);
1117 }
1118
1119 /*
1120 * Apparently the receive byte pointer can be bad after a reset, so
1121 * we hardwire it correctly.
1122 */
1123 PAGE(sc, 0);
1124 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET);
1125
1126 /* Setup ethernet MAC registers. XXX Symbolic constants. */
1127 PAGE(sc, 0x40);
1128 bus_space_write_1(bst, bsh, RX0MSK,
1129 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK);
1130 bus_space_write_1(bst, bsh, TX0MSK,
1131 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION |
1132 SQE | TX_ABORT | TX_OK);
1133 if (sc->sc_chipset < XI_CHIPSET_DINGO)
1134 /* XXX From Linux, dunno what 0xb0 means. */
1135 bus_space_write_1(bst, bsh, TX1MSK, 0xb0);
1136 bus_space_write_1(bst, bsh, RXST0, 0);
1137 bus_space_write_1(bst, bsh, TXST0, 0);
1138 bus_space_write_1(bst, bsh, TXST1, 0);
1139
1140 PAGE(sc, 2);
1141
1142 /* Enable MII function if available. */
1143 x = 0;
1144 if (LIST_FIRST(&sc->sc_mii.mii_phys))
1145 x |= SELECT_MII;
1146 bus_space_write_1(bst, bsh, MSR, x);
1147 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000);
1148
1149 /* Configure the LED registers. */
1150 /* XXX This is not good for 10base2. */
1151 bus_space_write_1(bst, bsh, LED,
1152 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT));
1153 if (sc->sc_chipset >= XI_CHIPSET_DINGO)
1154 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT);
1155
1156 /*
1157 * The Linux driver says this:
1158 * We should switch back to page 0 to avoid a bug in revision 0
1159 * where regs with offset below 8 can't be read after an access
1160 * to the MAC registers.
1161 */
1162 PAGE(sc, 0);
1163 }
1164