1 /* $NetBSD: if_xi.c,v 1.48 2004/08/12 19:42:03 mycroft Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.48 2004/08/12 19:42:03 mycroft Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 #ifdef NS 94 #include <netns/ns.h> 95 #include <netns/ns_if.h> 96 #endif 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 /* 104 * Maximum number of bytes to read per interrupt. Linux recommends 105 * somewhere between 2000-22000. 106 * XXX This is currently a hard maximum. 107 */ 108 #define MAX_BYTES_INTR 12000 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 113 #include <dev/pcmcia/pcmciareg.h> 114 #include <dev/pcmcia/pcmciavar.h> 115 #include <dev/pcmcia/pcmciadevs.h> 116 117 #include <dev/pcmcia/if_xireg.h> 118 #include <dev/pcmcia/if_xivar.h> 119 120 #ifdef __GNUC__ 121 #define INLINE __inline 122 #else 123 #define INLINE 124 #endif /* __GNUC__ */ 125 126 #define XIDEBUG 127 #define XIDEBUG_VALUE 0 128 129 #ifdef XIDEBUG 130 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 131 132 #define XID_CONFIG 0x01 133 #define XID_MII 0x02 134 #define XID_INTR 0x04 135 #define XID_FIFO 0x08 136 #define XID_MCAST 0x10 137 138 #ifdef XIDEBUG_VALUE 139 int xidebug = XIDEBUG_VALUE; 140 #else 141 int xidebug = 0; 142 #endif 143 #else 144 #define DPRINTF(cat, x) (void)0 145 #endif 146 147 #define STATIC 148 149 STATIC int xi_enable __P((struct xi_softc *)); 150 STATIC void xi_disable __P((struct xi_softc *)); 151 STATIC void xi_cycle_power __P((struct xi_softc *)); 152 STATIC int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 153 STATIC void xi_full_reset __P((struct xi_softc *)); 154 STATIC void xi_init __P((struct xi_softc *)); 155 STATIC int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 156 STATIC int xi_mdi_read __P((struct device *, int, int)); 157 STATIC void xi_mdi_write __P((struct device *, int, int, int)); 158 STATIC int xi_mediachange __P((struct ifnet *)); 159 STATIC void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 160 STATIC u_int16_t xi_get __P((struct xi_softc *)); 161 STATIC void xi_reset __P((struct xi_softc *)); 162 STATIC void xi_set_address __P((struct xi_softc *)); 163 STATIC void xi_start __P((struct ifnet *)); 164 STATIC void xi_statchg __P((struct device *)); 165 STATIC void xi_stop __P((struct xi_softc *)); 166 STATIC void xi_watchdog __P((struct ifnet *)); 167 168 void 169 xi_attach(sc, myea) 170 struct xi_softc *sc; 171 u_int8_t *myea; 172 { 173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 174 175 #if 0 176 /* 177 * Configuration as advised by DINGO documentation. 178 * Dingo has some extra configuration registers in the CCR space. 179 */ 180 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 181 struct pcmcia_mem_handle pcmh; 182 int ccr_window; 183 bus_size_t ccr_offset; 184 185 /* get access to the DINGO CCR space */ 186 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 187 &pcmh)) { 188 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 189 goto fail; 190 } 191 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 192 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 193 &pcmh, &ccr_offset, &ccr_window)) { 194 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 195 pcmcia_mem_free(psc->sc_pf, &pcmh); 196 goto fail; 197 } 198 199 /* enable the second function - usually modem */ 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR1, 204 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 205 bus_space_write_1(pcmh.memt, pcmh.memh, 206 ccr_offset + PCMCIA_CCR_DCOR2, 0); 207 bus_space_write_1(pcmh.memt, pcmh.memh, 208 ccr_offset + PCMCIA_CCR_DCOR3, 0); 209 bus_space_write_1(pcmh.memt, pcmh.memh, 210 ccr_offset + PCMCIA_CCR_DCOR4, 0); 211 212 /* We don't need them anymore and can free them (I think). */ 213 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 214 pcmcia_mem_free(psc->sc_pf, &pcmh); 215 } 216 #endif 217 218 /* Reset and initialize the card. */ 219 xi_full_reset(sc); 220 221 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, ether_sprintf(myea)); 222 223 ifp = &sc->sc_ethercom.ec_if; 224 /* Initialize the ifnet structure. */ 225 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 226 ifp->if_softc = sc; 227 ifp->if_start = xi_start; 228 ifp->if_ioctl = xi_ioctl; 229 ifp->if_watchdog = xi_watchdog; 230 ifp->if_flags = 231 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 232 IFQ_SET_READY(&ifp->if_snd); 233 234 /* 802.1q capability */ 235 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 236 237 /* Attach the interface. */ 238 if_attach(ifp); 239 ether_ifattach(ifp, myea); 240 241 /* 242 * Initialize our media structures and probe the MII. 243 */ 244 sc->sc_mii.mii_ifp = ifp; 245 sc->sc_mii.mii_readreg = xi_mdi_read; 246 sc->sc_mii.mii_writereg = xi_mdi_write; 247 sc->sc_mii.mii_statchg = xi_statchg; 248 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 249 xi_mediastatus); 250 DPRINTF(XID_MII | XID_CONFIG, 251 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 252 253 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 254 MII_OFFSET_ANY, 0); 255 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 256 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 257 NULL); 258 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 259 260 #if NRND > 0 261 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET, 0); 262 #endif 263 } 264 265 int 266 xi_detach(self, flags) 267 struct device *self; 268 int flags; 269 { 270 struct xi_softc *sc = (void *)self; 271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 272 273 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 274 275 xi_disable(sc); 276 277 #if NRND > 0 278 rnd_detach_source(&sc->sc_rnd_source); 279 #endif 280 281 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 282 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 283 ether_ifdetach(ifp); 284 if_detach(ifp); 285 286 return 0; 287 } 288 289 int 290 xi_activate(self, act) 291 struct device *self; 292 enum devact act; 293 { 294 struct xi_softc *sc = (void *)self; 295 int s, rv = 0; 296 297 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 298 299 s = splnet(); 300 switch (act) { 301 case DVACT_ACTIVATE: 302 rv = EOPNOTSUPP; 303 break; 304 305 case DVACT_DEACTIVATE: 306 if_deactivate(&sc->sc_ethercom.ec_if); 307 break; 308 } 309 splx(s); 310 return (rv); 311 } 312 313 int 314 xi_intr(arg) 315 void *arg; 316 { 317 struct xi_softc *sc = arg; 318 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 319 u_int8_t esr, rsr, isr, rx_status; 320 u_int16_t tx_status, recvcount = 0, tempint; 321 322 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 323 324 if (sc->sc_enabled == 0 || 325 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 326 return (0); 327 328 ifp->if_timer = 0; /* turn watchdog timer off */ 329 330 PAGE(sc, 0); 331 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 332 /* Disable interrupt (Linux does it). */ 333 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 334 } 335 336 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 337 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 338 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 339 340 /* Check to see if card has been ejected. */ 341 if (isr == 0xff) { 342 #ifdef DIAGNOSTIC 343 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 344 #endif 345 goto end; 346 } 347 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 348 349 PAGE(sc, 0x40); 350 rx_status = 351 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 352 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 353 tx_status = 354 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 355 tx_status |= 356 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 357 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 358 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 359 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 360 tx_status)); 361 362 PAGE(sc, 0); 363 while (esr & FULL_PKT_RCV) { 364 if (!(rsr & RSR_RX_OK)) 365 break; 366 367 /* Compare bytes read this interrupt to hard maximum. */ 368 if (recvcount > MAX_BYTES_INTR) { 369 DPRINTF(XID_INTR, 370 ("xi: too many bytes this interrupt\n")); 371 ifp->if_iqdrops++; 372 /* Drop packet. */ 373 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 374 DO_SKIP_RX_PKT); 375 } 376 tempint = xi_get(sc); /* XXX doesn't check the error! */ 377 recvcount += tempint; 378 ifp->if_ibytes += tempint; 379 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 380 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 381 } 382 383 /* Packet too long? */ 384 if (rsr & RSR_TOO_LONG) { 385 ifp->if_ierrors++; 386 DPRINTF(XID_INTR, ("xi: packet too long\n")); 387 } 388 389 /* CRC error? */ 390 if (rsr & RSR_CRCERR) { 391 ifp->if_ierrors++; 392 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 393 } 394 395 /* Alignment error? */ 396 if (rsr & RSR_ALIGNERR) { 397 ifp->if_ierrors++; 398 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 399 } 400 401 /* Check for rx overrun. */ 402 if (rx_status & RX_OVERRUN) { 403 ifp->if_ierrors++; 404 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 405 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 406 } 407 408 /* Try to start more packets transmitting. */ 409 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 410 xi_start(ifp); 411 412 /* Detected excessive collisions? */ 413 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 414 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 415 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 416 ifp->if_oerrors++; 417 } 418 419 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 420 ifp->if_oerrors++; 421 422 /* have handled the interrupt */ 423 #if NRND > 0 424 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 425 #endif 426 427 end: 428 /* Reenable interrupts. */ 429 PAGE(sc, 0); 430 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 431 432 return (1); 433 } 434 435 /* 436 * Pull a packet from the card into an mbuf chain. 437 */ 438 STATIC u_int16_t 439 xi_get(sc) 440 struct xi_softc *sc; 441 { 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 struct mbuf *top, **mp, *m; 444 u_int16_t pktlen, len, recvcount = 0; 445 u_int8_t *data; 446 447 DPRINTF(XID_CONFIG, ("xi_get()\n")); 448 449 PAGE(sc, 0); 450 pktlen = 451 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 452 453 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 454 455 if (pktlen == 0) { 456 /* 457 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 458 * when MPE is set. It is not known why. 459 */ 460 return (0); 461 } 462 463 /* XXX should this be incremented now ? */ 464 recvcount += pktlen; 465 466 MGETHDR(m, M_DONTWAIT, MT_DATA); 467 if (m == 0) 468 return (recvcount); 469 m->m_pkthdr.rcvif = ifp; 470 m->m_pkthdr.len = pktlen; 471 m->m_flags |= M_HASFCS; 472 len = MHLEN; 473 top = 0; 474 mp = ⊤ 475 476 while (pktlen > 0) { 477 if (top) { 478 MGET(m, M_DONTWAIT, MT_DATA); 479 if (m == 0) { 480 m_freem(top); 481 return (recvcount); 482 } 483 len = MLEN; 484 } 485 if (pktlen >= MINCLSIZE) { 486 MCLGET(m, M_DONTWAIT); 487 if (!(m->m_flags & M_EXT)) { 488 m_freem(m); 489 m_freem(top); 490 return (recvcount); 491 } 492 len = MCLBYTES; 493 } 494 if (!top) { 495 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 496 sizeof(struct ether_header)) - 497 sizeof(struct ether_header); 498 len -= newdata - m->m_data; 499 m->m_data = newdata; 500 } 501 len = min(pktlen, len); 502 data = mtod(m, u_int8_t *); 503 if (len > 1) { 504 len &= ~1; 505 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 506 (u_int16_t *)data, len>>1); 507 } else 508 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 509 m->m_len = len; 510 pktlen -= len; 511 *mp = m; 512 mp = &m->m_next; 513 } 514 515 /* Skip Rx packet. */ 516 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 517 518 ifp->if_ipackets++; 519 520 #if NBPFILTER > 0 521 if (ifp->if_bpf) 522 bpf_mtap(ifp->if_bpf, top); 523 #endif 524 525 (*ifp->if_input)(ifp, top); 526 return (recvcount); 527 } 528 529 /* 530 * Serial management for the MII. 531 * The DELAY's below stem from the fact that the maximum frequency 532 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 533 * go much faster than that. 534 */ 535 536 /* Let the MII serial management be idle for one period. */ 537 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 538 static INLINE void 539 xi_mdi_idle(sc) 540 struct xi_softc *sc; 541 { 542 bus_space_tag_t bst = sc->sc_bst; 543 bus_space_handle_t bsh = sc->sc_bsh; 544 545 /* Drive MDC low... */ 546 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 547 DELAY(1); 548 549 /* and high again. */ 550 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 551 DELAY(1); 552 } 553 554 /* Pulse out one bit of data. */ 555 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 556 static INLINE void 557 xi_mdi_pulse(sc, data) 558 struct xi_softc *sc; 559 int data; 560 { 561 bus_space_tag_t bst = sc->sc_bst; 562 bus_space_handle_t bsh = sc->sc_bsh; 563 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 564 565 /* First latch the data bit MDIO with clock bit MDC low...*/ 566 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 567 DELAY(1); 568 569 /* then raise the clock again, preserving the data bit. */ 570 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 571 DELAY(1); 572 } 573 574 /* Probe one bit of data. */ 575 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 576 static INLINE int 577 xi_mdi_probe(sc) 578 struct xi_softc *sc; 579 { 580 bus_space_tag_t bst = sc->sc_bst; 581 bus_space_handle_t bsh = sc->sc_bsh; 582 u_int8_t x; 583 584 /* Pull clock bit MDCK low... */ 585 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 586 DELAY(1); 587 588 /* Read data and drive clock high again. */ 589 x = bus_space_read_1(bst, bsh, GP2); 590 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 591 DELAY(1); 592 593 return (x & MDIO); 594 } 595 596 /* Pulse out a sequence of data bits. */ 597 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 598 static INLINE void 599 xi_mdi_pulse_bits(sc, data, len) 600 struct xi_softc *sc; 601 u_int32_t data; 602 int len; 603 { 604 u_int32_t mask; 605 606 for (mask = 1 << (len - 1); mask; mask >>= 1) 607 xi_mdi_pulse(sc, data & mask); 608 } 609 610 /* Read a PHY register. */ 611 STATIC int 612 xi_mdi_read(self, phy, reg) 613 struct device *self; 614 int phy; 615 int reg; 616 { 617 struct xi_softc *sc = (struct xi_softc *)self; 618 int i; 619 u_int32_t mask; 620 u_int32_t data = 0; 621 622 PAGE(sc, 2); 623 for (i = 0; i < 32; i++) /* Synchronize. */ 624 xi_mdi_pulse(sc, 1); 625 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 626 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 627 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 628 xi_mdi_idle(sc); /* Turn around. */ 629 xi_mdi_probe(sc); /* Drop initial zero bit. */ 630 631 for (mask = 1 << 15; mask; mask >>= 1) { 632 if (xi_mdi_probe(sc)) 633 data |= mask; 634 } 635 xi_mdi_idle(sc); 636 637 DPRINTF(XID_MII, 638 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 639 640 return (data); 641 } 642 643 /* Write a PHY register. */ 644 STATIC void 645 xi_mdi_write(self, phy, reg, value) 646 struct device *self; 647 int phy; 648 int reg; 649 int value; 650 { 651 struct xi_softc *sc = (struct xi_softc *)self; 652 int i; 653 654 PAGE(sc, 2); 655 for (i = 0; i < 32; i++) /* Synchronize. */ 656 xi_mdi_pulse(sc, 1); 657 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 658 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 659 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 660 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 661 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 662 xi_mdi_idle(sc); /* Idle away. */ 663 664 DPRINTF(XID_MII, 665 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 666 } 667 668 STATIC void 669 xi_statchg(self) 670 struct device *self; 671 { 672 /* XXX Update ifp->if_baudrate */ 673 } 674 675 /* 676 * Change media according to request. 677 */ 678 STATIC int 679 xi_mediachange(ifp) 680 struct ifnet *ifp; 681 { 682 int s; 683 684 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 685 686 if (ifp->if_flags & IFF_UP) { 687 s = splnet(); 688 xi_init(ifp->if_softc); 689 splx(s); 690 } 691 return (0); 692 } 693 694 /* 695 * Notify the world which media we're using. 696 */ 697 STATIC void 698 xi_mediastatus(ifp, ifmr) 699 struct ifnet *ifp; 700 struct ifmediareq *ifmr; 701 { 702 struct xi_softc *sc = ifp->if_softc; 703 704 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 705 706 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 707 mii_pollstat(&sc->sc_mii); 708 ifmr->ifm_status = sc->sc_mii.mii_media_status; 709 ifmr->ifm_active = sc->sc_mii.mii_media_active; 710 } 711 } 712 713 STATIC void 714 xi_reset(sc) 715 struct xi_softc *sc; 716 { 717 int s; 718 719 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 720 721 s = splnet(); 722 xi_stop(sc); 723 xi_init(sc); 724 splx(s); 725 } 726 727 STATIC void 728 xi_watchdog(ifp) 729 struct ifnet *ifp; 730 { 731 struct xi_softc *sc = ifp->if_softc; 732 733 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 734 ++ifp->if_oerrors; 735 736 xi_reset(sc); 737 } 738 739 STATIC void 740 xi_stop(sc) 741 register struct xi_softc *sc; 742 { 743 bus_space_tag_t bst = sc->sc_bst; 744 bus_space_handle_t bsh = sc->sc_bsh; 745 746 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 747 748 PAGE(sc, 0x40); 749 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 750 751 /* Disable interrupts. */ 752 PAGE(sc, 0); 753 bus_space_write_1(bst, bsh, CR, 0); 754 755 PAGE(sc, 1); 756 bus_space_write_1(bst, bsh, IMR0, 0); 757 758 /* Cancel watchdog timer. */ 759 sc->sc_ethercom.ec_if.if_timer = 0; 760 } 761 762 STATIC int 763 xi_enable(sc) 764 struct xi_softc *sc; 765 { 766 int error; 767 768 if (!sc->sc_enabled) { 769 error = (*sc->sc_enable)(sc); 770 if (error) 771 return (error); 772 sc->sc_enabled = 1; 773 xi_full_reset(sc); 774 } 775 return (0); 776 } 777 778 STATIC void 779 xi_disable(sc) 780 struct xi_softc *sc; 781 { 782 783 if (sc->sc_enabled) { 784 sc->sc_enabled = 0; 785 (*sc->sc_disable)(sc); 786 } 787 } 788 789 STATIC void 790 xi_init(sc) 791 struct xi_softc *sc; 792 { 793 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 794 bus_space_tag_t bst = sc->sc_bst; 795 bus_space_handle_t bsh = sc->sc_bsh; 796 797 DPRINTF(XID_CONFIG, ("xi_init()\n")); 798 799 /* Setup the ethernet interrupt mask. */ 800 PAGE(sc, 1); 801 bus_space_write_1(bst, bsh, IMR0, 802 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 803 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 804 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 805 /* XXX What is this? Not for Dingo at least. */ 806 /* Unmask TX underrun detection */ 807 bus_space_write_1(bst, bsh, IMR1, 1); 808 } 809 810 /* Enable interrupts. */ 811 PAGE(sc, 0); 812 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 813 814 xi_set_address(sc); 815 816 PAGE(sc, 0x40); 817 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 818 819 PAGE(sc, 0); 820 821 /* Set current media. */ 822 mii_mediachg(&sc->sc_mii); 823 824 ifp->if_flags |= IFF_RUNNING; 825 ifp->if_flags &= ~IFF_OACTIVE; 826 827 xi_start(ifp); 828 } 829 830 /* 831 * Start outputting on the interface. 832 * Always called as splnet(). 833 */ 834 STATIC void 835 xi_start(ifp) 836 struct ifnet *ifp; 837 { 838 struct xi_softc *sc = ifp->if_softc; 839 bus_space_tag_t bst = sc->sc_bst; 840 bus_space_handle_t bsh = sc->sc_bsh; 841 unsigned int s, len, pad = 0; 842 struct mbuf *m0, *m; 843 u_int16_t space; 844 845 DPRINTF(XID_CONFIG, ("xi_start()\n")); 846 847 /* Don't transmit if interface is busy or not running. */ 848 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 849 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 850 return; 851 } 852 853 /* Peek at the next packet. */ 854 IFQ_POLL(&ifp->if_snd, m0); 855 if (m0 == 0) 856 return; 857 858 /* We need to use m->m_pkthdr.len, so require the header. */ 859 if (!(m0->m_flags & M_PKTHDR)) 860 panic("xi_start: no header mbuf"); 861 862 len = m0->m_pkthdr.len; 863 864 #if 1 865 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 866 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 867 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 868 #else 869 pad = 0; 870 #endif 871 872 PAGE(sc, 0); 873 874 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 875 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 876 if (len + pad + 2 > space) { 877 DPRINTF(XID_FIFO, 878 ("xi: not enough space in output FIFO (%d > %d)\n", 879 len + pad + 2, space)); 880 return; 881 } 882 883 IFQ_DEQUEUE(&ifp->if_snd, m0); 884 885 #if NBPFILTER > 0 886 if (ifp->if_bpf) 887 bpf_mtap(ifp->if_bpf, m0); 888 #endif 889 890 /* 891 * Do the output at splhigh() so that an interrupt from another device 892 * won't cause a FIFO underrun. 893 */ 894 s = splhigh(); 895 896 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 897 for (m = m0; m; ) { 898 if (m->m_len > 1) 899 bus_space_write_multi_2(bst, bsh, EDP, 900 mtod(m, u_int16_t *), m->m_len>>1); 901 if (m->m_len & 1) { 902 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 903 bus_space_write_1(bst, bsh, EDP, 904 *(mtod(m, u_int8_t *) + m->m_len - 1)); 905 } 906 MFREE(m, m0); 907 m = m0; 908 } 909 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 910 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 911 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 912 else { 913 for (; pad > 1; pad -= 2) 914 bus_space_write_2(bst, bsh, EDP, 0); 915 if (pad == 1) 916 bus_space_write_1(bst, bsh, EDP, 0); 917 } 918 919 splx(s); 920 921 ifp->if_timer = 5; 922 ++ifp->if_opackets; 923 } 924 925 STATIC int 926 xi_ether_ioctl(ifp, cmd, data) 927 struct ifnet *ifp; 928 u_long cmd; 929 caddr_t data; 930 { 931 struct ifaddr *ifa = (struct ifaddr *)data; 932 struct xi_softc *sc = ifp->if_softc; 933 int error; 934 935 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 936 937 switch (cmd) { 938 case SIOCSIFADDR: 939 if ((error = xi_enable(sc)) != 0) 940 break; 941 942 ifp->if_flags |= IFF_UP; 943 944 switch (ifa->ifa_addr->sa_family) { 945 #ifdef INET 946 case AF_INET: 947 xi_init(sc); 948 arp_ifinit(ifp, ifa); 949 break; 950 #endif /* INET */ 951 952 #ifdef NS 953 case AF_NS: 954 { 955 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 956 957 if (ns_nullhost(*ina)) 958 ina->x_host = *(union ns_host *) 959 LLADDR(ifp->if_sadl); 960 else 961 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 962 ifp->if_addrlen); 963 /* Set new address. */ 964 xi_init(sc); 965 break; 966 } 967 #endif /* NS */ 968 969 default: 970 xi_init(sc); 971 break; 972 } 973 break; 974 975 default: 976 return (EINVAL); 977 } 978 979 return (0); 980 } 981 982 STATIC int 983 xi_ioctl(ifp, cmd, data) 984 struct ifnet *ifp; 985 u_long cmd; 986 caddr_t data; 987 { 988 struct xi_softc *sc = ifp->if_softc; 989 struct ifreq *ifr = (struct ifreq *)data; 990 int s, error = 0; 991 992 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 993 994 s = splnet(); 995 996 switch (cmd) { 997 case SIOCSIFADDR: 998 error = xi_ether_ioctl(ifp, cmd, data); 999 break; 1000 1001 case SIOCSIFFLAGS: 1002 if ((ifp->if_flags & IFF_UP) == 0 && 1003 (ifp->if_flags & IFF_RUNNING) != 0) { 1004 /* 1005 * If interface is marked down and it is running, 1006 * stop it. 1007 */ 1008 xi_stop(sc); 1009 ifp->if_flags &= ~IFF_RUNNING; 1010 xi_disable(sc); 1011 } else if ((ifp->if_flags & IFF_UP) != 0 && 1012 (ifp->if_flags & IFF_RUNNING) == 0) { 1013 /* 1014 * If interface is marked up and it is stopped, 1015 * start it. 1016 */ 1017 if ((error = xi_enable(sc)) != 0) 1018 break; 1019 xi_init(sc); 1020 } else if ((ifp->if_flags & IFF_UP) != 0) { 1021 /* 1022 * Reset the interface to pick up changes in any 1023 * other flags that affect hardware registers. 1024 */ 1025 xi_set_address(sc); 1026 } 1027 break; 1028 1029 case SIOCADDMULTI: 1030 case SIOCDELMULTI: 1031 if (sc->sc_enabled == 0) { 1032 error = EIO; 1033 break; 1034 } 1035 1036 error = (cmd == SIOCADDMULTI) ? 1037 ether_addmulti(ifr, &sc->sc_ethercom) : 1038 ether_delmulti(ifr, &sc->sc_ethercom); 1039 if (error == ENETRESET) { 1040 /* 1041 * Multicast list has changed; set the hardware 1042 * filter accordingly. 1043 */ 1044 xi_set_address(sc); 1045 error = 0; 1046 } 1047 break; 1048 1049 case SIOCSIFMEDIA: 1050 case SIOCGIFMEDIA: 1051 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1052 break; 1053 1054 default: 1055 error = EINVAL; 1056 break; 1057 } 1058 1059 splx(s); 1060 return (error); 1061 } 1062 1063 STATIC void 1064 xi_set_address(sc) 1065 struct xi_softc *sc; 1066 { 1067 bus_space_tag_t bst = sc->sc_bst; 1068 bus_space_handle_t bsh = sc->sc_bsh; 1069 struct ethercom *ether = &sc->sc_ethercom; 1070 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1071 struct ether_multistep step; 1072 struct ether_multi *enm; 1073 int page, num; 1074 int i; 1075 u_int8_t x; 1076 u_int8_t *enaddr; 1077 u_int8_t indaddr[64]; 1078 1079 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1080 1081 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 1082 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1083 for (i = 0; i < 6; i++) 1084 indaddr[i] = enaddr[5 - i]; 1085 else 1086 for (i = 0; i < 6; i++) 1087 indaddr[i] = enaddr[i]; 1088 num = 1; 1089 1090 if (ether->ec_multicnt > 9) { 1091 ifp->if_flags |= IFF_ALLMULTI; 1092 goto done; 1093 } 1094 1095 ETHER_FIRST_MULTI(step, ether, enm); 1096 for (; enm; num++) { 1097 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1098 sizeof(enm->enm_addrlo)) != 0) { 1099 /* 1100 * The multicast address is really a range; 1101 * it's easier just to accept all multicasts. 1102 * XXX should we be setting IFF_ALLMULTI here? 1103 */ 1104 ifp->if_flags |= IFF_ALLMULTI; 1105 goto done; 1106 } 1107 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1108 for (i = 0; i < 6; i++) 1109 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1110 else 1111 for (i = 0; i < 6; i++) 1112 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1113 ETHER_NEXT_MULTI(step, enm); 1114 } 1115 ifp->if_flags &= ~IFF_ALLMULTI; 1116 1117 done: 1118 if (num < 10) 1119 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1120 1121 for (page = 0; page < 8; page++) { 1122 #ifdef XIDEBUG 1123 if (xidebug & XID_MCAST) { 1124 printf("page %d before:", page); 1125 for (i = 0; i < 8; i++) 1126 printf(" %02x", indaddr[page * 8 + i]); 1127 printf("\n"); 1128 } 1129 #endif 1130 1131 PAGE(sc, 0x50 + page); 1132 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1133 page == 7 ? 4 : 8); 1134 /* 1135 * XXX 1136 * Without this delay, the address registers on my CE2 get 1137 * trashed the first and I have to cycle it. I have no idea 1138 * why. - mycroft, 2004/08/09 1139 */ 1140 DELAY(50); 1141 1142 #ifdef XIDEBUG 1143 if (xidebug & XID_MCAST) { 1144 bus_space_read_region_1(bst, bsh, IA, 1145 &indaddr[page * 8], page == 7 ? 4 : 8); 1146 printf("page %d after: ", page); 1147 for (i = 0; i < 8; i++) 1148 printf(" %02x", indaddr[page * 8 + i]); 1149 printf("\n"); 1150 } 1151 #endif 1152 } 1153 1154 PAGE(sc, 0x42); 1155 x = SWC1_IND_ADDR; 1156 if (ifp->if_flags & IFF_PROMISC) 1157 x |= SWC1_PROMISC; 1158 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1159 x |= SWC1_MCAST_PROM; 1160 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1161 x |= SWC1_AUTO_MEDIA; 1162 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1163 } 1164 1165 STATIC void 1166 xi_cycle_power(sc) 1167 struct xi_softc *sc; 1168 { 1169 bus_space_tag_t bst = sc->sc_bst; 1170 bus_space_handle_t bsh = sc->sc_bsh; 1171 1172 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1173 1174 PAGE(sc, 4); 1175 DELAY(1); 1176 bus_space_write_1(bst, bsh, GP1, 0); 1177 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1178 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1179 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1180 else 1181 /* XXX What is bit 2 (aka AIC)? */ 1182 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1183 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1184 } 1185 1186 STATIC void 1187 xi_full_reset(sc) 1188 struct xi_softc *sc; 1189 { 1190 bus_space_tag_t bst = sc->sc_bst; 1191 bus_space_handle_t bsh = sc->sc_bsh; 1192 u_int8_t x; 1193 1194 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1195 1196 /* Do an as extensive reset as possible on all functions. */ 1197 xi_cycle_power(sc); 1198 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1199 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1200 bus_space_write_1(bst, bsh, CR, 0); 1201 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1202 PAGE(sc, 4); 1203 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1204 /* 1205 * Drive GP1 low to power up ML6692 and GP2 high to power up 1206 * the 10MHz chip. XXX What chip is that? The phy? 1207 */ 1208 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1209 } 1210 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1211 1212 /* Get revision information. XXX Symbolic constants. */ 1213 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1214 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1215 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1216 1217 /* Media selection. XXX Maybe manual overriding too? */ 1218 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1219 /* 1220 * XXX I have no idea what this really does, it is from the 1221 * Linux driver. 1222 */ 1223 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1224 } 1225 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1226 1227 /* 1228 * Disable source insertion. 1229 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1230 */ 1231 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1232 PAGE(sc, 0x42); 1233 bus_space_write_1(bst, bsh, SWC0, 0x20); 1234 } 1235 1236 /* Set the local memory dividing line. */ 1237 if (sc->sc_rev != 1) { 1238 PAGE(sc, 2); 1239 /* XXX Symbolic constant preferrable. */ 1240 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1241 } 1242 1243 /* 1244 * Apparently the receive byte pointer can be bad after a reset, so 1245 * we hardwire it correctly. 1246 */ 1247 PAGE(sc, 0); 1248 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1249 1250 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1251 PAGE(sc, 0x40); 1252 bus_space_write_1(bst, bsh, RX0MSK, 1253 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1254 bus_space_write_1(bst, bsh, TX0MSK, 1255 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1256 SQE | TX_ABORT | TX_OK); 1257 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1258 /* XXX From Linux, dunno what 0xb0 means. */ 1259 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1260 bus_space_write_1(bst, bsh, RXST0, 0); 1261 bus_space_write_1(bst, bsh, TXST0, 0); 1262 bus_space_write_1(bst, bsh, TXST1, 0); 1263 1264 PAGE(sc, 2); 1265 1266 /* Enable MII function if available. */ 1267 x = 0; 1268 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1269 x |= SELECT_MII; 1270 bus_space_write_1(bst, bsh, MSR, x); 1271 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1272 1273 /* Configure the LED registers. */ 1274 /* XXX This is not good for 10base2. */ 1275 bus_space_write_1(bst, bsh, LED, 1276 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1277 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1278 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1279 1280 /* 1281 * The Linux driver says this: 1282 * We should switch back to page 0 to avoid a bug in revision 0 1283 * where regs with offset below 8 can't be read after an access 1284 * to the MAC registers. 1285 */ 1286 PAGE(sc, 0); 1287 } 1288