1 /* $NetBSD: if_xi.c,v 1.8 2001/01/14 17:39:24 thorpej Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include "opt_inet.h" 52 #include "bpfilter.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/socket.h> 61 62 #include <net/if.h> 63 #include <net/if_dl.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 #include <net/if_ether.h> 67 68 #ifdef INET 69 #include <netinet/in.h> 70 #include <netinet/in_systm.h> 71 #include <netinet/in_var.h> 72 #include <netinet/ip.h> 73 #include <netinet/if_inarp.h> 74 #endif 75 76 #ifdef IPX 77 #include <netipx/ipx.h> 78 #include <netipx/ipx_if.h> 79 #endif 80 81 #ifdef NS 82 #include <netns/ns.h> 83 #include <netns/ns_if.h> 84 #endif 85 86 #if NBPFILTER > 0 87 #include <net/bpf.h> 88 #include <net/bpfdesc.h> 89 #endif 90 91 #define ETHER_MIN_LEN 64 92 #define ETHER_CRC_LEN 4 93 94 /* 95 * Maximum number of bytes to read per interrupt. Linux recommends 96 * somewhere between 2000-22000. 97 * XXX This is currently a hard maximum. 98 */ 99 #define MAX_BYTES_INTR 12000 100 101 #include <dev/mii/mii.h> 102 #include <dev/mii/miivar.h> 103 104 #include <dev/pcmcia/pcmciareg.h> 105 #include <dev/pcmcia/pcmciavar.h> 106 #include <dev/pcmcia/pcmciadevs.h> 107 108 #define XI_IOSIZ 16 109 110 #include <dev/pcmcia/if_xireg.h> 111 112 #ifdef __GNUC__ 113 #define INLINE __inline 114 #else 115 #define INLINE 116 #endif /* __GNUC__ */ 117 118 #ifdef XIDEBUG 119 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 120 121 #define XID_CONFIG 0x1 122 #define XID_MII 0x2 123 #define XID_INTR 0x4 124 #define XID_FIFO 0x8 125 126 #ifdef XIDEBUG_VALUE 127 int xidebug = XIDEBUG_VALUE; 128 #else 129 int xidebug = 0; 130 #endif 131 #else 132 #define DPRINTF(cat, x) (void)0 133 #endif 134 135 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 136 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 137 int xi_pcmcia_detach __P((struct device *, int)); 138 int xi_pcmcia_activate __P((struct device *, enum devact)); 139 140 /* 141 * In case this chipset ever turns up out of pcmcia attachments (very 142 * unlikely) do the driver splitup. 143 */ 144 struct xi_softc { 145 struct device sc_dev; /* Generic device info */ 146 struct ethercom sc_ethercom; /* Ethernet common part */ 147 148 struct mii_data sc_mii; /* MII media information */ 149 150 bus_space_tag_t sc_bst; /* Bus cookie */ 151 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 152 bus_addr_t sc_offset; /* Offset of registers */ 153 154 u_int8_t sc_rev; /* Chip revision */ 155 u_int32_t sc_flags; /* Misc. flags */ 156 int sc_all_mcasts; /* Receive all multicasts */ 157 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 158 }; 159 160 struct xi_pcmcia_softc { 161 struct xi_softc sc_xi; /* Generic device info */ 162 163 /* PCMCIA-specific goo */ 164 struct pcmcia_function *sc_pf; /* PCMCIA function */ 165 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 166 int sc_io_window; /* io window info */ 167 void *sc_ih; /* Interrupt handler */ 168 169 int sc_resource; /* resource allocated */ 170 #define XI_RES_PCIC 1 171 #define XI_RES_IO 2 172 #define XI_RES_MI 8 173 }; 174 175 struct cfattach xi_pcmcia_ca = { 176 sizeof(struct xi_pcmcia_softc), xi_pcmcia_match, xi_pcmcia_attach, 177 xi_pcmcia_detach, xi_pcmcia_activate 178 }; 179 180 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 181 static void xi_cycle_power __P((struct xi_softc *)); 182 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 183 static void xi_full_reset __P((struct xi_softc *)); 184 static void xi_init __P((struct xi_softc *)); 185 static int xi_intr __P((void *)); 186 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 187 static int xi_mdi_read __P((struct device *, int, int)); 188 static void xi_mdi_write __P((struct device *, int, int, int)); 189 static int xi_mediachange __P((struct ifnet *)); 190 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 191 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 192 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 193 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 194 static u_int16_t xi_get __P((struct xi_softc *)); 195 static void xi_reset __P((struct xi_softc *)); 196 static void xi_set_address __P((struct xi_softc *)); 197 static void xi_start __P((struct ifnet *)); 198 static void xi_statchg __P((struct device *)); 199 static void xi_stop __P((struct xi_softc *)); 200 static void xi_watchdog __P((struct ifnet *)); 201 struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 202 struct pcmcia_attach_args *)); 203 204 /* flags */ 205 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 206 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 207 #define XIFLAGS_MODEM 0x004 /* modem also present */ 208 209 struct xi_pcmcia_product { 210 u_int32_t xpp_vendor; /* vendor ID */ 211 u_int32_t xpp_product; /* product ID */ 212 int xpp_expfunc; /* expected function number */ 213 int xpp_flags; /* initial softc flags */ 214 const char *xpp_name; /* device name */ 215 } xi_pcmcia_products[] = { 216 #ifdef NOT_SUPPORTED 217 { PCMCIA_VENDOR_XIRCOM, 0x0141, 218 0, 0, 219 PCMCIA_STR_XIRCOM_CE }, 220 #endif 221 { PCMCIA_VENDOR_XIRCOM, 0x0141, 222 0, 0, 223 PCMCIA_STR_XIRCOM_CE2 }, 224 { PCMCIA_VENDOR_XIRCOM, 0x0142, 225 0, 0, 226 PCMCIA_STR_XIRCOM_CE2 }, 227 { PCMCIA_VENDOR_XIRCOM, 0x0143, 228 0, XIFLAGS_MOHAWK, 229 PCMCIA_STR_XIRCOM_CE3 }, 230 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 231 0, XIFLAGS_MOHAWK, 232 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 233 { PCMCIA_VENDOR_INTEL, 0x0143, 234 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 235 PCMCIA_STR_INTEL_EEPRO100 }, 236 #ifdef NOT_SUPPORTED 237 { PCMCIA_VENDOR_XIRCOM, 0x1141, 238 0, XIFLAGS_MODEM, 239 PCMCIA_STR_XIRCOM_CEM }, 240 #endif 241 { PCMCIA_VENDOR_XIRCOM, 0x1142, 242 0, XIFLAGS_MODEM, 243 PCMCIA_STR_XIRCOM_CEM }, 244 { PCMCIA_VENDOR_XIRCOM, 0x1143, 245 0, XIFLAGS_MODEM, 246 PCMCIA_STR_XIRCOM_CEM }, 247 { PCMCIA_VENDOR_XIRCOM, 0x1144, 248 0, XIFLAGS_MODEM, 249 PCMCIA_STR_XIRCOM_CEM33 }, 250 { PCMCIA_VENDOR_XIRCOM, 0x1145, 251 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 252 PCMCIA_STR_XIRCOM_CEM56 }, 253 { PCMCIA_VENDOR_XIRCOM, 0x1146, 254 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 255 PCMCIA_STR_XIRCOM_REM56 }, 256 { PCMCIA_VENDOR_XIRCOM, 0x1147, 257 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 258 PCMCIA_STR_XIRCOM_REM56 }, 259 { 0, 0, 260 0, 0, 261 NULL }, 262 }; 263 264 265 struct xi_pcmcia_product * 266 xi_pcmcia_identify(dev, pa) 267 struct device *dev; 268 struct pcmcia_attach_args *pa; 269 { 270 struct xi_pcmcia_product *xpp; 271 u_int8_t id; 272 u_int32_t prod; 273 274 /* 275 * The Xircom ethernet cards swap the revision and product fields 276 * inside the CIS, which makes identification just a little 277 * bit different. 278 */ 279 280 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 281 282 prod = (pa->product & ~0xff) | id; 283 284 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 285 286 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 287 if (pa->manufacturer == xpp->xpp_vendor && 288 prod == xpp->xpp_product && 289 pa->pf->number == xpp->xpp_expfunc) 290 return (xpp); 291 return (NULL); 292 } 293 294 /* 295 * If someone can determine which manufacturers/products require cis_quirks, 296 * then the proper infrastucture can be used. Until then... 297 * This also becomes a pain with detaching. 298 */ 299 static int 300 xi_pcmcia_cis_quirks(pf) 301 struct pcmcia_function *pf; 302 { 303 struct pcmcia_config_entry *cfe; 304 305 /* Tell the pcmcia framework where the CCR is. */ 306 pf->ccr_base = 0x800; 307 pf->ccr_mask = 0x67; 308 309 /* Fake a cfe. */ 310 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 311 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT); 312 313 if (cfe == NULL) 314 return -1; 315 bzero(cfe, sizeof(*cfe)); 316 317 /* 318 * XXX Use preprocessor symbols instead. 319 * Enable ethernet & its interrupts, wiring them to -INT 320 * No I/O base. 321 */ 322 cfe->number = 0x5; 323 cfe->flags = 0; /* XXX Check! */ 324 cfe->iftype = PCMCIA_IFTYPE_IO; 325 cfe->num_iospace = 0; 326 cfe->num_memspace = 0; 327 cfe->irqmask = 0x8eb0; 328 329 return 0; 330 } 331 332 int 333 xi_pcmcia_match(parent, match, aux) 334 struct device *parent; 335 struct cfdata *match; 336 void *aux; 337 { 338 struct pcmcia_attach_args *pa = aux; 339 340 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 341 return (0); 342 343 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 344 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 345 return (1); 346 347 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 348 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 349 return (1); 350 351 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 352 ((pa->product >> 8) == XIMEDIA_ETHER || 353 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 354 return (1); 355 356 return (0); 357 } 358 359 void 360 xi_pcmcia_attach(parent, self, aux) 361 struct device *parent, *self; 362 void *aux; 363 { 364 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 365 struct xi_softc *sc = &psc->sc_xi; 366 struct pcmcia_attach_args *pa = aux; 367 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 368 struct xi_pcmcia_product *xpp; 369 370 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 371 printf(": function enable failed\n"); 372 return; 373 } 374 375 /* Enable the card */ 376 psc->sc_pf = pa->pf; 377 pcmcia_function_init(psc->sc_pf, psc->sc_pf->cfe_head.sqh_first); 378 if (pcmcia_function_enable(psc->sc_pf)) { 379 printf(": function enable failed\n"); 380 goto fail; 381 } 382 psc->sc_resource |= XI_RES_PCIC; 383 384 /* allocate/map ISA I/O space */ 385 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZ, XI_IOSIZ, 386 &psc->sc_pcioh) != 0) { 387 printf(": i/o allocation failed\n"); 388 goto fail; 389 } 390 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_IO16, 0, XI_IOSIZ, 391 &psc->sc_pcioh, &psc->sc_io_window)) { 392 printf(": can't map i/o space\n"); 393 goto fail; 394 } 395 sc->sc_bst = psc->sc_pcioh.iot; 396 sc->sc_bsh = psc->sc_pcioh.ioh; 397 sc->sc_offset = 0; 398 psc->sc_resource |= XI_RES_IO; 399 400 xpp = xi_pcmcia_identify(parent,pa); 401 if (xpp == NULL) { 402 printf(": unrecognised model\n"); 403 return; 404 } 405 sc->sc_flags = xpp->xpp_flags; 406 407 printf(": %s\n", xpp->xpp_name); 408 409 /* 410 * Configuration as adviced by DINGO documentation. 411 * Dingo has some extra configuration registers in the CCR space. 412 */ 413 if (sc->sc_flags & XIFLAGS_DINGO) { 414 struct pcmcia_mem_handle pcmh; 415 int ccr_window; 416 bus_addr_t ccr_offset; 417 418 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 419 &pcmh)) { 420 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 421 goto fail; 422 } 423 424 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 425 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 426 &pcmh, &ccr_offset, &ccr_window)) { 427 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 428 pcmcia_mem_free(psc->sc_pf, &pcmh); 429 goto fail; 430 } 431 432 bus_space_write_1(pcmh.memt, pcmh.memh, 433 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 434 bus_space_write_1(pcmh.memt, pcmh.memh, 435 ccr_offset + PCMCIA_CCR_DCOR1, 436 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 437 bus_space_write_1(pcmh.memt, pcmh.memh, 438 ccr_offset + PCMCIA_CCR_DCOR2, 0); 439 bus_space_write_1(pcmh.memt, pcmh.memh, 440 ccr_offset + PCMCIA_CCR_DCOR3, 0); 441 bus_space_write_1(pcmh.memt, pcmh.memh, 442 ccr_offset + PCMCIA_CCR_DCOR4, 0); 443 444 /* We don't need them anymore and can free them (I think). */ 445 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 446 pcmcia_mem_free(psc->sc_pf, &pcmh); 447 } 448 449 /* 450 * Try to get the ethernet address from FUNCE/LAN_NID tuple. 451 */ 452 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 453 if (!sc->sc_enaddr) { 454 printf("%s: unable to get ethernet address\n", 455 sc->sc_dev.dv_xname); 456 goto fail; 457 } 458 459 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 460 ether_sprintf(sc->sc_enaddr)); 461 462 ifp = &sc->sc_ethercom.ec_if; 463 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 464 ifp->if_softc = sc; 465 ifp->if_start = xi_start; 466 ifp->if_ioctl = xi_ioctl; 467 ifp->if_watchdog = xi_watchdog; 468 ifp->if_flags = 469 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 470 IFQ_SET_READY(&ifp->if_snd); 471 472 /* Reset and initialize the card. */ 473 xi_full_reset(sc); 474 475 /* 476 * Initialize our media structures and probe the MII. 477 */ 478 sc->sc_mii.mii_ifp = ifp; 479 sc->sc_mii.mii_readreg = xi_mdi_read; 480 sc->sc_mii.mii_writereg = xi_mdi_write; 481 sc->sc_mii.mii_statchg = xi_statchg; 482 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 483 xi_mediastatus); 484 DPRINTF(XID_MII | XID_CONFIG, 485 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 486 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 487 MII_OFFSET_ANY, 0); 488 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 489 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 490 NULL); 491 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 492 493 /* 494 * Attach the interface. 495 */ 496 if_attach(ifp); 497 ether_ifattach(ifp, sc->sc_enaddr); 498 psc->sc_resource |= XI_RES_MI; 499 500 /* 501 * Reset and initialize the card again for DINGO (as found in Linux 502 * driver). Without this Dingo will get a watchdog timeout the first 503 * time. The ugly media tickling seems to be necessary for getting 504 * autonegotiation to work too. 505 */ 506 if (sc->sc_flags & XIFLAGS_DINGO) { 507 xi_full_reset(sc); 508 xi_init(sc); 509 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 510 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 511 xi_stop(sc); 512 } 513 514 /* Establish the interrupt. */ 515 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 516 if (psc->sc_ih == NULL) { 517 printf("%s: couldn't establish interrupt\n", 518 sc->sc_dev.dv_xname); 519 goto fail; 520 } 521 522 return; 523 524 fail: 525 if ((psc->sc_resource & XI_RES_IO) != 0) { 526 /* Unmap our i/o windows. */ 527 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 528 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 529 } 530 psc->sc_resource &= ~XI_RES_IO; 531 if (psc->sc_resource & XI_RES_PCIC) { 532 pcmcia_function_disable(pa->pf); 533 psc->sc_resource &= ~XI_RES_PCIC; 534 } 535 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 536 } 537 538 int 539 xi_pcmcia_detach(self, flags) 540 struct device *self; 541 int flags; 542 { 543 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 544 struct xi_softc *sc = &psc->sc_xi; 545 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 546 547 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 548 549 if ((ifp->if_flags & IFF_RUNNING) == 0) { 550 xi_stop(sc); 551 } 552 553 pcmcia_function_disable(psc->sc_pf); 554 psc->sc_resource &= ~XI_RES_PCIC; 555 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 556 ifp->if_flags &= ~IFF_RUNNING; 557 ifp->if_timer = 0; 558 559 if ((psc->sc_resource & XI_RES_MI) != 0) { 560 561 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 562 563 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 564 565 ether_ifdetach(ifp); 566 if_detach(ifp); 567 psc->sc_resource &= ~XI_RES_MI; 568 } 569 570 if ((psc->sc_resource & XI_RES_IO) != 0) { 571 /* Unmap our i/o windows. */ 572 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 573 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 574 } 575 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 576 psc->sc_resource &= ~XI_RES_IO; 577 578 return 0; 579 } 580 581 int 582 xi_pcmcia_activate(self, act) 583 struct device *self; 584 enum devact act; 585 { 586 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 587 struct xi_softc *sc = &psc->sc_xi; 588 int s, rv=0; 589 590 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 591 592 s = splnet(); 593 switch (act) { 594 case DVACT_ACTIVATE: 595 rv = EOPNOTSUPP; 596 break; 597 598 case DVACT_DEACTIVATE: 599 if_deactivate(&sc->sc_ethercom.ec_if); 600 break; 601 } 602 splx(s); 603 return (rv); 604 } 605 606 /* 607 * XXX These two functions might be OK to factor out into pcmcia.c since 608 * if_sm_pcmcia.c uses similar ones. 609 */ 610 static int 611 xi_pcmcia_funce_enaddr(parent, myla) 612 struct device *parent; 613 u_int8_t *myla; 614 { 615 /* XXX The Linux driver has more ways to do this in case of failure. */ 616 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 617 } 618 619 static int 620 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 621 struct pcmcia_tuple *tuple; 622 void *arg; 623 { 624 u_int8_t *myla = arg; 625 int i; 626 627 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 628 629 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 630 if (tuple->length < 2) 631 return (0); 632 633 switch (pcmcia_tuple_read_1(tuple, 0)) { 634 case PCMCIA_TPLFE_TYPE_LAN_NID: 635 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 636 return (0); 637 break; 638 639 case 0x02: 640 /* 641 * Not sure about this, I don't have a CE2 642 * that puts the ethernet addr here. 643 */ 644 if (pcmcia_tuple_read_1(tuple, 1) != 13) 645 return (0); 646 break; 647 648 default: 649 return (0); 650 } 651 652 for (i = 0; i < ETHER_ADDR_LEN; i++) 653 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 654 return (1); 655 } 656 657 /* Yet another spot where this might be. */ 658 if (tuple->code == 0x89) { 659 pcmcia_tuple_read_1(tuple, 1); 660 for (i = 0; i < ETHER_ADDR_LEN; i++) 661 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 662 return (1); 663 } 664 return (0); 665 } 666 667 int 668 xi_pcmcia_manfid_ciscallback(tuple, arg) 669 struct pcmcia_tuple *tuple; 670 void *arg; 671 { 672 u_int8_t *id = arg; 673 674 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 675 676 if (tuple->code != PCMCIA_CISTPL_MANFID) 677 return (0); 678 679 if (tuple->length < 2) 680 return (0); 681 682 *id = pcmcia_tuple_read_1(tuple, 4); 683 return (1); 684 } 685 686 687 688 static int 689 xi_intr(arg) 690 void *arg; 691 { 692 struct xi_softc *sc = arg; 693 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 694 u_int8_t esr, rsr, isr, rx_status, savedpage; 695 u_int16_t tx_status, recvcount = 0, tempint; 696 697 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 698 699 #if 0 700 if (!(ifp->if_flags & IFF_RUNNING)) 701 return (0); 702 #endif 703 704 ifp->if_timer = 0; /* turn watchdog timer off */ 705 706 if (sc->sc_flags & XIFLAGS_MOHAWK) { 707 /* Disable interrupt (Linux does it). */ 708 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 709 0); 710 } 711 712 savedpage = 713 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 714 715 PAGE(sc, 0); 716 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 717 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 718 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 719 720 /* Check to see if card has been ejected. */ 721 if (isr == 0xff) { 722 #ifdef DIAGNOSTIC 723 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 724 #endif 725 goto end; 726 } 727 728 PAGE(sc, 40); 729 rx_status = 730 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 731 tx_status = 732 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 733 734 /* 735 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine 736 * without it, and I can't see an obvious reason for it. 737 */ 738 739 PAGE(sc, 0); 740 while (esr & FULL_PKT_RCV) { 741 if (!(rsr & RSR_RX_OK)) 742 break; 743 744 /* Compare bytes read this interrupt to hard maximum. */ 745 if (recvcount > MAX_BYTES_INTR) { 746 DPRINTF(XID_INTR, 747 ("xi: too many bytes this interrupt\n")); 748 ifp->if_iqdrops++; 749 /* Drop packet. */ 750 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 751 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 752 } 753 tempint = xi_get(sc); /* XXX doesn't check the error! */ 754 recvcount += tempint; 755 ifp->if_ibytes += tempint; 756 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 757 sc->sc_offset + ESR); 758 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 759 sc->sc_offset + RSR); 760 } 761 762 /* Packet too long? */ 763 if (rsr & RSR_TOO_LONG) { 764 ifp->if_ierrors++; 765 DPRINTF(XID_INTR, ("xi: packet too long\n")); 766 } 767 768 /* CRC error? */ 769 if (rsr & RSR_CRCERR) { 770 ifp->if_ierrors++; 771 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 772 } 773 774 /* Alignment error? */ 775 if (rsr & RSR_ALIGNERR) { 776 ifp->if_ierrors++; 777 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 778 } 779 780 /* Check for rx overrun. */ 781 if (rx_status & RX_OVERRUN) { 782 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 783 CLR_RX_OVERRUN); 784 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 785 } 786 787 /* Try to start more packets transmitting. */ 788 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 789 xi_start(ifp); 790 791 /* Detected excessive collisions? */ 792 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 793 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 794 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 795 RESTART_TX); 796 ifp->if_oerrors++; 797 } 798 799 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 800 ifp->if_oerrors++; 801 802 end: 803 /* Reenable interrupts. */ 804 PAGE(sc, savedpage); 805 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 806 ENABLE_INT); 807 808 return (1); 809 } 810 811 /* 812 * Pull a packet from the card into an mbuf chain. 813 */ 814 static u_int16_t 815 xi_get(sc) 816 struct xi_softc *sc; 817 { 818 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 819 struct mbuf *top, **mp, *m; 820 u_int16_t pktlen, len, recvcount = 0; 821 u_int8_t *data; 822 u_int8_t rsr; 823 824 DPRINTF(XID_CONFIG, ("xi_get()\n")); 825 826 PAGE(sc, 0); 827 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 828 829 pktlen = 830 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 831 RBC_COUNT_MASK; 832 833 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 834 835 if (pktlen == 0) { 836 /* 837 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 838 * when MPE is set. It is not known why. 839 */ 840 return (0); 841 } 842 843 /* XXX should this be incremented now ? */ 844 recvcount += pktlen; 845 846 MGETHDR(m, M_DONTWAIT, MT_DATA); 847 if (m == 0) 848 return (recvcount); 849 m->m_pkthdr.rcvif = ifp; 850 m->m_pkthdr.len = pktlen; 851 len = MHLEN; 852 top = 0; 853 mp = ⊤ 854 855 while (pktlen > 0) { 856 if (top) { 857 MGET(m, M_DONTWAIT, MT_DATA); 858 if (m == 0) { 859 m_freem(top); 860 return (recvcount); 861 } 862 len = MLEN; 863 } 864 if (pktlen >= MINCLSIZE) { 865 MCLGET(m, M_DONTWAIT); 866 if (!(m->m_flags & M_EXT)) { 867 m_freem(m); 868 m_freem(top); 869 return (recvcount); 870 } 871 len = MCLBYTES; 872 } 873 if (!top) { 874 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 875 sizeof(struct ether_header)) - 876 sizeof(struct ether_header); 877 len -= newdata - m->m_data; 878 m->m_data = newdata; 879 } 880 len = min(pktlen, len); 881 data = mtod(m, u_int8_t *); 882 if (len > 1) { 883 len &= ~1; 884 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 885 sc->sc_offset + EDP, data, len>>1); 886 } else 887 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 888 sc->sc_offset + EDP); 889 m->m_len = len; 890 pktlen -= len; 891 *mp = m; 892 mp = &m->m_next; 893 } 894 895 /* Skip Rx packet. */ 896 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 897 DO_SKIP_RX_PKT); 898 899 ifp->if_ipackets++; 900 901 #if NBPFILTER > 0 902 if (ifp->if_bpf) 903 bpf_mtap(ifp->if_bpf, top); 904 #endif 905 906 (*ifp->if_input)(ifp, top); 907 return (recvcount); 908 } 909 910 /* 911 * Serial management for the MII. 912 * The DELAY's below stem from the fact that the maximum frequency 913 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 914 * go much faster than that. 915 */ 916 917 /* Let the MII serial management be idle for one period. */ 918 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 919 static INLINE void 920 xi_mdi_idle(sc) 921 struct xi_softc *sc; 922 { 923 bus_space_tag_t bst = sc->sc_bst; 924 bus_space_handle_t bsh = sc->sc_bsh; 925 bus_addr_t offset = sc->sc_offset; 926 927 /* Drive MDC low... */ 928 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 929 DELAY(1); 930 931 /* and high again. */ 932 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 933 DELAY(1); 934 } 935 936 /* Pulse out one bit of data. */ 937 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 938 static INLINE void 939 xi_mdi_pulse(sc, data) 940 struct xi_softc *sc; 941 int data; 942 { 943 bus_space_tag_t bst = sc->sc_bst; 944 bus_space_handle_t bsh = sc->sc_bsh; 945 bus_addr_t offset = sc->sc_offset; 946 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 947 948 /* First latch the data bit MDIO with clock bit MDC low...*/ 949 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 950 DELAY(1); 951 952 /* then raise the clock again, preserving the data bit. */ 953 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 954 DELAY(1); 955 } 956 957 /* Probe one bit of data. */ 958 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 959 static INLINE int 960 xi_mdi_probe(sc) 961 struct xi_softc *sc; 962 { 963 bus_space_tag_t bst = sc->sc_bst; 964 bus_space_handle_t bsh = sc->sc_bsh; 965 bus_addr_t offset = sc->sc_offset; 966 u_int8_t x; 967 968 /* Pull clock bit MDCK low... */ 969 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 970 DELAY(1); 971 972 /* Read data and drive clock high again. */ 973 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 974 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 975 DELAY(1); 976 977 return (x); 978 } 979 980 /* Pulse out a sequence of data bits. */ 981 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 982 static INLINE void 983 xi_mdi_pulse_bits(sc, data, len) 984 struct xi_softc *sc; 985 u_int32_t data; 986 int len; 987 { 988 u_int32_t mask; 989 990 for (mask = 1 << (len - 1); mask; mask >>= 1) 991 xi_mdi_pulse(sc, data & mask); 992 } 993 994 /* Read a PHY register. */ 995 static int 996 xi_mdi_read(self, phy, reg) 997 struct device *self; 998 int phy; 999 int reg; 1000 { 1001 struct xi_softc *sc = (struct xi_softc *)self; 1002 int i; 1003 u_int32_t mask; 1004 u_int32_t data = 0; 1005 1006 PAGE(sc, 2); 1007 for (i = 0; i < 32; i++) /* Synchronize. */ 1008 xi_mdi_pulse(sc, 1); 1009 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1010 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1011 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1012 xi_mdi_idle(sc); /* Turn around. */ 1013 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1014 1015 for (mask = 1 << 15; mask; mask >>= 1) { 1016 if (xi_mdi_probe(sc)) 1017 data |= mask; 1018 } 1019 xi_mdi_idle(sc); 1020 1021 DPRINTF(XID_MII, 1022 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1023 1024 return (data); 1025 } 1026 1027 /* Write a PHY register. */ 1028 static void 1029 xi_mdi_write(self, phy, reg, value) 1030 struct device *self; 1031 int phy; 1032 int reg; 1033 int value; 1034 { 1035 struct xi_softc *sc = (struct xi_softc *)self; 1036 int i; 1037 1038 PAGE(sc, 2); 1039 for (i = 0; i < 32; i++) /* Synchronize. */ 1040 xi_mdi_pulse(sc, 1); 1041 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1042 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1043 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1044 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1045 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1046 xi_mdi_idle(sc); /* Idle away. */ 1047 1048 DPRINTF(XID_MII, 1049 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1050 } 1051 1052 static void 1053 xi_statchg(self) 1054 struct device *self; 1055 { 1056 /* XXX Update ifp->if_baudrate */ 1057 } 1058 1059 /* 1060 * Change media according to request. 1061 */ 1062 static int 1063 xi_mediachange(ifp) 1064 struct ifnet *ifp; 1065 { 1066 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1067 1068 if (ifp->if_flags & IFF_UP) 1069 xi_init(ifp->if_softc); 1070 return (0); 1071 } 1072 1073 /* 1074 * Notify the world which media we're using. 1075 */ 1076 static void 1077 xi_mediastatus(ifp, ifmr) 1078 struct ifnet *ifp; 1079 struct ifmediareq *ifmr; 1080 { 1081 struct xi_softc *sc = ifp->if_softc; 1082 1083 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1084 1085 mii_pollstat(&sc->sc_mii); 1086 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1087 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1088 } 1089 1090 static void 1091 xi_reset(sc) 1092 struct xi_softc *sc; 1093 { 1094 int s; 1095 1096 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1097 1098 s = splnet(); 1099 xi_stop(sc); 1100 xi_full_reset(sc); 1101 xi_init(sc); 1102 splx(s); 1103 } 1104 1105 static void 1106 xi_watchdog(ifp) 1107 struct ifnet *ifp; 1108 { 1109 struct xi_softc *sc = ifp->if_softc; 1110 1111 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1112 ++ifp->if_oerrors; 1113 1114 xi_reset(sc); 1115 } 1116 1117 static void 1118 xi_stop(sc) 1119 register struct xi_softc *sc; 1120 { 1121 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1122 1123 /* Disable interrupts. */ 1124 PAGE(sc, 0); 1125 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1126 1127 PAGE(sc, 1); 1128 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1129 1130 /* Power down, wait. */ 1131 PAGE(sc, 4); 1132 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1133 DELAY(40000); 1134 1135 /* Cancel watchdog timer. */ 1136 sc->sc_ethercom.ec_if.if_timer = 0; 1137 } 1138 1139 static void 1140 xi_init(sc) 1141 struct xi_softc *sc; 1142 { 1143 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1144 int s; 1145 1146 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1147 1148 s = splnet(); 1149 1150 xi_set_address(sc); 1151 1152 /* Set current media. */ 1153 mii_mediachg(&sc->sc_mii); 1154 1155 ifp->if_flags |= IFF_RUNNING; 1156 ifp->if_flags &= ~IFF_OACTIVE; 1157 splx(s); 1158 } 1159 1160 /* 1161 * Start outputting on the interface. 1162 * Always called as splnet(). 1163 */ 1164 static void 1165 xi_start(ifp) 1166 struct ifnet *ifp; 1167 { 1168 struct xi_softc *sc = ifp->if_softc; 1169 bus_space_tag_t bst = sc->sc_bst; 1170 bus_space_handle_t bsh = sc->sc_bsh; 1171 bus_addr_t offset = sc->sc_offset; 1172 unsigned int s, len, pad = 0; 1173 struct mbuf *m0, *m; 1174 u_int16_t space; 1175 1176 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1177 1178 /* Don't transmit if interface is busy or not running. */ 1179 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1180 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1181 return; 1182 } 1183 1184 /* Peek at the next packet. */ 1185 IFQ_POLL(&ifp->if_snd, m0); 1186 if (m0 == 0) 1187 return; 1188 1189 /* We need to use m->m_pkthdr.len, so require the header. */ 1190 if (!(m0->m_flags & M_PKTHDR)) 1191 panic("xi_start: no header mbuf"); 1192 1193 len = m0->m_pkthdr.len; 1194 1195 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1196 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1197 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1198 1199 PAGE(sc, 0); 1200 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1201 if (len + pad + 2 > space) { 1202 DPRINTF(XID_FIFO, 1203 ("xi: not enough space in output FIFO (%d > %d)\n", 1204 len + pad + 2, space)); 1205 return; 1206 } 1207 1208 IFQ_DEQUEUE(&ifp->if_snd, m0); 1209 1210 #if NBPFILTER > 0 1211 if (ifp->if_bpf) 1212 bpf_mtap(ifp->if_bpf, m0); 1213 #endif 1214 1215 /* 1216 * Do the output at splhigh() so that an interrupt from another device 1217 * won't cause a FIFO underrun. 1218 */ 1219 s = splhigh(); 1220 1221 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1222 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1223 for (m = m0; m; ) { 1224 if (m->m_len > 1) 1225 bus_space_write_multi_2(bst, bsh, offset + EDP, 1226 mtod(m, u_int8_t *), m->m_len>>1); 1227 if (m->m_len & 1) 1228 bus_space_write_1(bst, bsh, offset + EDP, 1229 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1230 MFREE(m, m0); 1231 m = m0; 1232 } 1233 if (sc->sc_flags & XIFLAGS_MOHAWK) 1234 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1235 else { 1236 for (; pad > 1; pad -= 2) 1237 bus_space_write_2(bst, bsh, offset + EDP, 0); 1238 if (pad == 1) 1239 bus_space_write_1(bst, bsh, offset + EDP, 0); 1240 } 1241 1242 splx(s); 1243 1244 ifp->if_timer = 5; 1245 ++ifp->if_opackets; 1246 } 1247 1248 static int 1249 xi_ether_ioctl(ifp, cmd, data) 1250 struct ifnet *ifp; 1251 u_long cmd; 1252 caddr_t data; 1253 { 1254 struct ifaddr *ifa = (struct ifaddr *)data; 1255 struct xi_softc *sc = ifp->if_softc; 1256 1257 1258 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1259 1260 switch (cmd) { 1261 case SIOCSIFADDR: 1262 ifp->if_flags |= IFF_UP; 1263 1264 switch (ifa->ifa_addr->sa_family) { 1265 #ifdef INET 1266 case AF_INET: 1267 xi_init(sc); 1268 arp_ifinit(ifp, ifa); 1269 break; 1270 #endif /* INET */ 1271 1272 #ifdef NS 1273 case AF_NS: 1274 { 1275 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1276 1277 if (ns_nullhost(*ina)) 1278 ina->x_host = *(union ns_host *) 1279 LLADDR(ifp->if_sadl); 1280 else 1281 bcopy(ina->x_host.c_host, 1282 LLADDR(ifp->if_sadl), 1283 ifp->if_addrlen); 1284 /* Set new address. */ 1285 xi_init(sc); 1286 break; 1287 } 1288 #endif /* NS */ 1289 1290 default: 1291 xi_init(sc); 1292 break; 1293 } 1294 break; 1295 1296 default: 1297 return (EINVAL); 1298 } 1299 1300 return (0); 1301 } 1302 1303 static int 1304 xi_ioctl(ifp, command, data) 1305 struct ifnet *ifp; 1306 u_long command; 1307 caddr_t data; 1308 { 1309 struct xi_softc *sc = ifp->if_softc; 1310 struct ifreq *ifr = (struct ifreq *)data; 1311 int s, error = 0; 1312 1313 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1314 1315 s = splnet(); 1316 1317 switch (command) { 1318 case SIOCSIFADDR: 1319 error = xi_ether_ioctl(ifp, command, data); 1320 break; 1321 1322 case SIOCSIFFLAGS: 1323 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1324 1325 PAGE(sc, 0x42); 1326 if ((ifp->if_flags & IFF_PROMISC) || 1327 (ifp->if_flags & IFF_ALLMULTI)) 1328 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1329 sc->sc_offset + SWC1, 1330 SWC1_PROMISC | SWC1_MCAST_PROM); 1331 else 1332 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1333 sc->sc_offset + SWC1, 0); 1334 1335 /* 1336 * If interface is marked up and not running, then start it. 1337 * If it is marked down and running, stop it. 1338 * XXX If it's up then re-initialize it. This is so flags 1339 * such as IFF_PROMISC are handled. 1340 */ 1341 if (ifp->if_flags & IFF_UP) { 1342 xi_init(sc); 1343 } else { 1344 if (ifp->if_flags & IFF_RUNNING) { 1345 xi_stop(sc); 1346 ifp->if_flags &= ~IFF_RUNNING; 1347 } 1348 } 1349 break; 1350 1351 case SIOCADDMULTI: 1352 case SIOCDELMULTI: 1353 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1354 error = (command == SIOCADDMULTI) ? 1355 ether_addmulti(ifr, &sc->sc_ethercom) : 1356 ether_delmulti(ifr, &sc->sc_ethercom); 1357 1358 if (error == ENETRESET) { 1359 /* 1360 * Multicast list has changed; set the hardware 1361 * filter accordingly. 1362 */ 1363 if (!sc->sc_all_mcasts && 1364 !(ifp->if_flags & IFF_PROMISC)) 1365 xi_set_address(sc); 1366 1367 /* 1368 * xi_set_address() can turn on all_mcasts if we run 1369 * out of space, so check it again rather than else {}. 1370 */ 1371 if (sc->sc_all_mcasts) 1372 xi_init(sc); 1373 error = 0; 1374 } 1375 break; 1376 1377 case SIOCSIFMEDIA: 1378 case SIOCGIFMEDIA: 1379 error = 1380 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1381 break; 1382 1383 default: 1384 error = EINVAL; 1385 } 1386 splx(s); 1387 return (error); 1388 } 1389 1390 static void 1391 xi_set_address(sc) 1392 struct xi_softc *sc; 1393 { 1394 bus_space_tag_t bst = sc->sc_bst; 1395 bus_space_handle_t bsh = sc->sc_bsh; 1396 bus_addr_t offset = sc->sc_offset; 1397 struct ethercom *ether = &sc->sc_ethercom; 1398 struct ether_multi *enm; 1399 struct ether_multistep step; 1400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1401 int i, page, pos, num; 1402 1403 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1404 1405 PAGE(sc, 0x50); 1406 for (i = 0; i < 6; i++) { 1407 bus_space_write_1(bst, bsh, offset + IA + i, 1408 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1409 } 1410 1411 if (ether->ec_multicnt > 0) { 1412 if (ether->ec_multicnt > 9) { 1413 PAGE(sc, 0x42); 1414 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1415 sc->sc_offset + SWC1, 1416 SWC1_PROMISC | SWC1_MCAST_PROM); 1417 return; 1418 } 1419 1420 ETHER_FIRST_MULTI(step, ether, enm); 1421 1422 pos = IA + 6; 1423 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1424 num--) { 1425 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 1426 sizeof(enm->enm_addrlo)) != 0) { 1427 /* 1428 * The multicast address is really a range; 1429 * it's easier just to accept all multicasts. 1430 * XXX should we be setting IFF_ALLMULTI here? 1431 */ 1432 ifp->if_flags |= IFF_ALLMULTI; 1433 sc->sc_all_mcasts=1; 1434 break; 1435 } 1436 1437 for (i = 0; i < 6; i++) { 1438 bus_space_write_1(bst, bsh, offset + pos, 1439 enm->enm_addrlo[ 1440 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1441 1442 if (++pos > 15) { 1443 pos = IA; 1444 page++; 1445 PAGE(sc, page); 1446 } 1447 } 1448 } 1449 } 1450 } 1451 1452 static void 1453 xi_cycle_power(sc) 1454 struct xi_softc *sc; 1455 { 1456 bus_space_tag_t bst = sc->sc_bst; 1457 bus_space_handle_t bsh = sc->sc_bsh; 1458 bus_addr_t offset = sc->sc_offset; 1459 1460 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1461 1462 PAGE(sc, 4); 1463 DELAY(1); 1464 bus_space_write_1(bst, bsh, offset + GP1, 0); 1465 DELAY(40000); 1466 if (sc->sc_flags & XIFLAGS_MOHAWK) 1467 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1468 else 1469 /* XXX What is bit 2 (aka AIC)? */ 1470 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1471 DELAY(20000); 1472 } 1473 1474 static void 1475 xi_full_reset(sc) 1476 struct xi_softc *sc; 1477 { 1478 bus_space_tag_t bst = sc->sc_bst; 1479 bus_space_handle_t bsh = sc->sc_bsh; 1480 bus_addr_t offset = sc->sc_offset; 1481 1482 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1483 1484 /* Do an as extensive reset as possible on all functions. */ 1485 xi_cycle_power(sc); 1486 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1487 DELAY(20000); 1488 bus_space_write_1(bst, bsh, offset + CR, 0); 1489 DELAY(20000); 1490 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1491 PAGE(sc, 4); 1492 /* 1493 * Drive GP1 low to power up ML6692 and GP2 high to power up 1494 * the 10Mhz chip. XXX What chip is that? The phy? 1495 */ 1496 bus_space_write_1(bst, bsh, offset + GP0, 1497 GP1_OUT | GP2_OUT | GP2_WR); 1498 } 1499 DELAY(500000); 1500 1501 /* Get revision information. XXX Symbolic constants. */ 1502 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1503 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1504 1505 /* Media selection. XXX Maybe manual overriding too? */ 1506 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1507 PAGE(sc, 4); 1508 /* 1509 * XXX I have no idea what this really does, it is from the 1510 * Linux driver. 1511 */ 1512 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1513 } 1514 DELAY(40000); 1515 1516 /* Setup the ethernet interrupt mask. */ 1517 PAGE(sc, 1); 1518 bus_space_write_1(bst, bsh, offset + IMR0, 1519 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1520 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1521 #if 0 1522 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1523 #endif 1524 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1525 /* XXX What is this? Not for Dingo at least. */ 1526 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1527 } 1528 1529 /* 1530 * Disable source insertion. 1531 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1532 */ 1533 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1534 PAGE(sc, 0x42); 1535 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1536 } 1537 1538 /* Set the local memory dividing line. */ 1539 if (sc->sc_rev != 1) { 1540 PAGE(sc, 2); 1541 /* XXX Symbolic constant preferrable. */ 1542 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1543 } 1544 1545 xi_set_address(sc); 1546 1547 /* 1548 * Apparently the receive byte pointer can be bad after a reset, so 1549 * we hardwire it correctly. 1550 */ 1551 PAGE(sc, 0); 1552 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1553 1554 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1555 PAGE(sc, 0x40); 1556 bus_space_write_1(bst, bsh, offset + RX0MSK, 1557 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1558 bus_space_write_1(bst, bsh, offset + TX0MSK, 1559 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1560 SQE | TX_ABORT | TX_OK); 1561 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1562 /* XXX From Linux, dunno what 0xb0 means. */ 1563 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1564 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1565 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1566 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1567 1568 /* Enable MII function if available. */ 1569 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1570 PAGE(sc, 2); 1571 bus_space_write_1(bst, bsh, offset + MSR, 1572 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1573 DELAY(20000); 1574 } else { 1575 PAGE(sc, 0); 1576 1577 /* XXX Do we need to do this? */ 1578 PAGE(sc, 0x42); 1579 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1580 DELAY(50000); 1581 1582 /* XXX Linux probes the media here. */ 1583 } 1584 1585 /* Configure the LED registers. */ 1586 PAGE(sc, 2); 1587 1588 /* XXX This is not good for 10base2. */ 1589 bus_space_write_1(bst, bsh, offset + LED, 1590 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1591 if (sc->sc_flags & XIFLAGS_DINGO) 1592 bus_space_write_1(bst, bsh, offset + LED3, 1593 LED_100MB_LINK << LED3_SHIFT); 1594 1595 /* Enable receiver and go online. */ 1596 PAGE(sc, 0x40); 1597 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1598 1599 #if 0 1600 /* XXX Linux does this here - is it necessary? */ 1601 PAGE(sc, 1); 1602 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1603 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1604 /* XXX What is this? Not for Dingo at least. */ 1605 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1606 } 1607 #endif 1608 1609 /* Enable interrupts. */ 1610 PAGE(sc, 0); 1611 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1612 1613 /* XXX This is pure magic for me, found in the Linux driver. */ 1614 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1615 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1616 /* Unmask the master interrupt bit. */ 1617 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1618 } 1619 1620 /* 1621 * The Linux driver says this: 1622 * We should switch back to page 0 to avoid a bug in revision 0 1623 * where regs with offset below 8 can't be read after an access 1624 * to the MAC registers. 1625 */ 1626 PAGE(sc, 0); 1627 } 1628