1 /* $NetBSD: if_xi.c,v 1.71 2010/04/05 07:21:47 joerg Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.71 2010/04/05 07:21:47 joerg Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/device.h> 66 #include <sys/ioctl.h> 67 #include <sys/mbuf.h> 68 #include <sys/malloc.h> 69 #include <sys/socket.h> 70 #include <sys/kernel.h> 71 #include <sys/proc.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_ether.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef IPX 88 #include <netipx/ipx.h> 89 #include <netipx/ipx_if.h> 90 #endif 91 92 93 #include <net/bpf.h> 94 #include <net/bpfdesc.h> 95 96 /* 97 * Maximum number of bytes to read per interrupt. Linux recommends 98 * somewhere between 2000-22000. 99 * XXX This is currently a hard maximum. 100 */ 101 #define MAX_BYTES_INTR 12000 102 103 #include <dev/mii/mii.h> 104 #include <dev/mii/miivar.h> 105 106 #include <dev/pcmcia/pcmciareg.h> 107 #include <dev/pcmcia/pcmciavar.h> 108 #include <dev/pcmcia/pcmciadevs.h> 109 110 #include <dev/pcmcia/if_xireg.h> 111 #include <dev/pcmcia/if_xivar.h> 112 113 #ifdef __GNUC__ 114 #define INLINE inline 115 #else 116 #define INLINE 117 #endif /* __GNUC__ */ 118 119 #define XIDEBUG 120 #define XIDEBUG_VALUE 0 121 122 #ifdef XIDEBUG 123 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 124 125 #define XID_CONFIG 0x01 126 #define XID_MII 0x02 127 #define XID_INTR 0x04 128 #define XID_FIFO 0x08 129 #define XID_MCAST 0x10 130 131 #ifdef XIDEBUG_VALUE 132 int xidebug = XIDEBUG_VALUE; 133 #else 134 int xidebug = 0; 135 #endif 136 #else 137 #define DPRINTF(cat, x) (void)0 138 #endif 139 140 #define STATIC 141 142 STATIC int xi_enable(struct xi_softc *); 143 STATIC void xi_disable(struct xi_softc *); 144 STATIC void xi_cycle_power(struct xi_softc *); 145 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 146 STATIC void xi_full_reset(struct xi_softc *); 147 STATIC void xi_init(struct xi_softc *); 148 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 149 STATIC int xi_mdi_read(device_t, int, int); 150 STATIC void xi_mdi_write(device_t, int, int, int); 151 STATIC int xi_mediachange(struct ifnet *); 152 STATIC u_int16_t xi_get(struct xi_softc *); 153 STATIC void xi_reset(struct xi_softc *); 154 STATIC void xi_set_address(struct xi_softc *); 155 STATIC void xi_start(struct ifnet *); 156 STATIC void xi_statchg(device_t); 157 STATIC void xi_stop(struct xi_softc *); 158 STATIC void xi_watchdog(struct ifnet *); 159 160 void 161 xi_attach(struct xi_softc *sc, u_int8_t *myea) 162 { 163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 164 165 #if 0 166 /* 167 * Configuration as advised by DINGO documentation. 168 * Dingo has some extra configuration registers in the CCR space. 169 */ 170 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 171 struct pcmcia_mem_handle pcmh; 172 int ccr_window; 173 bus_size_t ccr_offset; 174 175 /* get access to the DINGO CCR space */ 176 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 177 &pcmh)) { 178 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 179 goto fail; 180 } 181 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 182 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 183 &pcmh, &ccr_offset, &ccr_window)) { 184 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 185 pcmcia_mem_free(psc->sc_pf, &pcmh); 186 goto fail; 187 } 188 189 /* enable the second function - usually modem */ 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR1, 194 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 195 bus_space_write_1(pcmh.memt, pcmh.memh, 196 ccr_offset + PCMCIA_CCR_DCOR2, 0); 197 bus_space_write_1(pcmh.memt, pcmh.memh, 198 ccr_offset + PCMCIA_CCR_DCOR3, 0); 199 bus_space_write_1(pcmh.memt, pcmh.memh, 200 ccr_offset + PCMCIA_CCR_DCOR4, 0); 201 202 /* We don't need them anymore and can free them (I think). */ 203 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 204 pcmcia_mem_free(psc->sc_pf, &pcmh); 205 } 206 #endif 207 208 /* Reset and initialize the card. */ 209 xi_full_reset(sc); 210 211 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 212 213 ifp = &sc->sc_ethercom.ec_if; 214 /* Initialize the ifnet structure. */ 215 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 216 ifp->if_softc = sc; 217 ifp->if_start = xi_start; 218 ifp->if_ioctl = xi_ioctl; 219 ifp->if_watchdog = xi_watchdog; 220 ifp->if_flags = 221 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 222 IFQ_SET_READY(&ifp->if_snd); 223 224 /* 802.1q capability */ 225 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 226 227 /* Attach the interface. */ 228 if_attach(ifp); 229 ether_ifattach(ifp, myea); 230 231 /* 232 * Initialize our media structures and probe the MII. 233 */ 234 sc->sc_mii.mii_ifp = ifp; 235 sc->sc_mii.mii_readreg = xi_mdi_read; 236 sc->sc_mii.mii_writereg = xi_mdi_write; 237 sc->sc_mii.mii_statchg = xi_statchg; 238 sc->sc_ethercom.ec_mii = &sc->sc_mii; 239 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 240 ether_mediastatus); 241 DPRINTF(XID_MII | XID_CONFIG, 242 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 243 244 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 245 MII_OFFSET_ANY, 0); 246 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 247 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 248 NULL); 249 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 250 251 #if NRND > 0 252 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), RND_TYPE_NET, 0); 253 #endif 254 } 255 256 int 257 xi_detach(device_t self, int flags) 258 { 259 struct xi_softc *sc = device_private(self); 260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 261 262 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 263 264 xi_disable(sc); 265 266 #if NRND > 0 267 rnd_detach_source(&sc->sc_rnd_source); 268 #endif 269 270 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 271 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 272 ether_ifdetach(ifp); 273 if_detach(ifp); 274 275 return 0; 276 } 277 278 int 279 xi_intr(void *arg) 280 { 281 struct xi_softc *sc = arg; 282 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 283 u_int8_t esr, rsr, isr, rx_status; 284 u_int16_t tx_status, recvcount = 0, tempint; 285 286 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 287 288 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 289 return (0); 290 291 ifp->if_timer = 0; /* turn watchdog timer off */ 292 293 PAGE(sc, 0); 294 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 295 /* Disable interrupt (Linux does it). */ 296 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 297 } 298 299 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 300 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 301 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 302 303 /* Check to see if card has been ejected. */ 304 if (isr == 0xff) { 305 #ifdef DIAGNOSTIC 306 printf("%s: interrupt for dead card\n", 307 device_xname(sc->sc_dev)); 308 #endif 309 goto end; 310 } 311 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 312 313 PAGE(sc, 0x40); 314 rx_status = 315 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 316 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 317 tx_status = 318 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 319 tx_status |= 320 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 321 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 322 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 323 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 324 tx_status)); 325 326 PAGE(sc, 0); 327 while (esr & FULL_PKT_RCV) { 328 if (!(rsr & RSR_RX_OK)) 329 break; 330 331 /* Compare bytes read this interrupt to hard maximum. */ 332 if (recvcount > MAX_BYTES_INTR) { 333 DPRINTF(XID_INTR, 334 ("xi: too many bytes this interrupt\n")); 335 ifp->if_iqdrops++; 336 /* Drop packet. */ 337 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 338 DO_SKIP_RX_PKT); 339 } 340 tempint = xi_get(sc); /* XXX doesn't check the error! */ 341 recvcount += tempint; 342 ifp->if_ibytes += tempint; 343 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 344 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 345 } 346 347 /* Packet too long? */ 348 if (rsr & RSR_TOO_LONG) { 349 ifp->if_ierrors++; 350 DPRINTF(XID_INTR, ("xi: packet too long\n")); 351 } 352 353 /* CRC error? */ 354 if (rsr & RSR_CRCERR) { 355 ifp->if_ierrors++; 356 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 357 } 358 359 /* Alignment error? */ 360 if (rsr & RSR_ALIGNERR) { 361 ifp->if_ierrors++; 362 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 363 } 364 365 /* Check for rx overrun. */ 366 if (rx_status & RX_OVERRUN) { 367 ifp->if_ierrors++; 368 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 369 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 370 } 371 372 /* Try to start more packets transmitting. */ 373 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 374 xi_start(ifp); 375 376 /* Detected excessive collisions? */ 377 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 378 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 379 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 380 ifp->if_oerrors++; 381 } 382 383 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 384 ifp->if_oerrors++; 385 386 /* have handled the interrupt */ 387 #if NRND > 0 388 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 389 #endif 390 391 end: 392 /* Reenable interrupts. */ 393 PAGE(sc, 0); 394 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 395 396 return (1); 397 } 398 399 /* 400 * Pull a packet from the card into an mbuf chain. 401 */ 402 STATIC u_int16_t 403 xi_get(struct xi_softc *sc) 404 { 405 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 406 struct mbuf *top, **mp, *m; 407 u_int16_t pktlen, len, recvcount = 0; 408 u_int8_t *data; 409 410 DPRINTF(XID_CONFIG, ("xi_get()\n")); 411 412 PAGE(sc, 0); 413 pktlen = 414 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 415 416 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 417 418 if (pktlen == 0) { 419 /* 420 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 421 * when MPE is set. It is not known why. 422 */ 423 return (0); 424 } 425 426 /* XXX should this be incremented now ? */ 427 recvcount += pktlen; 428 429 MGETHDR(m, M_DONTWAIT, MT_DATA); 430 if (m == NULL) 431 return (recvcount); 432 m->m_pkthdr.rcvif = ifp; 433 m->m_pkthdr.len = pktlen; 434 len = MHLEN; 435 top = NULL; 436 mp = ⊤ 437 438 while (pktlen > 0) { 439 if (top) { 440 MGET(m, M_DONTWAIT, MT_DATA); 441 if (m == NULL) { 442 m_freem(top); 443 return (recvcount); 444 } 445 len = MLEN; 446 } 447 if (pktlen >= MINCLSIZE) { 448 MCLGET(m, M_DONTWAIT); 449 if (!(m->m_flags & M_EXT)) { 450 m_freem(m); 451 m_freem(top); 452 return (recvcount); 453 } 454 len = MCLBYTES; 455 } 456 if (top == NULL) { 457 char *newdata = (char *)ALIGN(m->m_data + 458 sizeof(struct ether_header)) - 459 sizeof(struct ether_header); 460 len -= newdata - m->m_data; 461 m->m_data = newdata; 462 } 463 len = min(pktlen, len); 464 data = mtod(m, u_int8_t *); 465 if (len > 1) { 466 len &= ~1; 467 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 468 (u_int16_t *)data, len>>1); 469 } else 470 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 471 m->m_len = len; 472 pktlen -= len; 473 *mp = m; 474 mp = &m->m_next; 475 } 476 477 /* Skip Rx packet. */ 478 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 479 480 if (top == NULL) 481 return recvcount; 482 483 /* Trim the CRC off the end of the packet. */ 484 m_adj(top, -ETHER_CRC_LEN); 485 486 ifp->if_ipackets++; 487 488 bpf_mtap(ifp, top); 489 490 (*ifp->if_input)(ifp, top); 491 return (recvcount); 492 } 493 494 /* 495 * Serial management for the MII. 496 * The DELAY's below stem from the fact that the maximum frequency 497 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 498 * go much faster than that. 499 */ 500 501 /* Let the MII serial management be idle for one period. */ 502 static INLINE void xi_mdi_idle(struct xi_softc *); 503 static INLINE void 504 xi_mdi_idle(struct xi_softc *sc) 505 { 506 bus_space_tag_t bst = sc->sc_bst; 507 bus_space_handle_t bsh = sc->sc_bsh; 508 509 /* Drive MDC low... */ 510 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 511 DELAY(1); 512 513 /* and high again. */ 514 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 515 DELAY(1); 516 } 517 518 /* Pulse out one bit of data. */ 519 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 520 static INLINE void 521 xi_mdi_pulse(struct xi_softc *sc, int data) 522 { 523 bus_space_tag_t bst = sc->sc_bst; 524 bus_space_handle_t bsh = sc->sc_bsh; 525 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 526 527 /* First latch the data bit MDIO with clock bit MDC low...*/ 528 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 529 DELAY(1); 530 531 /* then raise the clock again, preserving the data bit. */ 532 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 533 DELAY(1); 534 } 535 536 /* Probe one bit of data. */ 537 static INLINE int xi_mdi_probe(struct xi_softc *sc); 538 static INLINE int 539 xi_mdi_probe(struct xi_softc *sc) 540 { 541 bus_space_tag_t bst = sc->sc_bst; 542 bus_space_handle_t bsh = sc->sc_bsh; 543 u_int8_t x; 544 545 /* Pull clock bit MDCK low... */ 546 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 547 DELAY(1); 548 549 /* Read data and drive clock high again. */ 550 x = bus_space_read_1(bst, bsh, GP2); 551 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 552 DELAY(1); 553 554 return (x & MDIO); 555 } 556 557 /* Pulse out a sequence of data bits. */ 558 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 559 static INLINE void 560 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 561 { 562 u_int32_t mask; 563 564 for (mask = 1 << (len - 1); mask; mask >>= 1) 565 xi_mdi_pulse(sc, data & mask); 566 } 567 568 /* Read a PHY register. */ 569 STATIC int 570 xi_mdi_read(device_t self, int phy, int reg) 571 { 572 struct xi_softc *sc = device_private(self); 573 int i; 574 u_int32_t mask; 575 u_int32_t data = 0; 576 577 PAGE(sc, 2); 578 for (i = 0; i < 32; i++) /* Synchronize. */ 579 xi_mdi_pulse(sc, 1); 580 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 581 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 582 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 583 xi_mdi_idle(sc); /* Turn around. */ 584 xi_mdi_probe(sc); /* Drop initial zero bit. */ 585 586 for (mask = 1 << 15; mask; mask >>= 1) { 587 if (xi_mdi_probe(sc)) 588 data |= mask; 589 } 590 xi_mdi_idle(sc); 591 592 DPRINTF(XID_MII, 593 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 594 595 return (data); 596 } 597 598 /* Write a PHY register. */ 599 STATIC void 600 xi_mdi_write(device_t self, int phy, int reg, int value) 601 { 602 struct xi_softc *sc = device_private(self); 603 int i; 604 605 PAGE(sc, 2); 606 for (i = 0; i < 32; i++) /* Synchronize. */ 607 xi_mdi_pulse(sc, 1); 608 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 609 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 610 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 611 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 612 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 613 xi_mdi_idle(sc); /* Idle away. */ 614 615 DPRINTF(XID_MII, 616 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 617 } 618 619 STATIC void 620 xi_statchg(device_t self) 621 { 622 /* XXX Update ifp->if_baudrate */ 623 } 624 625 /* 626 * Change media according to request. 627 */ 628 STATIC int 629 xi_mediachange(struct ifnet *ifp) 630 { 631 int s; 632 633 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 634 635 if (ifp->if_flags & IFF_UP) { 636 s = splnet(); 637 xi_init(ifp->if_softc); 638 splx(s); 639 } 640 return (0); 641 } 642 643 STATIC void 644 xi_reset(struct xi_softc *sc) 645 { 646 int s; 647 648 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 649 650 s = splnet(); 651 xi_stop(sc); 652 xi_init(sc); 653 splx(s); 654 } 655 656 STATIC void 657 xi_watchdog(struct ifnet *ifp) 658 { 659 struct xi_softc *sc = ifp->if_softc; 660 661 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 662 ++ifp->if_oerrors; 663 664 xi_reset(sc); 665 } 666 667 STATIC void 668 xi_stop(register struct xi_softc *sc) 669 { 670 bus_space_tag_t bst = sc->sc_bst; 671 bus_space_handle_t bsh = sc->sc_bsh; 672 673 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 674 675 PAGE(sc, 0x40); 676 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 677 678 /* Disable interrupts. */ 679 PAGE(sc, 0); 680 bus_space_write_1(bst, bsh, CR, 0); 681 682 PAGE(sc, 1); 683 bus_space_write_1(bst, bsh, IMR0, 0); 684 685 /* Cancel watchdog timer. */ 686 sc->sc_ethercom.ec_if.if_timer = 0; 687 } 688 689 STATIC int 690 xi_enable(struct xi_softc *sc) 691 { 692 int error; 693 694 if (!sc->sc_enabled) { 695 error = (*sc->sc_enable)(sc); 696 if (error) 697 return (error); 698 sc->sc_enabled = 1; 699 xi_full_reset(sc); 700 } 701 return (0); 702 } 703 704 STATIC void 705 xi_disable(struct xi_softc *sc) 706 { 707 708 if (sc->sc_enabled) { 709 sc->sc_enabled = 0; 710 (*sc->sc_disable)(sc); 711 } 712 } 713 714 STATIC void 715 xi_init(struct xi_softc *sc) 716 { 717 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 718 bus_space_tag_t bst = sc->sc_bst; 719 bus_space_handle_t bsh = sc->sc_bsh; 720 721 DPRINTF(XID_CONFIG, ("xi_init()\n")); 722 723 /* Setup the ethernet interrupt mask. */ 724 PAGE(sc, 1); 725 bus_space_write_1(bst, bsh, IMR0, 726 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 727 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 728 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 729 /* XXX What is this? Not for Dingo at least. */ 730 /* Unmask TX underrun detection */ 731 bus_space_write_1(bst, bsh, IMR1, 1); 732 } 733 734 /* Enable interrupts. */ 735 PAGE(sc, 0); 736 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 737 738 xi_set_address(sc); 739 740 PAGE(sc, 0x40); 741 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 742 743 PAGE(sc, 0); 744 745 /* Set current media. */ 746 mii_mediachg(&sc->sc_mii); 747 748 ifp->if_flags |= IFF_RUNNING; 749 ifp->if_flags &= ~IFF_OACTIVE; 750 751 xi_start(ifp); 752 } 753 754 /* 755 * Start outputting on the interface. 756 * Always called as splnet(). 757 */ 758 STATIC void 759 xi_start(struct ifnet *ifp) 760 { 761 struct xi_softc *sc = ifp->if_softc; 762 bus_space_tag_t bst = sc->sc_bst; 763 bus_space_handle_t bsh = sc->sc_bsh; 764 unsigned int s, len, pad = 0; 765 struct mbuf *m0, *m; 766 u_int16_t space; 767 768 DPRINTF(XID_CONFIG, ("xi_start()\n")); 769 770 /* Don't transmit if interface is busy or not running. */ 771 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 772 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 773 return; 774 } 775 776 /* Peek at the next packet. */ 777 IFQ_POLL(&ifp->if_snd, m0); 778 if (m0 == 0) 779 return; 780 781 /* We need to use m->m_pkthdr.len, so require the header. */ 782 if (!(m0->m_flags & M_PKTHDR)) 783 panic("xi_start: no header mbuf"); 784 785 len = m0->m_pkthdr.len; 786 787 #if 1 788 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 789 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 790 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 791 #else 792 pad = 0; 793 #endif 794 795 PAGE(sc, 0); 796 797 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 798 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 799 if (len + pad + 2 > space) { 800 DPRINTF(XID_FIFO, 801 ("xi: not enough space in output FIFO (%d > %d)\n", 802 len + pad + 2, space)); 803 return; 804 } 805 806 IFQ_DEQUEUE(&ifp->if_snd, m0); 807 808 bpf_mtap(ifp, m0); 809 810 /* 811 * Do the output at splhigh() so that an interrupt from another device 812 * won't cause a FIFO underrun. 813 */ 814 s = splhigh(); 815 816 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 817 for (m = m0; m; ) { 818 if (m->m_len > 1) 819 bus_space_write_multi_2(bst, bsh, EDP, 820 mtod(m, u_int16_t *), m->m_len>>1); 821 if (m->m_len & 1) { 822 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 823 bus_space_write_1(bst, bsh, EDP, 824 *(mtod(m, u_int8_t *) + m->m_len - 1)); 825 } 826 MFREE(m, m0); 827 m = m0; 828 } 829 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 830 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 831 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 832 else { 833 for (; pad > 1; pad -= 2) 834 bus_space_write_2(bst, bsh, EDP, 0); 835 if (pad == 1) 836 bus_space_write_1(bst, bsh, EDP, 0); 837 } 838 839 splx(s); 840 841 ifp->if_timer = 5; 842 ++ifp->if_opackets; 843 } 844 845 STATIC int 846 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 847 { 848 struct ifaddr *ifa = (struct ifaddr *)data; 849 struct xi_softc *sc = ifp->if_softc; 850 int error; 851 852 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 853 854 switch (cmd) { 855 case SIOCINITIFADDR: 856 if ((error = xi_enable(sc)) != 0) 857 break; 858 859 ifp->if_flags |= IFF_UP; 860 861 xi_init(sc); 862 switch (ifa->ifa_addr->sa_family) { 863 #ifdef INET 864 case AF_INET: 865 arp_ifinit(ifp, ifa); 866 break; 867 #endif /* INET */ 868 869 870 default: 871 break; 872 } 873 break; 874 875 default: 876 return (EINVAL); 877 } 878 879 return (0); 880 } 881 882 STATIC int 883 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 884 { 885 struct xi_softc *sc = ifp->if_softc; 886 int s, error = 0; 887 888 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 889 890 s = splnet(); 891 892 switch (cmd) { 893 case SIOCINITIFADDR: 894 error = xi_ether_ioctl(ifp, cmd, data); 895 break; 896 897 case SIOCSIFFLAGS: 898 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 899 break; 900 /* XXX re-use ether_ioctl() */ 901 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 902 case IFF_RUNNING: 903 /* 904 * If interface is marked down and it is running, 905 * stop it. 906 */ 907 xi_stop(sc); 908 ifp->if_flags &= ~IFF_RUNNING; 909 xi_disable(sc); 910 break; 911 case IFF_UP: 912 /* 913 * If interface is marked up and it is stopped, 914 * start it. 915 */ 916 if ((error = xi_enable(sc)) != 0) 917 break; 918 xi_init(sc); 919 break; 920 case IFF_UP|IFF_RUNNING: 921 /* 922 * Reset the interface to pick up changes in any 923 * other flags that affect hardware registers. 924 */ 925 xi_set_address(sc); 926 break; 927 case 0: 928 break; 929 } 930 break; 931 932 case SIOCADDMULTI: 933 case SIOCDELMULTI: 934 if (sc->sc_enabled == 0) { 935 error = EIO; 936 break; 937 } 938 /*FALLTHROUGH*/ 939 case SIOCSIFMEDIA: 940 case SIOCGIFMEDIA: 941 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 942 /* 943 * Multicast list has changed; set the hardware 944 * filter accordingly. 945 */ 946 if (ifp->if_flags & IFF_RUNNING) 947 xi_set_address(sc); 948 error = 0; 949 } 950 break; 951 952 default: 953 error = ether_ioctl(ifp, cmd, data); 954 break; 955 } 956 957 splx(s); 958 return (error); 959 } 960 961 STATIC void 962 xi_set_address(struct xi_softc *sc) 963 { 964 bus_space_tag_t bst = sc->sc_bst; 965 bus_space_handle_t bsh = sc->sc_bsh; 966 struct ethercom *ether = &sc->sc_ethercom; 967 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 968 struct ether_multistep step; 969 struct ether_multi *enm; 970 int page, num; 971 int i; 972 u_int8_t x; 973 const u_int8_t *enaddr; 974 u_int8_t indaddr[64]; 975 976 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 977 978 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 979 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 980 for (i = 0; i < 6; i++) 981 indaddr[i] = enaddr[5 - i]; 982 else 983 for (i = 0; i < 6; i++) 984 indaddr[i] = enaddr[i]; 985 num = 1; 986 987 if (ether->ec_multicnt > 9) { 988 ifp->if_flags |= IFF_ALLMULTI; 989 goto done; 990 } 991 992 ETHER_FIRST_MULTI(step, ether, enm); 993 for (; enm; num++) { 994 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 995 sizeof(enm->enm_addrlo)) != 0) { 996 /* 997 * The multicast address is really a range; 998 * it's easier just to accept all multicasts. 999 * XXX should we be setting IFF_ALLMULTI here? 1000 */ 1001 ifp->if_flags |= IFF_ALLMULTI; 1002 goto done; 1003 } 1004 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1005 for (i = 0; i < 6; i++) 1006 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1007 else 1008 for (i = 0; i < 6; i++) 1009 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1010 ETHER_NEXT_MULTI(step, enm); 1011 } 1012 ifp->if_flags &= ~IFF_ALLMULTI; 1013 1014 done: 1015 if (num < 10) 1016 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1017 1018 for (page = 0; page < 8; page++) { 1019 #ifdef XIDEBUG 1020 if (xidebug & XID_MCAST) { 1021 printf("page %d before:", page); 1022 for (i = 0; i < 8; i++) 1023 printf(" %02x", indaddr[page * 8 + i]); 1024 printf("\n"); 1025 } 1026 #endif 1027 1028 PAGE(sc, 0x50 + page); 1029 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1030 page == 7 ? 4 : 8); 1031 /* 1032 * XXX 1033 * Without this delay, the address registers on my CE2 get 1034 * trashed the first and I have to cycle it. I have no idea 1035 * why. - mycroft, 2004/08/09 1036 */ 1037 DELAY(50); 1038 1039 #ifdef XIDEBUG 1040 if (xidebug & XID_MCAST) { 1041 bus_space_read_region_1(bst, bsh, IA, 1042 &indaddr[page * 8], page == 7 ? 4 : 8); 1043 printf("page %d after: ", page); 1044 for (i = 0; i < 8; i++) 1045 printf(" %02x", indaddr[page * 8 + i]); 1046 printf("\n"); 1047 } 1048 #endif 1049 } 1050 1051 PAGE(sc, 0x42); 1052 x = SWC1_IND_ADDR; 1053 if (ifp->if_flags & IFF_PROMISC) 1054 x |= SWC1_PROMISC; 1055 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1056 x |= SWC1_MCAST_PROM; 1057 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1058 x |= SWC1_AUTO_MEDIA; 1059 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1060 } 1061 1062 STATIC void 1063 xi_cycle_power(struct xi_softc *sc) 1064 { 1065 bus_space_tag_t bst = sc->sc_bst; 1066 bus_space_handle_t bsh = sc->sc_bsh; 1067 1068 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1069 1070 PAGE(sc, 4); 1071 DELAY(1); 1072 bus_space_write_1(bst, bsh, GP1, 0); 1073 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1074 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1075 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1076 else 1077 /* XXX What is bit 2 (aka AIC)? */ 1078 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1079 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1080 } 1081 1082 STATIC void 1083 xi_full_reset(struct xi_softc *sc) 1084 { 1085 bus_space_tag_t bst = sc->sc_bst; 1086 bus_space_handle_t bsh = sc->sc_bsh; 1087 u_int8_t x; 1088 1089 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1090 1091 /* Do an as extensive reset as possible on all functions. */ 1092 xi_cycle_power(sc); 1093 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1094 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1095 bus_space_write_1(bst, bsh, CR, 0); 1096 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1097 PAGE(sc, 4); 1098 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1099 /* 1100 * Drive GP1 low to power up ML6692 and GP2 high to power up 1101 * the 10MHz chip. XXX What chip is that? The phy? 1102 */ 1103 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1104 } 1105 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1106 1107 /* Get revision information. XXX Symbolic constants. */ 1108 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1109 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1110 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1111 1112 /* Media selection. XXX Maybe manual overriding too? */ 1113 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1114 /* 1115 * XXX I have no idea what this really does, it is from the 1116 * Linux driver. 1117 */ 1118 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1119 } 1120 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1121 1122 /* 1123 * Disable source insertion. 1124 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1125 */ 1126 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1127 PAGE(sc, 0x42); 1128 bus_space_write_1(bst, bsh, SWC0, 0x20); 1129 } 1130 1131 /* Set the local memory dividing line. */ 1132 if (sc->sc_rev != 1) { 1133 PAGE(sc, 2); 1134 /* XXX Symbolic constant preferrable. */ 1135 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1136 } 1137 1138 /* 1139 * Apparently the receive byte pointer can be bad after a reset, so 1140 * we hardwire it correctly. 1141 */ 1142 PAGE(sc, 0); 1143 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1144 1145 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1146 PAGE(sc, 0x40); 1147 bus_space_write_1(bst, bsh, RX0MSK, 1148 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1149 bus_space_write_1(bst, bsh, TX0MSK, 1150 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1151 SQE | TX_ABORT | TX_OK); 1152 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1153 /* XXX From Linux, dunno what 0xb0 means. */ 1154 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1155 bus_space_write_1(bst, bsh, RXST0, 0); 1156 bus_space_write_1(bst, bsh, TXST0, 0); 1157 bus_space_write_1(bst, bsh, TXST1, 0); 1158 1159 PAGE(sc, 2); 1160 1161 /* Enable MII function if available. */ 1162 x = 0; 1163 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1164 x |= SELECT_MII; 1165 bus_space_write_1(bst, bsh, MSR, x); 1166 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1167 1168 /* Configure the LED registers. */ 1169 /* XXX This is not good for 10base2. */ 1170 bus_space_write_1(bst, bsh, LED, 1171 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1172 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1173 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1174 1175 /* 1176 * The Linux driver says this: 1177 * We should switch back to page 0 to avoid a bug in revision 0 1178 * where regs with offset below 8 can't be read after an access 1179 * to the MAC registers. 1180 */ 1181 PAGE(sc, 0); 1182 } 1183