1 /* $NetBSD: if_xi.c,v 1.54 2005/12/24 20:27:52 perry Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.54 2005/12/24 20:27:52 perry Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 #ifdef NS 94 #include <netns/ns.h> 95 #include <netns/ns_if.h> 96 #endif 97 98 #if NBPFILTER > 0 99 #include <net/bpf.h> 100 #include <net/bpfdesc.h> 101 #endif 102 103 /* 104 * Maximum number of bytes to read per interrupt. Linux recommends 105 * somewhere between 2000-22000. 106 * XXX This is currently a hard maximum. 107 */ 108 #define MAX_BYTES_INTR 12000 109 110 #include <dev/mii/mii.h> 111 #include <dev/mii/miivar.h> 112 113 #include <dev/pcmcia/pcmciareg.h> 114 #include <dev/pcmcia/pcmciavar.h> 115 #include <dev/pcmcia/pcmciadevs.h> 116 117 #include <dev/pcmcia/if_xireg.h> 118 #include <dev/pcmcia/if_xivar.h> 119 120 #ifdef __GNUC__ 121 #define INLINE inline 122 #else 123 #define INLINE 124 #endif /* __GNUC__ */ 125 126 #define XIDEBUG 127 #define XIDEBUG_VALUE 0 128 129 #ifdef XIDEBUG 130 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 131 132 #define XID_CONFIG 0x01 133 #define XID_MII 0x02 134 #define XID_INTR 0x04 135 #define XID_FIFO 0x08 136 #define XID_MCAST 0x10 137 138 #ifdef XIDEBUG_VALUE 139 int xidebug = XIDEBUG_VALUE; 140 #else 141 int xidebug = 0; 142 #endif 143 #else 144 #define DPRINTF(cat, x) (void)0 145 #endif 146 147 #define STATIC 148 149 STATIC int xi_enable(struct xi_softc *); 150 STATIC void xi_disable(struct xi_softc *); 151 STATIC void xi_cycle_power(struct xi_softc *); 152 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, caddr_t); 153 STATIC void xi_full_reset(struct xi_softc *); 154 STATIC void xi_init(struct xi_softc *); 155 STATIC int xi_ioctl(struct ifnet *, u_long, caddr_t); 156 STATIC int xi_mdi_read(struct device *, int, int); 157 STATIC void xi_mdi_write(struct device *, int, int, int); 158 STATIC int xi_mediachange(struct ifnet *); 159 STATIC void xi_mediastatus(struct ifnet *, struct ifmediareq *); 160 STATIC u_int16_t xi_get(struct xi_softc *); 161 STATIC void xi_reset(struct xi_softc *); 162 STATIC void xi_set_address(struct xi_softc *); 163 STATIC void xi_start(struct ifnet *); 164 STATIC void xi_statchg(struct device *); 165 STATIC void xi_stop(struct xi_softc *); 166 STATIC void xi_watchdog(struct ifnet *); 167 168 void 169 xi_attach(sc, myea) 170 struct xi_softc *sc; 171 u_int8_t *myea; 172 { 173 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 174 175 #if 0 176 /* 177 * Configuration as advised by DINGO documentation. 178 * Dingo has some extra configuration registers in the CCR space. 179 */ 180 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 181 struct pcmcia_mem_handle pcmh; 182 int ccr_window; 183 bus_size_t ccr_offset; 184 185 /* get access to the DINGO CCR space */ 186 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 187 &pcmh)) { 188 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 189 goto fail; 190 } 191 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 192 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 193 &pcmh, &ccr_offset, &ccr_window)) { 194 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 195 pcmcia_mem_free(psc->sc_pf, &pcmh); 196 goto fail; 197 } 198 199 /* enable the second function - usually modem */ 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR1, 204 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 205 bus_space_write_1(pcmh.memt, pcmh.memh, 206 ccr_offset + PCMCIA_CCR_DCOR2, 0); 207 bus_space_write_1(pcmh.memt, pcmh.memh, 208 ccr_offset + PCMCIA_CCR_DCOR3, 0); 209 bus_space_write_1(pcmh.memt, pcmh.memh, 210 ccr_offset + PCMCIA_CCR_DCOR4, 0); 211 212 /* We don't need them anymore and can free them (I think). */ 213 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 214 pcmcia_mem_free(psc->sc_pf, &pcmh); 215 } 216 #endif 217 218 /* Reset and initialize the card. */ 219 xi_full_reset(sc); 220 221 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, ether_sprintf(myea)); 222 223 ifp = &sc->sc_ethercom.ec_if; 224 /* Initialize the ifnet structure. */ 225 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 226 ifp->if_softc = sc; 227 ifp->if_start = xi_start; 228 ifp->if_ioctl = xi_ioctl; 229 ifp->if_watchdog = xi_watchdog; 230 ifp->if_flags = 231 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 232 IFQ_SET_READY(&ifp->if_snd); 233 234 /* 802.1q capability */ 235 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 236 237 /* Attach the interface. */ 238 if_attach(ifp); 239 ether_ifattach(ifp, myea); 240 241 /* 242 * Initialize our media structures and probe the MII. 243 */ 244 sc->sc_mii.mii_ifp = ifp; 245 sc->sc_mii.mii_readreg = xi_mdi_read; 246 sc->sc_mii.mii_writereg = xi_mdi_write; 247 sc->sc_mii.mii_statchg = xi_statchg; 248 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 249 xi_mediastatus); 250 DPRINTF(XID_MII | XID_CONFIG, 251 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 252 253 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 254 MII_OFFSET_ANY, 0); 255 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 256 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 257 NULL); 258 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 259 260 #if NRND > 0 261 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET, 0); 262 #endif 263 } 264 265 int 266 xi_detach(self, flags) 267 struct device *self; 268 int flags; 269 { 270 struct xi_softc *sc = (void *)self; 271 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 272 273 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 274 275 xi_disable(sc); 276 277 #if NRND > 0 278 rnd_detach_source(&sc->sc_rnd_source); 279 #endif 280 281 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 282 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 283 ether_ifdetach(ifp); 284 if_detach(ifp); 285 286 return 0; 287 } 288 289 int 290 xi_activate(self, act) 291 struct device *self; 292 enum devact act; 293 { 294 struct xi_softc *sc = (void *)self; 295 int s, rv = 0; 296 297 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 298 299 s = splnet(); 300 switch (act) { 301 case DVACT_ACTIVATE: 302 rv = EOPNOTSUPP; 303 break; 304 305 case DVACT_DEACTIVATE: 306 if_deactivate(&sc->sc_ethercom.ec_if); 307 break; 308 } 309 splx(s); 310 return (rv); 311 } 312 313 int 314 xi_intr(arg) 315 void *arg; 316 { 317 struct xi_softc *sc = arg; 318 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 319 u_int8_t esr, rsr, isr, rx_status; 320 u_int16_t tx_status, recvcount = 0, tempint; 321 322 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 323 324 if (sc->sc_enabled == 0 || 325 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 326 return (0); 327 328 ifp->if_timer = 0; /* turn watchdog timer off */ 329 330 PAGE(sc, 0); 331 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 332 /* Disable interrupt (Linux does it). */ 333 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 334 } 335 336 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 337 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 338 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 339 340 /* Check to see if card has been ejected. */ 341 if (isr == 0xff) { 342 #ifdef DIAGNOSTIC 343 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 344 #endif 345 goto end; 346 } 347 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 348 349 PAGE(sc, 0x40); 350 rx_status = 351 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 352 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 353 tx_status = 354 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 355 tx_status |= 356 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 357 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 358 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 359 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 360 tx_status)); 361 362 PAGE(sc, 0); 363 while (esr & FULL_PKT_RCV) { 364 if (!(rsr & RSR_RX_OK)) 365 break; 366 367 /* Compare bytes read this interrupt to hard maximum. */ 368 if (recvcount > MAX_BYTES_INTR) { 369 DPRINTF(XID_INTR, 370 ("xi: too many bytes this interrupt\n")); 371 ifp->if_iqdrops++; 372 /* Drop packet. */ 373 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 374 DO_SKIP_RX_PKT); 375 } 376 tempint = xi_get(sc); /* XXX doesn't check the error! */ 377 recvcount += tempint; 378 ifp->if_ibytes += tempint; 379 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 380 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 381 } 382 383 /* Packet too long? */ 384 if (rsr & RSR_TOO_LONG) { 385 ifp->if_ierrors++; 386 DPRINTF(XID_INTR, ("xi: packet too long\n")); 387 } 388 389 /* CRC error? */ 390 if (rsr & RSR_CRCERR) { 391 ifp->if_ierrors++; 392 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 393 } 394 395 /* Alignment error? */ 396 if (rsr & RSR_ALIGNERR) { 397 ifp->if_ierrors++; 398 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 399 } 400 401 /* Check for rx overrun. */ 402 if (rx_status & RX_OVERRUN) { 403 ifp->if_ierrors++; 404 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 405 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 406 } 407 408 /* Try to start more packets transmitting. */ 409 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 410 xi_start(ifp); 411 412 /* Detected excessive collisions? */ 413 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 414 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 415 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 416 ifp->if_oerrors++; 417 } 418 419 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 420 ifp->if_oerrors++; 421 422 /* have handled the interrupt */ 423 #if NRND > 0 424 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 425 #endif 426 427 end: 428 /* Reenable interrupts. */ 429 PAGE(sc, 0); 430 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 431 432 return (1); 433 } 434 435 /* 436 * Pull a packet from the card into an mbuf chain. 437 */ 438 STATIC u_int16_t 439 xi_get(sc) 440 struct xi_softc *sc; 441 { 442 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 443 struct mbuf *top, **mp, *m; 444 u_int16_t pktlen, len, recvcount = 0; 445 u_int8_t *data; 446 447 DPRINTF(XID_CONFIG, ("xi_get()\n")); 448 449 PAGE(sc, 0); 450 pktlen = 451 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 452 453 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 454 455 if (pktlen == 0) { 456 /* 457 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 458 * when MPE is set. It is not known why. 459 */ 460 return (0); 461 } 462 463 /* XXX should this be incremented now ? */ 464 recvcount += pktlen; 465 466 MGETHDR(m, M_DONTWAIT, MT_DATA); 467 if (m == 0) 468 return (recvcount); 469 m->m_pkthdr.rcvif = ifp; 470 m->m_pkthdr.len = pktlen; 471 len = MHLEN; 472 top = 0; 473 mp = ⊤ 474 475 while (pktlen > 0) { 476 if (top) { 477 MGET(m, M_DONTWAIT, MT_DATA); 478 if (m == 0) { 479 m_freem(top); 480 return (recvcount); 481 } 482 len = MLEN; 483 } 484 if (pktlen >= MINCLSIZE) { 485 MCLGET(m, M_DONTWAIT); 486 if (!(m->m_flags & M_EXT)) { 487 m_freem(m); 488 m_freem(top); 489 return (recvcount); 490 } 491 len = MCLBYTES; 492 } 493 if (!top) { 494 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 495 sizeof(struct ether_header)) - 496 sizeof(struct ether_header); 497 len -= newdata - m->m_data; 498 m->m_data = newdata; 499 } 500 len = min(pktlen, len); 501 data = mtod(m, u_int8_t *); 502 if (len > 1) { 503 len &= ~1; 504 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 505 (u_int16_t *)data, len>>1); 506 } else 507 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 508 m->m_len = len; 509 pktlen -= len; 510 *mp = m; 511 mp = &m->m_next; 512 } 513 514 /* Skip Rx packet. */ 515 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 516 517 /* Trim the CRC off the end of the packet. */ 518 m_adj(top, -ETHER_CRC_LEN); 519 520 ifp->if_ipackets++; 521 522 #if NBPFILTER > 0 523 if (ifp->if_bpf) 524 bpf_mtap(ifp->if_bpf, top); 525 #endif 526 527 (*ifp->if_input)(ifp, top); 528 return (recvcount); 529 } 530 531 /* 532 * Serial management for the MII. 533 * The DELAY's below stem from the fact that the maximum frequency 534 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 535 * go much faster than that. 536 */ 537 538 /* Let the MII serial management be idle for one period. */ 539 static INLINE void xi_mdi_idle(struct xi_softc *); 540 static INLINE void 541 xi_mdi_idle(sc) 542 struct xi_softc *sc; 543 { 544 bus_space_tag_t bst = sc->sc_bst; 545 bus_space_handle_t bsh = sc->sc_bsh; 546 547 /* Drive MDC low... */ 548 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 549 DELAY(1); 550 551 /* and high again. */ 552 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 553 DELAY(1); 554 } 555 556 /* Pulse out one bit of data. */ 557 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 558 static INLINE void 559 xi_mdi_pulse(sc, data) 560 struct xi_softc *sc; 561 int data; 562 { 563 bus_space_tag_t bst = sc->sc_bst; 564 bus_space_handle_t bsh = sc->sc_bsh; 565 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 566 567 /* First latch the data bit MDIO with clock bit MDC low...*/ 568 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 569 DELAY(1); 570 571 /* then raise the clock again, preserving the data bit. */ 572 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 573 DELAY(1); 574 } 575 576 /* Probe one bit of data. */ 577 static INLINE int xi_mdi_probe(struct xi_softc *sc); 578 static INLINE int 579 xi_mdi_probe(sc) 580 struct xi_softc *sc; 581 { 582 bus_space_tag_t bst = sc->sc_bst; 583 bus_space_handle_t bsh = sc->sc_bsh; 584 u_int8_t x; 585 586 /* Pull clock bit MDCK low... */ 587 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 588 DELAY(1); 589 590 /* Read data and drive clock high again. */ 591 x = bus_space_read_1(bst, bsh, GP2); 592 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 593 DELAY(1); 594 595 return (x & MDIO); 596 } 597 598 /* Pulse out a sequence of data bits. */ 599 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 600 static INLINE void 601 xi_mdi_pulse_bits(sc, data, len) 602 struct xi_softc *sc; 603 u_int32_t data; 604 int len; 605 { 606 u_int32_t mask; 607 608 for (mask = 1 << (len - 1); mask; mask >>= 1) 609 xi_mdi_pulse(sc, data & mask); 610 } 611 612 /* Read a PHY register. */ 613 STATIC int 614 xi_mdi_read(self, phy, reg) 615 struct device *self; 616 int phy; 617 int reg; 618 { 619 struct xi_softc *sc = (struct xi_softc *)self; 620 int i; 621 u_int32_t mask; 622 u_int32_t data = 0; 623 624 PAGE(sc, 2); 625 for (i = 0; i < 32; i++) /* Synchronize. */ 626 xi_mdi_pulse(sc, 1); 627 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 628 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 629 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 630 xi_mdi_idle(sc); /* Turn around. */ 631 xi_mdi_probe(sc); /* Drop initial zero bit. */ 632 633 for (mask = 1 << 15; mask; mask >>= 1) { 634 if (xi_mdi_probe(sc)) 635 data |= mask; 636 } 637 xi_mdi_idle(sc); 638 639 DPRINTF(XID_MII, 640 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 641 642 return (data); 643 } 644 645 /* Write a PHY register. */ 646 STATIC void 647 xi_mdi_write(self, phy, reg, value) 648 struct device *self; 649 int phy; 650 int reg; 651 int value; 652 { 653 struct xi_softc *sc = (struct xi_softc *)self; 654 int i; 655 656 PAGE(sc, 2); 657 for (i = 0; i < 32; i++) /* Synchronize. */ 658 xi_mdi_pulse(sc, 1); 659 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 660 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 661 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 662 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 663 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 664 xi_mdi_idle(sc); /* Idle away. */ 665 666 DPRINTF(XID_MII, 667 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 668 } 669 670 STATIC void 671 xi_statchg(self) 672 struct device *self; 673 { 674 /* XXX Update ifp->if_baudrate */ 675 } 676 677 /* 678 * Change media according to request. 679 */ 680 STATIC int 681 xi_mediachange(ifp) 682 struct ifnet *ifp; 683 { 684 int s; 685 686 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 687 688 if (ifp->if_flags & IFF_UP) { 689 s = splnet(); 690 xi_init(ifp->if_softc); 691 splx(s); 692 } 693 return (0); 694 } 695 696 /* 697 * Notify the world which media we're using. 698 */ 699 STATIC void 700 xi_mediastatus(ifp, ifmr) 701 struct ifnet *ifp; 702 struct ifmediareq *ifmr; 703 { 704 struct xi_softc *sc = ifp->if_softc; 705 706 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 707 708 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 709 mii_pollstat(&sc->sc_mii); 710 ifmr->ifm_status = sc->sc_mii.mii_media_status; 711 ifmr->ifm_active = sc->sc_mii.mii_media_active; 712 } 713 } 714 715 STATIC void 716 xi_reset(sc) 717 struct xi_softc *sc; 718 { 719 int s; 720 721 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 722 723 s = splnet(); 724 xi_stop(sc); 725 xi_init(sc); 726 splx(s); 727 } 728 729 STATIC void 730 xi_watchdog(ifp) 731 struct ifnet *ifp; 732 { 733 struct xi_softc *sc = ifp->if_softc; 734 735 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 736 ++ifp->if_oerrors; 737 738 xi_reset(sc); 739 } 740 741 STATIC void 742 xi_stop(sc) 743 register struct xi_softc *sc; 744 { 745 bus_space_tag_t bst = sc->sc_bst; 746 bus_space_handle_t bsh = sc->sc_bsh; 747 748 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 749 750 PAGE(sc, 0x40); 751 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 752 753 /* Disable interrupts. */ 754 PAGE(sc, 0); 755 bus_space_write_1(bst, bsh, CR, 0); 756 757 PAGE(sc, 1); 758 bus_space_write_1(bst, bsh, IMR0, 0); 759 760 /* Cancel watchdog timer. */ 761 sc->sc_ethercom.ec_if.if_timer = 0; 762 } 763 764 STATIC int 765 xi_enable(sc) 766 struct xi_softc *sc; 767 { 768 int error; 769 770 if (!sc->sc_enabled) { 771 error = (*sc->sc_enable)(sc); 772 if (error) 773 return (error); 774 sc->sc_enabled = 1; 775 xi_full_reset(sc); 776 } 777 return (0); 778 } 779 780 STATIC void 781 xi_disable(sc) 782 struct xi_softc *sc; 783 { 784 785 if (sc->sc_enabled) { 786 sc->sc_enabled = 0; 787 (*sc->sc_disable)(sc); 788 } 789 } 790 791 STATIC void 792 xi_init(sc) 793 struct xi_softc *sc; 794 { 795 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 796 bus_space_tag_t bst = sc->sc_bst; 797 bus_space_handle_t bsh = sc->sc_bsh; 798 799 DPRINTF(XID_CONFIG, ("xi_init()\n")); 800 801 /* Setup the ethernet interrupt mask. */ 802 PAGE(sc, 1); 803 bus_space_write_1(bst, bsh, IMR0, 804 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 805 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 806 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 807 /* XXX What is this? Not for Dingo at least. */ 808 /* Unmask TX underrun detection */ 809 bus_space_write_1(bst, bsh, IMR1, 1); 810 } 811 812 /* Enable interrupts. */ 813 PAGE(sc, 0); 814 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 815 816 xi_set_address(sc); 817 818 PAGE(sc, 0x40); 819 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 820 821 PAGE(sc, 0); 822 823 /* Set current media. */ 824 mii_mediachg(&sc->sc_mii); 825 826 ifp->if_flags |= IFF_RUNNING; 827 ifp->if_flags &= ~IFF_OACTIVE; 828 829 xi_start(ifp); 830 } 831 832 /* 833 * Start outputting on the interface. 834 * Always called as splnet(). 835 */ 836 STATIC void 837 xi_start(ifp) 838 struct ifnet *ifp; 839 { 840 struct xi_softc *sc = ifp->if_softc; 841 bus_space_tag_t bst = sc->sc_bst; 842 bus_space_handle_t bsh = sc->sc_bsh; 843 unsigned int s, len, pad = 0; 844 struct mbuf *m0, *m; 845 u_int16_t space; 846 847 DPRINTF(XID_CONFIG, ("xi_start()\n")); 848 849 /* Don't transmit if interface is busy or not running. */ 850 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 851 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 852 return; 853 } 854 855 /* Peek at the next packet. */ 856 IFQ_POLL(&ifp->if_snd, m0); 857 if (m0 == 0) 858 return; 859 860 /* We need to use m->m_pkthdr.len, so require the header. */ 861 if (!(m0->m_flags & M_PKTHDR)) 862 panic("xi_start: no header mbuf"); 863 864 len = m0->m_pkthdr.len; 865 866 #if 1 867 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 868 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 869 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 870 #else 871 pad = 0; 872 #endif 873 874 PAGE(sc, 0); 875 876 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 877 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 878 if (len + pad + 2 > space) { 879 DPRINTF(XID_FIFO, 880 ("xi: not enough space in output FIFO (%d > %d)\n", 881 len + pad + 2, space)); 882 return; 883 } 884 885 IFQ_DEQUEUE(&ifp->if_snd, m0); 886 887 #if NBPFILTER > 0 888 if (ifp->if_bpf) 889 bpf_mtap(ifp->if_bpf, m0); 890 #endif 891 892 /* 893 * Do the output at splhigh() so that an interrupt from another device 894 * won't cause a FIFO underrun. 895 */ 896 s = splhigh(); 897 898 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 899 for (m = m0; m; ) { 900 if (m->m_len > 1) 901 bus_space_write_multi_2(bst, bsh, EDP, 902 mtod(m, u_int16_t *), m->m_len>>1); 903 if (m->m_len & 1) { 904 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 905 bus_space_write_1(bst, bsh, EDP, 906 *(mtod(m, u_int8_t *) + m->m_len - 1)); 907 } 908 MFREE(m, m0); 909 m = m0; 910 } 911 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 912 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 913 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 914 else { 915 for (; pad > 1; pad -= 2) 916 bus_space_write_2(bst, bsh, EDP, 0); 917 if (pad == 1) 918 bus_space_write_1(bst, bsh, EDP, 0); 919 } 920 921 splx(s); 922 923 ifp->if_timer = 5; 924 ++ifp->if_opackets; 925 } 926 927 STATIC int 928 xi_ether_ioctl(ifp, cmd, data) 929 struct ifnet *ifp; 930 u_long cmd; 931 caddr_t data; 932 { 933 struct ifaddr *ifa = (struct ifaddr *)data; 934 struct xi_softc *sc = ifp->if_softc; 935 int error; 936 937 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 938 939 switch (cmd) { 940 case SIOCSIFADDR: 941 if ((error = xi_enable(sc)) != 0) 942 break; 943 944 ifp->if_flags |= IFF_UP; 945 946 switch (ifa->ifa_addr->sa_family) { 947 #ifdef INET 948 case AF_INET: 949 xi_init(sc); 950 arp_ifinit(ifp, ifa); 951 break; 952 #endif /* INET */ 953 954 #ifdef NS 955 case AF_NS: 956 { 957 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 958 959 if (ns_nullhost(*ina)) 960 ina->x_host = *(union ns_host *) 961 LLADDR(ifp->if_sadl); 962 else 963 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 964 ifp->if_addrlen); 965 /* Set new address. */ 966 xi_init(sc); 967 break; 968 } 969 #endif /* NS */ 970 971 default: 972 xi_init(sc); 973 break; 974 } 975 break; 976 977 default: 978 return (EINVAL); 979 } 980 981 return (0); 982 } 983 984 STATIC int 985 xi_ioctl(ifp, cmd, data) 986 struct ifnet *ifp; 987 u_long cmd; 988 caddr_t data; 989 { 990 struct xi_softc *sc = ifp->if_softc; 991 struct ifreq *ifr = (struct ifreq *)data; 992 int s, error = 0; 993 994 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 995 996 s = splnet(); 997 998 switch (cmd) { 999 case SIOCSIFADDR: 1000 error = xi_ether_ioctl(ifp, cmd, data); 1001 break; 1002 1003 case SIOCSIFFLAGS: 1004 if ((ifp->if_flags & IFF_UP) == 0 && 1005 (ifp->if_flags & IFF_RUNNING) != 0) { 1006 /* 1007 * If interface is marked down and it is running, 1008 * stop it. 1009 */ 1010 xi_stop(sc); 1011 ifp->if_flags &= ~IFF_RUNNING; 1012 xi_disable(sc); 1013 } else if ((ifp->if_flags & IFF_UP) != 0 && 1014 (ifp->if_flags & IFF_RUNNING) == 0) { 1015 /* 1016 * If interface is marked up and it is stopped, 1017 * start it. 1018 */ 1019 if ((error = xi_enable(sc)) != 0) 1020 break; 1021 xi_init(sc); 1022 } else if ((ifp->if_flags & IFF_UP) != 0) { 1023 /* 1024 * Reset the interface to pick up changes in any 1025 * other flags that affect hardware registers. 1026 */ 1027 xi_set_address(sc); 1028 } 1029 break; 1030 1031 case SIOCADDMULTI: 1032 case SIOCDELMULTI: 1033 if (sc->sc_enabled == 0) { 1034 error = EIO; 1035 break; 1036 } 1037 1038 error = (cmd == SIOCADDMULTI) ? 1039 ether_addmulti(ifr, &sc->sc_ethercom) : 1040 ether_delmulti(ifr, &sc->sc_ethercom); 1041 if (error == ENETRESET) { 1042 /* 1043 * Multicast list has changed; set the hardware 1044 * filter accordingly. 1045 */ 1046 if (ifp->if_flags & IFF_RUNNING) 1047 xi_set_address(sc); 1048 error = 0; 1049 } 1050 break; 1051 1052 case SIOCSIFMEDIA: 1053 case SIOCGIFMEDIA: 1054 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1055 break; 1056 1057 default: 1058 error = EINVAL; 1059 break; 1060 } 1061 1062 splx(s); 1063 return (error); 1064 } 1065 1066 STATIC void 1067 xi_set_address(sc) 1068 struct xi_softc *sc; 1069 { 1070 bus_space_tag_t bst = sc->sc_bst; 1071 bus_space_handle_t bsh = sc->sc_bsh; 1072 struct ethercom *ether = &sc->sc_ethercom; 1073 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1074 struct ether_multistep step; 1075 struct ether_multi *enm; 1076 int page, num; 1077 int i; 1078 u_int8_t x; 1079 u_int8_t *enaddr; 1080 u_int8_t indaddr[64]; 1081 1082 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1083 1084 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 1085 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1086 for (i = 0; i < 6; i++) 1087 indaddr[i] = enaddr[5 - i]; 1088 else 1089 for (i = 0; i < 6; i++) 1090 indaddr[i] = enaddr[i]; 1091 num = 1; 1092 1093 if (ether->ec_multicnt > 9) { 1094 ifp->if_flags |= IFF_ALLMULTI; 1095 goto done; 1096 } 1097 1098 ETHER_FIRST_MULTI(step, ether, enm); 1099 for (; enm; num++) { 1100 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1101 sizeof(enm->enm_addrlo)) != 0) { 1102 /* 1103 * The multicast address is really a range; 1104 * it's easier just to accept all multicasts. 1105 * XXX should we be setting IFF_ALLMULTI here? 1106 */ 1107 ifp->if_flags |= IFF_ALLMULTI; 1108 goto done; 1109 } 1110 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1111 for (i = 0; i < 6; i++) 1112 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1113 else 1114 for (i = 0; i < 6; i++) 1115 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1116 ETHER_NEXT_MULTI(step, enm); 1117 } 1118 ifp->if_flags &= ~IFF_ALLMULTI; 1119 1120 done: 1121 if (num < 10) 1122 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1123 1124 for (page = 0; page < 8; page++) { 1125 #ifdef XIDEBUG 1126 if (xidebug & XID_MCAST) { 1127 printf("page %d before:", page); 1128 for (i = 0; i < 8; i++) 1129 printf(" %02x", indaddr[page * 8 + i]); 1130 printf("\n"); 1131 } 1132 #endif 1133 1134 PAGE(sc, 0x50 + page); 1135 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1136 page == 7 ? 4 : 8); 1137 /* 1138 * XXX 1139 * Without this delay, the address registers on my CE2 get 1140 * trashed the first and I have to cycle it. I have no idea 1141 * why. - mycroft, 2004/08/09 1142 */ 1143 DELAY(50); 1144 1145 #ifdef XIDEBUG 1146 if (xidebug & XID_MCAST) { 1147 bus_space_read_region_1(bst, bsh, IA, 1148 &indaddr[page * 8], page == 7 ? 4 : 8); 1149 printf("page %d after: ", page); 1150 for (i = 0; i < 8; i++) 1151 printf(" %02x", indaddr[page * 8 + i]); 1152 printf("\n"); 1153 } 1154 #endif 1155 } 1156 1157 PAGE(sc, 0x42); 1158 x = SWC1_IND_ADDR; 1159 if (ifp->if_flags & IFF_PROMISC) 1160 x |= SWC1_PROMISC; 1161 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1162 x |= SWC1_MCAST_PROM; 1163 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1164 x |= SWC1_AUTO_MEDIA; 1165 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1166 } 1167 1168 STATIC void 1169 xi_cycle_power(sc) 1170 struct xi_softc *sc; 1171 { 1172 bus_space_tag_t bst = sc->sc_bst; 1173 bus_space_handle_t bsh = sc->sc_bsh; 1174 1175 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1176 1177 PAGE(sc, 4); 1178 DELAY(1); 1179 bus_space_write_1(bst, bsh, GP1, 0); 1180 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1181 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1182 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1183 else 1184 /* XXX What is bit 2 (aka AIC)? */ 1185 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1186 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1187 } 1188 1189 STATIC void 1190 xi_full_reset(sc) 1191 struct xi_softc *sc; 1192 { 1193 bus_space_tag_t bst = sc->sc_bst; 1194 bus_space_handle_t bsh = sc->sc_bsh; 1195 u_int8_t x; 1196 1197 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1198 1199 /* Do an as extensive reset as possible on all functions. */ 1200 xi_cycle_power(sc); 1201 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1202 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1203 bus_space_write_1(bst, bsh, CR, 0); 1204 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1205 PAGE(sc, 4); 1206 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1207 /* 1208 * Drive GP1 low to power up ML6692 and GP2 high to power up 1209 * the 10MHz chip. XXX What chip is that? The phy? 1210 */ 1211 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1212 } 1213 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1214 1215 /* Get revision information. XXX Symbolic constants. */ 1216 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1217 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1218 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1219 1220 /* Media selection. XXX Maybe manual overriding too? */ 1221 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1222 /* 1223 * XXX I have no idea what this really does, it is from the 1224 * Linux driver. 1225 */ 1226 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1227 } 1228 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1229 1230 /* 1231 * Disable source insertion. 1232 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1233 */ 1234 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1235 PAGE(sc, 0x42); 1236 bus_space_write_1(bst, bsh, SWC0, 0x20); 1237 } 1238 1239 /* Set the local memory dividing line. */ 1240 if (sc->sc_rev != 1) { 1241 PAGE(sc, 2); 1242 /* XXX Symbolic constant preferrable. */ 1243 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1244 } 1245 1246 /* 1247 * Apparently the receive byte pointer can be bad after a reset, so 1248 * we hardwire it correctly. 1249 */ 1250 PAGE(sc, 0); 1251 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1252 1253 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1254 PAGE(sc, 0x40); 1255 bus_space_write_1(bst, bsh, RX0MSK, 1256 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1257 bus_space_write_1(bst, bsh, TX0MSK, 1258 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1259 SQE | TX_ABORT | TX_OK); 1260 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1261 /* XXX From Linux, dunno what 0xb0 means. */ 1262 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1263 bus_space_write_1(bst, bsh, RXST0, 0); 1264 bus_space_write_1(bst, bsh, TXST0, 0); 1265 bus_space_write_1(bst, bsh, TXST1, 0); 1266 1267 PAGE(sc, 2); 1268 1269 /* Enable MII function if available. */ 1270 x = 0; 1271 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1272 x |= SELECT_MII; 1273 bus_space_write_1(bst, bsh, MSR, x); 1274 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1275 1276 /* Configure the LED registers. */ 1277 /* XXX This is not good for 10base2. */ 1278 bus_space_write_1(bst, bsh, LED, 1279 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1280 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1281 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1282 1283 /* 1284 * The Linux driver says this: 1285 * We should switch back to page 0 to avoid a bug in revision 0 1286 * where regs with offset below 8 can't be read after an access 1287 * to the MAC registers. 1288 */ 1289 PAGE(sc, 0); 1290 } 1291