1 /* $NetBSD: if_xi.c,v 1.62 2007/09/01 07:32:31 dyoung Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.62 2007/09/01 07:32:31 dyoung Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 /* 100 * Maximum number of bytes to read per interrupt. Linux recommends 101 * somewhere between 2000-22000. 102 * XXX This is currently a hard maximum. 103 */ 104 #define MAX_BYTES_INTR 12000 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/pcmcia/pcmciareg.h> 110 #include <dev/pcmcia/pcmciavar.h> 111 #include <dev/pcmcia/pcmciadevs.h> 112 113 #include <dev/pcmcia/if_xireg.h> 114 #include <dev/pcmcia/if_xivar.h> 115 116 #ifdef __GNUC__ 117 #define INLINE inline 118 #else 119 #define INLINE 120 #endif /* __GNUC__ */ 121 122 #define XIDEBUG 123 #define XIDEBUG_VALUE 0 124 125 #ifdef XIDEBUG 126 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 127 128 #define XID_CONFIG 0x01 129 #define XID_MII 0x02 130 #define XID_INTR 0x04 131 #define XID_FIFO 0x08 132 #define XID_MCAST 0x10 133 134 #ifdef XIDEBUG_VALUE 135 int xidebug = XIDEBUG_VALUE; 136 #else 137 int xidebug = 0; 138 #endif 139 #else 140 #define DPRINTF(cat, x) (void)0 141 #endif 142 143 #define STATIC 144 145 STATIC int xi_enable(struct xi_softc *); 146 STATIC void xi_disable(struct xi_softc *); 147 STATIC void xi_cycle_power(struct xi_softc *); 148 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 149 STATIC void xi_full_reset(struct xi_softc *); 150 STATIC void xi_init(struct xi_softc *); 151 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 152 STATIC int xi_mdi_read(struct device *, int, int); 153 STATIC void xi_mdi_write(struct device *, int, int, int); 154 STATIC int xi_mediachange(struct ifnet *); 155 STATIC void xi_mediastatus(struct ifnet *, struct ifmediareq *); 156 STATIC u_int16_t xi_get(struct xi_softc *); 157 STATIC void xi_reset(struct xi_softc *); 158 STATIC void xi_set_address(struct xi_softc *); 159 STATIC void xi_start(struct ifnet *); 160 STATIC void xi_statchg(struct device *); 161 STATIC void xi_stop(struct xi_softc *); 162 STATIC void xi_watchdog(struct ifnet *); 163 164 void 165 xi_attach(sc, myea) 166 struct xi_softc *sc; 167 u_int8_t *myea; 168 { 169 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 170 171 #if 0 172 /* 173 * Configuration as advised by DINGO documentation. 174 * Dingo has some extra configuration registers in the CCR space. 175 */ 176 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 177 struct pcmcia_mem_handle pcmh; 178 int ccr_window; 179 bus_size_t ccr_offset; 180 181 /* get access to the DINGO CCR space */ 182 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 183 &pcmh)) { 184 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 185 goto fail; 186 } 187 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 188 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 189 &pcmh, &ccr_offset, &ccr_window)) { 190 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 191 pcmcia_mem_free(psc->sc_pf, &pcmh); 192 goto fail; 193 } 194 195 /* enable the second function - usually modem */ 196 bus_space_write_1(pcmh.memt, pcmh.memh, 197 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 198 bus_space_write_1(pcmh.memt, pcmh.memh, 199 ccr_offset + PCMCIA_CCR_DCOR1, 200 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 201 bus_space_write_1(pcmh.memt, pcmh.memh, 202 ccr_offset + PCMCIA_CCR_DCOR2, 0); 203 bus_space_write_1(pcmh.memt, pcmh.memh, 204 ccr_offset + PCMCIA_CCR_DCOR3, 0); 205 bus_space_write_1(pcmh.memt, pcmh.memh, 206 ccr_offset + PCMCIA_CCR_DCOR4, 0); 207 208 /* We don't need them anymore and can free them (I think). */ 209 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 210 pcmcia_mem_free(psc->sc_pf, &pcmh); 211 } 212 #endif 213 214 /* Reset and initialize the card. */ 215 xi_full_reset(sc); 216 217 printf("%s: MAC address %s\n", sc->sc_dev.dv_xname, ether_sprintf(myea)); 218 219 ifp = &sc->sc_ethercom.ec_if; 220 /* Initialize the ifnet structure. */ 221 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 222 ifp->if_softc = sc; 223 ifp->if_start = xi_start; 224 ifp->if_ioctl = xi_ioctl; 225 ifp->if_watchdog = xi_watchdog; 226 ifp->if_flags = 227 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 228 IFQ_SET_READY(&ifp->if_snd); 229 230 /* 802.1q capability */ 231 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 232 233 /* Attach the interface. */ 234 if_attach(ifp); 235 ether_ifattach(ifp, myea); 236 237 /* 238 * Initialize our media structures and probe the MII. 239 */ 240 sc->sc_mii.mii_ifp = ifp; 241 sc->sc_mii.mii_readreg = xi_mdi_read; 242 sc->sc_mii.mii_writereg = xi_mdi_write; 243 sc->sc_mii.mii_statchg = xi_statchg; 244 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 245 xi_mediastatus); 246 DPRINTF(XID_MII | XID_CONFIG, 247 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 248 249 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 250 MII_OFFSET_ANY, 0); 251 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 252 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 253 NULL); 254 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 255 256 #if NRND > 0 257 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, RND_TYPE_NET, 0); 258 #endif 259 } 260 261 int 262 xi_detach(struct device *self, int flags) 263 { 264 struct xi_softc *sc = (void *)self; 265 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 266 267 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 268 269 xi_disable(sc); 270 271 #if NRND > 0 272 rnd_detach_source(&sc->sc_rnd_source); 273 #endif 274 275 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 276 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 277 ether_ifdetach(ifp); 278 if_detach(ifp); 279 280 return 0; 281 } 282 283 int 284 xi_activate(self, act) 285 struct device *self; 286 enum devact act; 287 { 288 struct xi_softc *sc = (void *)self; 289 int s, rv = 0; 290 291 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 292 293 s = splnet(); 294 switch (act) { 295 case DVACT_ACTIVATE: 296 rv = EOPNOTSUPP; 297 break; 298 299 case DVACT_DEACTIVATE: 300 if_deactivate(&sc->sc_ethercom.ec_if); 301 break; 302 } 303 splx(s); 304 return (rv); 305 } 306 307 int 308 xi_intr(arg) 309 void *arg; 310 { 311 struct xi_softc *sc = arg; 312 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 313 u_int8_t esr, rsr, isr, rx_status; 314 u_int16_t tx_status, recvcount = 0, tempint; 315 316 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 317 318 if (sc->sc_enabled == 0 || 319 !device_is_active(&sc->sc_dev)) 320 return (0); 321 322 ifp->if_timer = 0; /* turn watchdog timer off */ 323 324 PAGE(sc, 0); 325 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 326 /* Disable interrupt (Linux does it). */ 327 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 328 } 329 330 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 331 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 332 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 333 334 /* Check to see if card has been ejected. */ 335 if (isr == 0xff) { 336 #ifdef DIAGNOSTIC 337 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 338 #endif 339 goto end; 340 } 341 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 342 343 PAGE(sc, 0x40); 344 rx_status = 345 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 346 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 347 tx_status = 348 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 349 tx_status |= 350 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 351 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 352 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 353 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 354 tx_status)); 355 356 PAGE(sc, 0); 357 while (esr & FULL_PKT_RCV) { 358 if (!(rsr & RSR_RX_OK)) 359 break; 360 361 /* Compare bytes read this interrupt to hard maximum. */ 362 if (recvcount > MAX_BYTES_INTR) { 363 DPRINTF(XID_INTR, 364 ("xi: too many bytes this interrupt\n")); 365 ifp->if_iqdrops++; 366 /* Drop packet. */ 367 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 368 DO_SKIP_RX_PKT); 369 } 370 tempint = xi_get(sc); /* XXX doesn't check the error! */ 371 recvcount += tempint; 372 ifp->if_ibytes += tempint; 373 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 374 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 375 } 376 377 /* Packet too long? */ 378 if (rsr & RSR_TOO_LONG) { 379 ifp->if_ierrors++; 380 DPRINTF(XID_INTR, ("xi: packet too long\n")); 381 } 382 383 /* CRC error? */ 384 if (rsr & RSR_CRCERR) { 385 ifp->if_ierrors++; 386 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 387 } 388 389 /* Alignment error? */ 390 if (rsr & RSR_ALIGNERR) { 391 ifp->if_ierrors++; 392 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 393 } 394 395 /* Check for rx overrun. */ 396 if (rx_status & RX_OVERRUN) { 397 ifp->if_ierrors++; 398 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 399 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 400 } 401 402 /* Try to start more packets transmitting. */ 403 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 404 xi_start(ifp); 405 406 /* Detected excessive collisions? */ 407 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 408 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 409 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 410 ifp->if_oerrors++; 411 } 412 413 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 414 ifp->if_oerrors++; 415 416 /* have handled the interrupt */ 417 #if NRND > 0 418 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 419 #endif 420 421 end: 422 /* Reenable interrupts. */ 423 PAGE(sc, 0); 424 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 425 426 return (1); 427 } 428 429 /* 430 * Pull a packet from the card into an mbuf chain. 431 */ 432 STATIC u_int16_t 433 xi_get(sc) 434 struct xi_softc *sc; 435 { 436 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 437 struct mbuf *top, **mp, *m; 438 u_int16_t pktlen, len, recvcount = 0; 439 u_int8_t *data; 440 441 DPRINTF(XID_CONFIG, ("xi_get()\n")); 442 443 PAGE(sc, 0); 444 pktlen = 445 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 446 447 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 448 449 if (pktlen == 0) { 450 /* 451 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 452 * when MPE is set. It is not known why. 453 */ 454 return (0); 455 } 456 457 /* XXX should this be incremented now ? */ 458 recvcount += pktlen; 459 460 MGETHDR(m, M_DONTWAIT, MT_DATA); 461 if (m == NULL) 462 return (recvcount); 463 m->m_pkthdr.rcvif = ifp; 464 m->m_pkthdr.len = pktlen; 465 len = MHLEN; 466 top = NULL; 467 mp = ⊤ 468 469 while (pktlen > 0) { 470 if (top) { 471 MGET(m, M_DONTWAIT, MT_DATA); 472 if (m == NULL) { 473 m_freem(top); 474 return (recvcount); 475 } 476 len = MLEN; 477 } 478 if (pktlen >= MINCLSIZE) { 479 MCLGET(m, M_DONTWAIT); 480 if (!(m->m_flags & M_EXT)) { 481 m_freem(m); 482 m_freem(top); 483 return (recvcount); 484 } 485 len = MCLBYTES; 486 } 487 if (top == NULL) { 488 char *newdata = (char *)ALIGN(m->m_data + 489 sizeof(struct ether_header)) - 490 sizeof(struct ether_header); 491 len -= newdata - m->m_data; 492 m->m_data = newdata; 493 } 494 len = min(pktlen, len); 495 data = mtod(m, u_int8_t *); 496 if (len > 1) { 497 len &= ~1; 498 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 499 (u_int16_t *)data, len>>1); 500 } else 501 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 502 m->m_len = len; 503 pktlen -= len; 504 *mp = m; 505 mp = &m->m_next; 506 } 507 508 /* Skip Rx packet. */ 509 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 510 511 if (top == NULL) 512 return recvcount; 513 514 /* Trim the CRC off the end of the packet. */ 515 m_adj(top, -ETHER_CRC_LEN); 516 517 ifp->if_ipackets++; 518 519 #if NBPFILTER > 0 520 if (ifp->if_bpf) 521 bpf_mtap(ifp->if_bpf, top); 522 #endif 523 524 (*ifp->if_input)(ifp, top); 525 return (recvcount); 526 } 527 528 /* 529 * Serial management for the MII. 530 * The DELAY's below stem from the fact that the maximum frequency 531 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 532 * go much faster than that. 533 */ 534 535 /* Let the MII serial management be idle for one period. */ 536 static INLINE void xi_mdi_idle(struct xi_softc *); 537 static INLINE void 538 xi_mdi_idle(sc) 539 struct xi_softc *sc; 540 { 541 bus_space_tag_t bst = sc->sc_bst; 542 bus_space_handle_t bsh = sc->sc_bsh; 543 544 /* Drive MDC low... */ 545 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 546 DELAY(1); 547 548 /* and high again. */ 549 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 550 DELAY(1); 551 } 552 553 /* Pulse out one bit of data. */ 554 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 555 static INLINE void 556 xi_mdi_pulse(sc, data) 557 struct xi_softc *sc; 558 int data; 559 { 560 bus_space_tag_t bst = sc->sc_bst; 561 bus_space_handle_t bsh = sc->sc_bsh; 562 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 563 564 /* First latch the data bit MDIO with clock bit MDC low...*/ 565 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 566 DELAY(1); 567 568 /* then raise the clock again, preserving the data bit. */ 569 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 570 DELAY(1); 571 } 572 573 /* Probe one bit of data. */ 574 static INLINE int xi_mdi_probe(struct xi_softc *sc); 575 static INLINE int 576 xi_mdi_probe(sc) 577 struct xi_softc *sc; 578 { 579 bus_space_tag_t bst = sc->sc_bst; 580 bus_space_handle_t bsh = sc->sc_bsh; 581 u_int8_t x; 582 583 /* Pull clock bit MDCK low... */ 584 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 585 DELAY(1); 586 587 /* Read data and drive clock high again. */ 588 x = bus_space_read_1(bst, bsh, GP2); 589 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 590 DELAY(1); 591 592 return (x & MDIO); 593 } 594 595 /* Pulse out a sequence of data bits. */ 596 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 597 static INLINE void 598 xi_mdi_pulse_bits(sc, data, len) 599 struct xi_softc *sc; 600 u_int32_t data; 601 int len; 602 { 603 u_int32_t mask; 604 605 for (mask = 1 << (len - 1); mask; mask >>= 1) 606 xi_mdi_pulse(sc, data & mask); 607 } 608 609 /* Read a PHY register. */ 610 STATIC int 611 xi_mdi_read(self, phy, reg) 612 struct device *self; 613 int phy; 614 int reg; 615 { 616 struct xi_softc *sc = (struct xi_softc *)self; 617 int i; 618 u_int32_t mask; 619 u_int32_t data = 0; 620 621 PAGE(sc, 2); 622 for (i = 0; i < 32; i++) /* Synchronize. */ 623 xi_mdi_pulse(sc, 1); 624 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 625 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 626 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 627 xi_mdi_idle(sc); /* Turn around. */ 628 xi_mdi_probe(sc); /* Drop initial zero bit. */ 629 630 for (mask = 1 << 15; mask; mask >>= 1) { 631 if (xi_mdi_probe(sc)) 632 data |= mask; 633 } 634 xi_mdi_idle(sc); 635 636 DPRINTF(XID_MII, 637 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 638 639 return (data); 640 } 641 642 /* Write a PHY register. */ 643 STATIC void 644 xi_mdi_write(self, phy, reg, value) 645 struct device *self; 646 int phy; 647 int reg; 648 int value; 649 { 650 struct xi_softc *sc = (struct xi_softc *)self; 651 int i; 652 653 PAGE(sc, 2); 654 for (i = 0; i < 32; i++) /* Synchronize. */ 655 xi_mdi_pulse(sc, 1); 656 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 657 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 658 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 659 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 660 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 661 xi_mdi_idle(sc); /* Idle away. */ 662 663 DPRINTF(XID_MII, 664 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 665 } 666 667 STATIC void 668 xi_statchg(struct device *self) 669 { 670 /* XXX Update ifp->if_baudrate */ 671 } 672 673 /* 674 * Change media according to request. 675 */ 676 STATIC int 677 xi_mediachange(ifp) 678 struct ifnet *ifp; 679 { 680 int s; 681 682 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 683 684 if (ifp->if_flags & IFF_UP) { 685 s = splnet(); 686 xi_init(ifp->if_softc); 687 splx(s); 688 } 689 return (0); 690 } 691 692 /* 693 * Notify the world which media we're using. 694 */ 695 STATIC void 696 xi_mediastatus(ifp, ifmr) 697 struct ifnet *ifp; 698 struct ifmediareq *ifmr; 699 { 700 struct xi_softc *sc = ifp->if_softc; 701 702 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 703 704 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 705 mii_pollstat(&sc->sc_mii); 706 ifmr->ifm_status = sc->sc_mii.mii_media_status; 707 ifmr->ifm_active = sc->sc_mii.mii_media_active; 708 } 709 } 710 711 STATIC void 712 xi_reset(sc) 713 struct xi_softc *sc; 714 { 715 int s; 716 717 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 718 719 s = splnet(); 720 xi_stop(sc); 721 xi_init(sc); 722 splx(s); 723 } 724 725 STATIC void 726 xi_watchdog(ifp) 727 struct ifnet *ifp; 728 { 729 struct xi_softc *sc = ifp->if_softc; 730 731 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 732 ++ifp->if_oerrors; 733 734 xi_reset(sc); 735 } 736 737 STATIC void 738 xi_stop(sc) 739 register struct xi_softc *sc; 740 { 741 bus_space_tag_t bst = sc->sc_bst; 742 bus_space_handle_t bsh = sc->sc_bsh; 743 744 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 745 746 PAGE(sc, 0x40); 747 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 748 749 /* Disable interrupts. */ 750 PAGE(sc, 0); 751 bus_space_write_1(bst, bsh, CR, 0); 752 753 PAGE(sc, 1); 754 bus_space_write_1(bst, bsh, IMR0, 0); 755 756 /* Cancel watchdog timer. */ 757 sc->sc_ethercom.ec_if.if_timer = 0; 758 } 759 760 STATIC int 761 xi_enable(sc) 762 struct xi_softc *sc; 763 { 764 int error; 765 766 if (!sc->sc_enabled) { 767 error = (*sc->sc_enable)(sc); 768 if (error) 769 return (error); 770 sc->sc_enabled = 1; 771 xi_full_reset(sc); 772 } 773 return (0); 774 } 775 776 STATIC void 777 xi_disable(sc) 778 struct xi_softc *sc; 779 { 780 781 if (sc->sc_enabled) { 782 sc->sc_enabled = 0; 783 (*sc->sc_disable)(sc); 784 } 785 } 786 787 STATIC void 788 xi_init(sc) 789 struct xi_softc *sc; 790 { 791 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 792 bus_space_tag_t bst = sc->sc_bst; 793 bus_space_handle_t bsh = sc->sc_bsh; 794 795 DPRINTF(XID_CONFIG, ("xi_init()\n")); 796 797 /* Setup the ethernet interrupt mask. */ 798 PAGE(sc, 1); 799 bus_space_write_1(bst, bsh, IMR0, 800 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 801 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 802 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 803 /* XXX What is this? Not for Dingo at least. */ 804 /* Unmask TX underrun detection */ 805 bus_space_write_1(bst, bsh, IMR1, 1); 806 } 807 808 /* Enable interrupts. */ 809 PAGE(sc, 0); 810 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 811 812 xi_set_address(sc); 813 814 PAGE(sc, 0x40); 815 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 816 817 PAGE(sc, 0); 818 819 /* Set current media. */ 820 mii_mediachg(&sc->sc_mii); 821 822 ifp->if_flags |= IFF_RUNNING; 823 ifp->if_flags &= ~IFF_OACTIVE; 824 825 xi_start(ifp); 826 } 827 828 /* 829 * Start outputting on the interface. 830 * Always called as splnet(). 831 */ 832 STATIC void 833 xi_start(ifp) 834 struct ifnet *ifp; 835 { 836 struct xi_softc *sc = ifp->if_softc; 837 bus_space_tag_t bst = sc->sc_bst; 838 bus_space_handle_t bsh = sc->sc_bsh; 839 unsigned int s, len, pad = 0; 840 struct mbuf *m0, *m; 841 u_int16_t space; 842 843 DPRINTF(XID_CONFIG, ("xi_start()\n")); 844 845 /* Don't transmit if interface is busy or not running. */ 846 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 847 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 848 return; 849 } 850 851 /* Peek at the next packet. */ 852 IFQ_POLL(&ifp->if_snd, m0); 853 if (m0 == 0) 854 return; 855 856 /* We need to use m->m_pkthdr.len, so require the header. */ 857 if (!(m0->m_flags & M_PKTHDR)) 858 panic("xi_start: no header mbuf"); 859 860 len = m0->m_pkthdr.len; 861 862 #if 1 863 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 864 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 865 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 866 #else 867 pad = 0; 868 #endif 869 870 PAGE(sc, 0); 871 872 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 873 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 874 if (len + pad + 2 > space) { 875 DPRINTF(XID_FIFO, 876 ("xi: not enough space in output FIFO (%d > %d)\n", 877 len + pad + 2, space)); 878 return; 879 } 880 881 IFQ_DEQUEUE(&ifp->if_snd, m0); 882 883 #if NBPFILTER > 0 884 if (ifp->if_bpf) 885 bpf_mtap(ifp->if_bpf, m0); 886 #endif 887 888 /* 889 * Do the output at splhigh() so that an interrupt from another device 890 * won't cause a FIFO underrun. 891 */ 892 s = splhigh(); 893 894 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 895 for (m = m0; m; ) { 896 if (m->m_len > 1) 897 bus_space_write_multi_2(bst, bsh, EDP, 898 mtod(m, u_int16_t *), m->m_len>>1); 899 if (m->m_len & 1) { 900 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 901 bus_space_write_1(bst, bsh, EDP, 902 *(mtod(m, u_int8_t *) + m->m_len - 1)); 903 } 904 MFREE(m, m0); 905 m = m0; 906 } 907 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 908 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 909 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 910 else { 911 for (; pad > 1; pad -= 2) 912 bus_space_write_2(bst, bsh, EDP, 0); 913 if (pad == 1) 914 bus_space_write_1(bst, bsh, EDP, 0); 915 } 916 917 splx(s); 918 919 ifp->if_timer = 5; 920 ++ifp->if_opackets; 921 } 922 923 STATIC int 924 xi_ether_ioctl(ifp, cmd, data) 925 struct ifnet *ifp; 926 u_long cmd; 927 void *data; 928 { 929 struct ifaddr *ifa = (struct ifaddr *)data; 930 struct xi_softc *sc = ifp->if_softc; 931 int error; 932 933 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 934 935 switch (cmd) { 936 case SIOCSIFADDR: 937 if ((error = xi_enable(sc)) != 0) 938 break; 939 940 ifp->if_flags |= IFF_UP; 941 942 switch (ifa->ifa_addr->sa_family) { 943 #ifdef INET 944 case AF_INET: 945 xi_init(sc); 946 arp_ifinit(ifp, ifa); 947 break; 948 #endif /* INET */ 949 950 951 default: 952 xi_init(sc); 953 break; 954 } 955 break; 956 957 default: 958 return (EINVAL); 959 } 960 961 return (0); 962 } 963 964 STATIC int 965 xi_ioctl(ifp, cmd, data) 966 struct ifnet *ifp; 967 u_long cmd; 968 void *data; 969 { 970 struct xi_softc *sc = ifp->if_softc; 971 struct ifreq *ifr = (struct ifreq *)data; 972 int s, error = 0; 973 974 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 975 976 s = splnet(); 977 978 switch (cmd) { 979 case SIOCSIFADDR: 980 error = xi_ether_ioctl(ifp, cmd, data); 981 break; 982 983 case SIOCSIFFLAGS: 984 if ((ifp->if_flags & IFF_UP) == 0 && 985 (ifp->if_flags & IFF_RUNNING) != 0) { 986 /* 987 * If interface is marked down and it is running, 988 * stop it. 989 */ 990 xi_stop(sc); 991 ifp->if_flags &= ~IFF_RUNNING; 992 xi_disable(sc); 993 } else if ((ifp->if_flags & IFF_UP) != 0 && 994 (ifp->if_flags & IFF_RUNNING) == 0) { 995 /* 996 * If interface is marked up and it is stopped, 997 * start it. 998 */ 999 if ((error = xi_enable(sc)) != 0) 1000 break; 1001 xi_init(sc); 1002 } else if ((ifp->if_flags & IFF_UP) != 0) { 1003 /* 1004 * Reset the interface to pick up changes in any 1005 * other flags that affect hardware registers. 1006 */ 1007 xi_set_address(sc); 1008 } 1009 break; 1010 1011 case SIOCADDMULTI: 1012 case SIOCDELMULTI: 1013 if (sc->sc_enabled == 0) { 1014 error = EIO; 1015 break; 1016 } 1017 1018 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1019 /* 1020 * Multicast list has changed; set the hardware 1021 * filter accordingly. 1022 */ 1023 if (ifp->if_flags & IFF_RUNNING) 1024 xi_set_address(sc); 1025 error = 0; 1026 } 1027 break; 1028 1029 case SIOCSIFMEDIA: 1030 case SIOCGIFMEDIA: 1031 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1032 break; 1033 1034 default: 1035 error = EINVAL; 1036 break; 1037 } 1038 1039 splx(s); 1040 return (error); 1041 } 1042 1043 STATIC void 1044 xi_set_address(sc) 1045 struct xi_softc *sc; 1046 { 1047 bus_space_tag_t bst = sc->sc_bst; 1048 bus_space_handle_t bsh = sc->sc_bsh; 1049 struct ethercom *ether = &sc->sc_ethercom; 1050 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1051 struct ether_multistep step; 1052 struct ether_multi *enm; 1053 int page, num; 1054 int i; 1055 u_int8_t x; 1056 const u_int8_t *enaddr; 1057 u_int8_t indaddr[64]; 1058 1059 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1060 1061 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 1062 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1063 for (i = 0; i < 6; i++) 1064 indaddr[i] = enaddr[5 - i]; 1065 else 1066 for (i = 0; i < 6; i++) 1067 indaddr[i] = enaddr[i]; 1068 num = 1; 1069 1070 if (ether->ec_multicnt > 9) { 1071 ifp->if_flags |= IFF_ALLMULTI; 1072 goto done; 1073 } 1074 1075 ETHER_FIRST_MULTI(step, ether, enm); 1076 for (; enm; num++) { 1077 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1078 sizeof(enm->enm_addrlo)) != 0) { 1079 /* 1080 * The multicast address is really a range; 1081 * it's easier just to accept all multicasts. 1082 * XXX should we be setting IFF_ALLMULTI here? 1083 */ 1084 ifp->if_flags |= IFF_ALLMULTI; 1085 goto done; 1086 } 1087 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1088 for (i = 0; i < 6; i++) 1089 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1090 else 1091 for (i = 0; i < 6; i++) 1092 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1093 ETHER_NEXT_MULTI(step, enm); 1094 } 1095 ifp->if_flags &= ~IFF_ALLMULTI; 1096 1097 done: 1098 if (num < 10) 1099 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1100 1101 for (page = 0; page < 8; page++) { 1102 #ifdef XIDEBUG 1103 if (xidebug & XID_MCAST) { 1104 printf("page %d before:", page); 1105 for (i = 0; i < 8; i++) 1106 printf(" %02x", indaddr[page * 8 + i]); 1107 printf("\n"); 1108 } 1109 #endif 1110 1111 PAGE(sc, 0x50 + page); 1112 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1113 page == 7 ? 4 : 8); 1114 /* 1115 * XXX 1116 * Without this delay, the address registers on my CE2 get 1117 * trashed the first and I have to cycle it. I have no idea 1118 * why. - mycroft, 2004/08/09 1119 */ 1120 DELAY(50); 1121 1122 #ifdef XIDEBUG 1123 if (xidebug & XID_MCAST) { 1124 bus_space_read_region_1(bst, bsh, IA, 1125 &indaddr[page * 8], page == 7 ? 4 : 8); 1126 printf("page %d after: ", page); 1127 for (i = 0; i < 8; i++) 1128 printf(" %02x", indaddr[page * 8 + i]); 1129 printf("\n"); 1130 } 1131 #endif 1132 } 1133 1134 PAGE(sc, 0x42); 1135 x = SWC1_IND_ADDR; 1136 if (ifp->if_flags & IFF_PROMISC) 1137 x |= SWC1_PROMISC; 1138 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1139 x |= SWC1_MCAST_PROM; 1140 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1141 x |= SWC1_AUTO_MEDIA; 1142 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1143 } 1144 1145 STATIC void 1146 xi_cycle_power(sc) 1147 struct xi_softc *sc; 1148 { 1149 bus_space_tag_t bst = sc->sc_bst; 1150 bus_space_handle_t bsh = sc->sc_bsh; 1151 1152 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1153 1154 PAGE(sc, 4); 1155 DELAY(1); 1156 bus_space_write_1(bst, bsh, GP1, 0); 1157 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1158 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1159 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1160 else 1161 /* XXX What is bit 2 (aka AIC)? */ 1162 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1163 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1164 } 1165 1166 STATIC void 1167 xi_full_reset(sc) 1168 struct xi_softc *sc; 1169 { 1170 bus_space_tag_t bst = sc->sc_bst; 1171 bus_space_handle_t bsh = sc->sc_bsh; 1172 u_int8_t x; 1173 1174 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1175 1176 /* Do an as extensive reset as possible on all functions. */ 1177 xi_cycle_power(sc); 1178 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1179 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1180 bus_space_write_1(bst, bsh, CR, 0); 1181 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1182 PAGE(sc, 4); 1183 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1184 /* 1185 * Drive GP1 low to power up ML6692 and GP2 high to power up 1186 * the 10MHz chip. XXX What chip is that? The phy? 1187 */ 1188 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1189 } 1190 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1191 1192 /* Get revision information. XXX Symbolic constants. */ 1193 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1194 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1195 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1196 1197 /* Media selection. XXX Maybe manual overriding too? */ 1198 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1199 /* 1200 * XXX I have no idea what this really does, it is from the 1201 * Linux driver. 1202 */ 1203 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1204 } 1205 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1206 1207 /* 1208 * Disable source insertion. 1209 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1210 */ 1211 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1212 PAGE(sc, 0x42); 1213 bus_space_write_1(bst, bsh, SWC0, 0x20); 1214 } 1215 1216 /* Set the local memory dividing line. */ 1217 if (sc->sc_rev != 1) { 1218 PAGE(sc, 2); 1219 /* XXX Symbolic constant preferrable. */ 1220 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1221 } 1222 1223 /* 1224 * Apparently the receive byte pointer can be bad after a reset, so 1225 * we hardwire it correctly. 1226 */ 1227 PAGE(sc, 0); 1228 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1229 1230 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1231 PAGE(sc, 0x40); 1232 bus_space_write_1(bst, bsh, RX0MSK, 1233 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1234 bus_space_write_1(bst, bsh, TX0MSK, 1235 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1236 SQE | TX_ABORT | TX_OK); 1237 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1238 /* XXX From Linux, dunno what 0xb0 means. */ 1239 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1240 bus_space_write_1(bst, bsh, RXST0, 0); 1241 bus_space_write_1(bst, bsh, TXST0, 0); 1242 bus_space_write_1(bst, bsh, TXST1, 0); 1243 1244 PAGE(sc, 2); 1245 1246 /* Enable MII function if available. */ 1247 x = 0; 1248 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1249 x |= SELECT_MII; 1250 bus_space_write_1(bst, bsh, MSR, x); 1251 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1252 1253 /* Configure the LED registers. */ 1254 /* XXX This is not good for 10base2. */ 1255 bus_space_write_1(bst, bsh, LED, 1256 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1257 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1258 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1259 1260 /* 1261 * The Linux driver says this: 1262 * We should switch back to page 0 to avoid a bug in revision 0 1263 * where regs with offset below 8 can't be read after an access 1264 * to the MAC registers. 1265 */ 1266 PAGE(sc, 0); 1267 } 1268