1 /* $NetBSD: if_xi.c,v 1.70 2010/01/19 22:07:43 pooka Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.70 2010/01/19 22:07:43 pooka Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/device.h> 66 #include <sys/ioctl.h> 67 #include <sys/mbuf.h> 68 #include <sys/malloc.h> 69 #include <sys/socket.h> 70 #include <sys/kernel.h> 71 #include <sys/proc.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_ether.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef IPX 88 #include <netipx/ipx.h> 89 #include <netipx/ipx_if.h> 90 #endif 91 92 93 #include <net/bpf.h> 94 #include <net/bpfdesc.h> 95 96 /* 97 * Maximum number of bytes to read per interrupt. Linux recommends 98 * somewhere between 2000-22000. 99 * XXX This is currently a hard maximum. 100 */ 101 #define MAX_BYTES_INTR 12000 102 103 #include <dev/mii/mii.h> 104 #include <dev/mii/miivar.h> 105 106 #include <dev/pcmcia/pcmciareg.h> 107 #include <dev/pcmcia/pcmciavar.h> 108 #include <dev/pcmcia/pcmciadevs.h> 109 110 #include <dev/pcmcia/if_xireg.h> 111 #include <dev/pcmcia/if_xivar.h> 112 113 #ifdef __GNUC__ 114 #define INLINE inline 115 #else 116 #define INLINE 117 #endif /* __GNUC__ */ 118 119 #define XIDEBUG 120 #define XIDEBUG_VALUE 0 121 122 #ifdef XIDEBUG 123 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 124 125 #define XID_CONFIG 0x01 126 #define XID_MII 0x02 127 #define XID_INTR 0x04 128 #define XID_FIFO 0x08 129 #define XID_MCAST 0x10 130 131 #ifdef XIDEBUG_VALUE 132 int xidebug = XIDEBUG_VALUE; 133 #else 134 int xidebug = 0; 135 #endif 136 #else 137 #define DPRINTF(cat, x) (void)0 138 #endif 139 140 #define STATIC 141 142 STATIC int xi_enable(struct xi_softc *); 143 STATIC void xi_disable(struct xi_softc *); 144 STATIC void xi_cycle_power(struct xi_softc *); 145 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 146 STATIC void xi_full_reset(struct xi_softc *); 147 STATIC void xi_init(struct xi_softc *); 148 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 149 STATIC int xi_mdi_read(device_t, int, int); 150 STATIC void xi_mdi_write(device_t, int, int, int); 151 STATIC int xi_mediachange(struct ifnet *); 152 STATIC u_int16_t xi_get(struct xi_softc *); 153 STATIC void xi_reset(struct xi_softc *); 154 STATIC void xi_set_address(struct xi_softc *); 155 STATIC void xi_start(struct ifnet *); 156 STATIC void xi_statchg(device_t); 157 STATIC void xi_stop(struct xi_softc *); 158 STATIC void xi_watchdog(struct ifnet *); 159 160 void 161 xi_attach(struct xi_softc *sc, u_int8_t *myea) 162 { 163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 164 165 #if 0 166 /* 167 * Configuration as advised by DINGO documentation. 168 * Dingo has some extra configuration registers in the CCR space. 169 */ 170 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 171 struct pcmcia_mem_handle pcmh; 172 int ccr_window; 173 bus_size_t ccr_offset; 174 175 /* get access to the DINGO CCR space */ 176 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 177 &pcmh)) { 178 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 179 goto fail; 180 } 181 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 182 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 183 &pcmh, &ccr_offset, &ccr_window)) { 184 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 185 pcmcia_mem_free(psc->sc_pf, &pcmh); 186 goto fail; 187 } 188 189 /* enable the second function - usually modem */ 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR1, 194 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 195 bus_space_write_1(pcmh.memt, pcmh.memh, 196 ccr_offset + PCMCIA_CCR_DCOR2, 0); 197 bus_space_write_1(pcmh.memt, pcmh.memh, 198 ccr_offset + PCMCIA_CCR_DCOR3, 0); 199 bus_space_write_1(pcmh.memt, pcmh.memh, 200 ccr_offset + PCMCIA_CCR_DCOR4, 0); 201 202 /* We don't need them anymore and can free them (I think). */ 203 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 204 pcmcia_mem_free(psc->sc_pf, &pcmh); 205 } 206 #endif 207 208 /* Reset and initialize the card. */ 209 xi_full_reset(sc); 210 211 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 212 213 ifp = &sc->sc_ethercom.ec_if; 214 /* Initialize the ifnet structure. */ 215 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 216 ifp->if_softc = sc; 217 ifp->if_start = xi_start; 218 ifp->if_ioctl = xi_ioctl; 219 ifp->if_watchdog = xi_watchdog; 220 ifp->if_flags = 221 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 222 IFQ_SET_READY(&ifp->if_snd); 223 224 /* 802.1q capability */ 225 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 226 227 /* Attach the interface. */ 228 if_attach(ifp); 229 ether_ifattach(ifp, myea); 230 231 /* 232 * Initialize our media structures and probe the MII. 233 */ 234 sc->sc_mii.mii_ifp = ifp; 235 sc->sc_mii.mii_readreg = xi_mdi_read; 236 sc->sc_mii.mii_writereg = xi_mdi_write; 237 sc->sc_mii.mii_statchg = xi_statchg; 238 sc->sc_ethercom.ec_mii = &sc->sc_mii; 239 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 240 ether_mediastatus); 241 DPRINTF(XID_MII | XID_CONFIG, 242 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 243 244 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 245 MII_OFFSET_ANY, 0); 246 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 247 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 248 NULL); 249 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 250 251 #if NRND > 0 252 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), RND_TYPE_NET, 0); 253 #endif 254 } 255 256 int 257 xi_detach(device_t self, int flags) 258 { 259 struct xi_softc *sc = device_private(self); 260 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 261 262 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 263 264 xi_disable(sc); 265 266 #if NRND > 0 267 rnd_detach_source(&sc->sc_rnd_source); 268 #endif 269 270 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 271 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 272 ether_ifdetach(ifp); 273 if_detach(ifp); 274 275 return 0; 276 } 277 278 int 279 xi_intr(void *arg) 280 { 281 struct xi_softc *sc = arg; 282 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 283 u_int8_t esr, rsr, isr, rx_status; 284 u_int16_t tx_status, recvcount = 0, tempint; 285 286 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 287 288 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 289 return (0); 290 291 ifp->if_timer = 0; /* turn watchdog timer off */ 292 293 PAGE(sc, 0); 294 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 295 /* Disable interrupt (Linux does it). */ 296 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 297 } 298 299 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 300 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 301 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 302 303 /* Check to see if card has been ejected. */ 304 if (isr == 0xff) { 305 #ifdef DIAGNOSTIC 306 printf("%s: interrupt for dead card\n", 307 device_xname(sc->sc_dev)); 308 #endif 309 goto end; 310 } 311 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 312 313 PAGE(sc, 0x40); 314 rx_status = 315 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 316 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 317 tx_status = 318 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 319 tx_status |= 320 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 321 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 322 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 323 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 324 tx_status)); 325 326 PAGE(sc, 0); 327 while (esr & FULL_PKT_RCV) { 328 if (!(rsr & RSR_RX_OK)) 329 break; 330 331 /* Compare bytes read this interrupt to hard maximum. */ 332 if (recvcount > MAX_BYTES_INTR) { 333 DPRINTF(XID_INTR, 334 ("xi: too many bytes this interrupt\n")); 335 ifp->if_iqdrops++; 336 /* Drop packet. */ 337 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 338 DO_SKIP_RX_PKT); 339 } 340 tempint = xi_get(sc); /* XXX doesn't check the error! */ 341 recvcount += tempint; 342 ifp->if_ibytes += tempint; 343 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 344 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 345 } 346 347 /* Packet too long? */ 348 if (rsr & RSR_TOO_LONG) { 349 ifp->if_ierrors++; 350 DPRINTF(XID_INTR, ("xi: packet too long\n")); 351 } 352 353 /* CRC error? */ 354 if (rsr & RSR_CRCERR) { 355 ifp->if_ierrors++; 356 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 357 } 358 359 /* Alignment error? */ 360 if (rsr & RSR_ALIGNERR) { 361 ifp->if_ierrors++; 362 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 363 } 364 365 /* Check for rx overrun. */ 366 if (rx_status & RX_OVERRUN) { 367 ifp->if_ierrors++; 368 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 369 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 370 } 371 372 /* Try to start more packets transmitting. */ 373 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 374 xi_start(ifp); 375 376 /* Detected excessive collisions? */ 377 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 378 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 379 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 380 ifp->if_oerrors++; 381 } 382 383 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 384 ifp->if_oerrors++; 385 386 /* have handled the interrupt */ 387 #if NRND > 0 388 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 389 #endif 390 391 end: 392 /* Reenable interrupts. */ 393 PAGE(sc, 0); 394 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 395 396 return (1); 397 } 398 399 /* 400 * Pull a packet from the card into an mbuf chain. 401 */ 402 STATIC u_int16_t 403 xi_get(struct xi_softc *sc) 404 { 405 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 406 struct mbuf *top, **mp, *m; 407 u_int16_t pktlen, len, recvcount = 0; 408 u_int8_t *data; 409 410 DPRINTF(XID_CONFIG, ("xi_get()\n")); 411 412 PAGE(sc, 0); 413 pktlen = 414 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 415 416 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 417 418 if (pktlen == 0) { 419 /* 420 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 421 * when MPE is set. It is not known why. 422 */ 423 return (0); 424 } 425 426 /* XXX should this be incremented now ? */ 427 recvcount += pktlen; 428 429 MGETHDR(m, M_DONTWAIT, MT_DATA); 430 if (m == NULL) 431 return (recvcount); 432 m->m_pkthdr.rcvif = ifp; 433 m->m_pkthdr.len = pktlen; 434 len = MHLEN; 435 top = NULL; 436 mp = ⊤ 437 438 while (pktlen > 0) { 439 if (top) { 440 MGET(m, M_DONTWAIT, MT_DATA); 441 if (m == NULL) { 442 m_freem(top); 443 return (recvcount); 444 } 445 len = MLEN; 446 } 447 if (pktlen >= MINCLSIZE) { 448 MCLGET(m, M_DONTWAIT); 449 if (!(m->m_flags & M_EXT)) { 450 m_freem(m); 451 m_freem(top); 452 return (recvcount); 453 } 454 len = MCLBYTES; 455 } 456 if (top == NULL) { 457 char *newdata = (char *)ALIGN(m->m_data + 458 sizeof(struct ether_header)) - 459 sizeof(struct ether_header); 460 len -= newdata - m->m_data; 461 m->m_data = newdata; 462 } 463 len = min(pktlen, len); 464 data = mtod(m, u_int8_t *); 465 if (len > 1) { 466 len &= ~1; 467 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 468 (u_int16_t *)data, len>>1); 469 } else 470 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 471 m->m_len = len; 472 pktlen -= len; 473 *mp = m; 474 mp = &m->m_next; 475 } 476 477 /* Skip Rx packet. */ 478 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 479 480 if (top == NULL) 481 return recvcount; 482 483 /* Trim the CRC off the end of the packet. */ 484 m_adj(top, -ETHER_CRC_LEN); 485 486 ifp->if_ipackets++; 487 488 if (ifp->if_bpf) 489 bpf_ops->bpf_mtap(ifp->if_bpf, top); 490 491 (*ifp->if_input)(ifp, top); 492 return (recvcount); 493 } 494 495 /* 496 * Serial management for the MII. 497 * The DELAY's below stem from the fact that the maximum frequency 498 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 499 * go much faster than that. 500 */ 501 502 /* Let the MII serial management be idle for one period. */ 503 static INLINE void xi_mdi_idle(struct xi_softc *); 504 static INLINE void 505 xi_mdi_idle(struct xi_softc *sc) 506 { 507 bus_space_tag_t bst = sc->sc_bst; 508 bus_space_handle_t bsh = sc->sc_bsh; 509 510 /* Drive MDC low... */ 511 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 512 DELAY(1); 513 514 /* and high again. */ 515 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 516 DELAY(1); 517 } 518 519 /* Pulse out one bit of data. */ 520 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 521 static INLINE void 522 xi_mdi_pulse(struct xi_softc *sc, int data) 523 { 524 bus_space_tag_t bst = sc->sc_bst; 525 bus_space_handle_t bsh = sc->sc_bsh; 526 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 527 528 /* First latch the data bit MDIO with clock bit MDC low...*/ 529 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 530 DELAY(1); 531 532 /* then raise the clock again, preserving the data bit. */ 533 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 534 DELAY(1); 535 } 536 537 /* Probe one bit of data. */ 538 static INLINE int xi_mdi_probe(struct xi_softc *sc); 539 static INLINE int 540 xi_mdi_probe(struct xi_softc *sc) 541 { 542 bus_space_tag_t bst = sc->sc_bst; 543 bus_space_handle_t bsh = sc->sc_bsh; 544 u_int8_t x; 545 546 /* Pull clock bit MDCK low... */ 547 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 548 DELAY(1); 549 550 /* Read data and drive clock high again. */ 551 x = bus_space_read_1(bst, bsh, GP2); 552 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 553 DELAY(1); 554 555 return (x & MDIO); 556 } 557 558 /* Pulse out a sequence of data bits. */ 559 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 560 static INLINE void 561 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 562 { 563 u_int32_t mask; 564 565 for (mask = 1 << (len - 1); mask; mask >>= 1) 566 xi_mdi_pulse(sc, data & mask); 567 } 568 569 /* Read a PHY register. */ 570 STATIC int 571 xi_mdi_read(device_t self, int phy, int reg) 572 { 573 struct xi_softc *sc = device_private(self); 574 int i; 575 u_int32_t mask; 576 u_int32_t data = 0; 577 578 PAGE(sc, 2); 579 for (i = 0; i < 32; i++) /* Synchronize. */ 580 xi_mdi_pulse(sc, 1); 581 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 582 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 583 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 584 xi_mdi_idle(sc); /* Turn around. */ 585 xi_mdi_probe(sc); /* Drop initial zero bit. */ 586 587 for (mask = 1 << 15; mask; mask >>= 1) { 588 if (xi_mdi_probe(sc)) 589 data |= mask; 590 } 591 xi_mdi_idle(sc); 592 593 DPRINTF(XID_MII, 594 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 595 596 return (data); 597 } 598 599 /* Write a PHY register. */ 600 STATIC void 601 xi_mdi_write(device_t self, int phy, int reg, int value) 602 { 603 struct xi_softc *sc = device_private(self); 604 int i; 605 606 PAGE(sc, 2); 607 for (i = 0; i < 32; i++) /* Synchronize. */ 608 xi_mdi_pulse(sc, 1); 609 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 610 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 611 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 612 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 613 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 614 xi_mdi_idle(sc); /* Idle away. */ 615 616 DPRINTF(XID_MII, 617 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 618 } 619 620 STATIC void 621 xi_statchg(device_t self) 622 { 623 /* XXX Update ifp->if_baudrate */ 624 } 625 626 /* 627 * Change media according to request. 628 */ 629 STATIC int 630 xi_mediachange(struct ifnet *ifp) 631 { 632 int s; 633 634 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 635 636 if (ifp->if_flags & IFF_UP) { 637 s = splnet(); 638 xi_init(ifp->if_softc); 639 splx(s); 640 } 641 return (0); 642 } 643 644 STATIC void 645 xi_reset(struct xi_softc *sc) 646 { 647 int s; 648 649 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 650 651 s = splnet(); 652 xi_stop(sc); 653 xi_init(sc); 654 splx(s); 655 } 656 657 STATIC void 658 xi_watchdog(struct ifnet *ifp) 659 { 660 struct xi_softc *sc = ifp->if_softc; 661 662 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 663 ++ifp->if_oerrors; 664 665 xi_reset(sc); 666 } 667 668 STATIC void 669 xi_stop(register struct xi_softc *sc) 670 { 671 bus_space_tag_t bst = sc->sc_bst; 672 bus_space_handle_t bsh = sc->sc_bsh; 673 674 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 675 676 PAGE(sc, 0x40); 677 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 678 679 /* Disable interrupts. */ 680 PAGE(sc, 0); 681 bus_space_write_1(bst, bsh, CR, 0); 682 683 PAGE(sc, 1); 684 bus_space_write_1(bst, bsh, IMR0, 0); 685 686 /* Cancel watchdog timer. */ 687 sc->sc_ethercom.ec_if.if_timer = 0; 688 } 689 690 STATIC int 691 xi_enable(struct xi_softc *sc) 692 { 693 int error; 694 695 if (!sc->sc_enabled) { 696 error = (*sc->sc_enable)(sc); 697 if (error) 698 return (error); 699 sc->sc_enabled = 1; 700 xi_full_reset(sc); 701 } 702 return (0); 703 } 704 705 STATIC void 706 xi_disable(struct xi_softc *sc) 707 { 708 709 if (sc->sc_enabled) { 710 sc->sc_enabled = 0; 711 (*sc->sc_disable)(sc); 712 } 713 } 714 715 STATIC void 716 xi_init(struct xi_softc *sc) 717 { 718 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 719 bus_space_tag_t bst = sc->sc_bst; 720 bus_space_handle_t bsh = sc->sc_bsh; 721 722 DPRINTF(XID_CONFIG, ("xi_init()\n")); 723 724 /* Setup the ethernet interrupt mask. */ 725 PAGE(sc, 1); 726 bus_space_write_1(bst, bsh, IMR0, 727 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 728 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 729 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 730 /* XXX What is this? Not for Dingo at least. */ 731 /* Unmask TX underrun detection */ 732 bus_space_write_1(bst, bsh, IMR1, 1); 733 } 734 735 /* Enable interrupts. */ 736 PAGE(sc, 0); 737 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 738 739 xi_set_address(sc); 740 741 PAGE(sc, 0x40); 742 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 743 744 PAGE(sc, 0); 745 746 /* Set current media. */ 747 mii_mediachg(&sc->sc_mii); 748 749 ifp->if_flags |= IFF_RUNNING; 750 ifp->if_flags &= ~IFF_OACTIVE; 751 752 xi_start(ifp); 753 } 754 755 /* 756 * Start outputting on the interface. 757 * Always called as splnet(). 758 */ 759 STATIC void 760 xi_start(struct ifnet *ifp) 761 { 762 struct xi_softc *sc = ifp->if_softc; 763 bus_space_tag_t bst = sc->sc_bst; 764 bus_space_handle_t bsh = sc->sc_bsh; 765 unsigned int s, len, pad = 0; 766 struct mbuf *m0, *m; 767 u_int16_t space; 768 769 DPRINTF(XID_CONFIG, ("xi_start()\n")); 770 771 /* Don't transmit if interface is busy or not running. */ 772 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 773 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 774 return; 775 } 776 777 /* Peek at the next packet. */ 778 IFQ_POLL(&ifp->if_snd, m0); 779 if (m0 == 0) 780 return; 781 782 /* We need to use m->m_pkthdr.len, so require the header. */ 783 if (!(m0->m_flags & M_PKTHDR)) 784 panic("xi_start: no header mbuf"); 785 786 len = m0->m_pkthdr.len; 787 788 #if 1 789 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 790 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 791 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 792 #else 793 pad = 0; 794 #endif 795 796 PAGE(sc, 0); 797 798 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 799 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 800 if (len + pad + 2 > space) { 801 DPRINTF(XID_FIFO, 802 ("xi: not enough space in output FIFO (%d > %d)\n", 803 len + pad + 2, space)); 804 return; 805 } 806 807 IFQ_DEQUEUE(&ifp->if_snd, m0); 808 809 if (ifp->if_bpf) 810 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 811 812 /* 813 * Do the output at splhigh() so that an interrupt from another device 814 * won't cause a FIFO underrun. 815 */ 816 s = splhigh(); 817 818 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 819 for (m = m0; m; ) { 820 if (m->m_len > 1) 821 bus_space_write_multi_2(bst, bsh, EDP, 822 mtod(m, u_int16_t *), m->m_len>>1); 823 if (m->m_len & 1) { 824 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 825 bus_space_write_1(bst, bsh, EDP, 826 *(mtod(m, u_int8_t *) + m->m_len - 1)); 827 } 828 MFREE(m, m0); 829 m = m0; 830 } 831 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 832 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 833 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 834 else { 835 for (; pad > 1; pad -= 2) 836 bus_space_write_2(bst, bsh, EDP, 0); 837 if (pad == 1) 838 bus_space_write_1(bst, bsh, EDP, 0); 839 } 840 841 splx(s); 842 843 ifp->if_timer = 5; 844 ++ifp->if_opackets; 845 } 846 847 STATIC int 848 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 849 { 850 struct ifaddr *ifa = (struct ifaddr *)data; 851 struct xi_softc *sc = ifp->if_softc; 852 int error; 853 854 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 855 856 switch (cmd) { 857 case SIOCINITIFADDR: 858 if ((error = xi_enable(sc)) != 0) 859 break; 860 861 ifp->if_flags |= IFF_UP; 862 863 xi_init(sc); 864 switch (ifa->ifa_addr->sa_family) { 865 #ifdef INET 866 case AF_INET: 867 arp_ifinit(ifp, ifa); 868 break; 869 #endif /* INET */ 870 871 872 default: 873 break; 874 } 875 break; 876 877 default: 878 return (EINVAL); 879 } 880 881 return (0); 882 } 883 884 STATIC int 885 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 886 { 887 struct xi_softc *sc = ifp->if_softc; 888 int s, error = 0; 889 890 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 891 892 s = splnet(); 893 894 switch (cmd) { 895 case SIOCINITIFADDR: 896 error = xi_ether_ioctl(ifp, cmd, data); 897 break; 898 899 case SIOCSIFFLAGS: 900 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 901 break; 902 /* XXX re-use ether_ioctl() */ 903 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 904 case IFF_RUNNING: 905 /* 906 * If interface is marked down and it is running, 907 * stop it. 908 */ 909 xi_stop(sc); 910 ifp->if_flags &= ~IFF_RUNNING; 911 xi_disable(sc); 912 break; 913 case IFF_UP: 914 /* 915 * If interface is marked up and it is stopped, 916 * start it. 917 */ 918 if ((error = xi_enable(sc)) != 0) 919 break; 920 xi_init(sc); 921 break; 922 case IFF_UP|IFF_RUNNING: 923 /* 924 * Reset the interface to pick up changes in any 925 * other flags that affect hardware registers. 926 */ 927 xi_set_address(sc); 928 break; 929 case 0: 930 break; 931 } 932 break; 933 934 case SIOCADDMULTI: 935 case SIOCDELMULTI: 936 if (sc->sc_enabled == 0) { 937 error = EIO; 938 break; 939 } 940 /*FALLTHROUGH*/ 941 case SIOCSIFMEDIA: 942 case SIOCGIFMEDIA: 943 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 944 /* 945 * Multicast list has changed; set the hardware 946 * filter accordingly. 947 */ 948 if (ifp->if_flags & IFF_RUNNING) 949 xi_set_address(sc); 950 error = 0; 951 } 952 break; 953 954 default: 955 error = ether_ioctl(ifp, cmd, data); 956 break; 957 } 958 959 splx(s); 960 return (error); 961 } 962 963 STATIC void 964 xi_set_address(struct xi_softc *sc) 965 { 966 bus_space_tag_t bst = sc->sc_bst; 967 bus_space_handle_t bsh = sc->sc_bsh; 968 struct ethercom *ether = &sc->sc_ethercom; 969 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 970 struct ether_multistep step; 971 struct ether_multi *enm; 972 int page, num; 973 int i; 974 u_int8_t x; 975 const u_int8_t *enaddr; 976 u_int8_t indaddr[64]; 977 978 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 979 980 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 981 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 982 for (i = 0; i < 6; i++) 983 indaddr[i] = enaddr[5 - i]; 984 else 985 for (i = 0; i < 6; i++) 986 indaddr[i] = enaddr[i]; 987 num = 1; 988 989 if (ether->ec_multicnt > 9) { 990 ifp->if_flags |= IFF_ALLMULTI; 991 goto done; 992 } 993 994 ETHER_FIRST_MULTI(step, ether, enm); 995 for (; enm; num++) { 996 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 997 sizeof(enm->enm_addrlo)) != 0) { 998 /* 999 * The multicast address is really a range; 1000 * it's easier just to accept all multicasts. 1001 * XXX should we be setting IFF_ALLMULTI here? 1002 */ 1003 ifp->if_flags |= IFF_ALLMULTI; 1004 goto done; 1005 } 1006 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1007 for (i = 0; i < 6; i++) 1008 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1009 else 1010 for (i = 0; i < 6; i++) 1011 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1012 ETHER_NEXT_MULTI(step, enm); 1013 } 1014 ifp->if_flags &= ~IFF_ALLMULTI; 1015 1016 done: 1017 if (num < 10) 1018 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1019 1020 for (page = 0; page < 8; page++) { 1021 #ifdef XIDEBUG 1022 if (xidebug & XID_MCAST) { 1023 printf("page %d before:", page); 1024 for (i = 0; i < 8; i++) 1025 printf(" %02x", indaddr[page * 8 + i]); 1026 printf("\n"); 1027 } 1028 #endif 1029 1030 PAGE(sc, 0x50 + page); 1031 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1032 page == 7 ? 4 : 8); 1033 /* 1034 * XXX 1035 * Without this delay, the address registers on my CE2 get 1036 * trashed the first and I have to cycle it. I have no idea 1037 * why. - mycroft, 2004/08/09 1038 */ 1039 DELAY(50); 1040 1041 #ifdef XIDEBUG 1042 if (xidebug & XID_MCAST) { 1043 bus_space_read_region_1(bst, bsh, IA, 1044 &indaddr[page * 8], page == 7 ? 4 : 8); 1045 printf("page %d after: ", page); 1046 for (i = 0; i < 8; i++) 1047 printf(" %02x", indaddr[page * 8 + i]); 1048 printf("\n"); 1049 } 1050 #endif 1051 } 1052 1053 PAGE(sc, 0x42); 1054 x = SWC1_IND_ADDR; 1055 if (ifp->if_flags & IFF_PROMISC) 1056 x |= SWC1_PROMISC; 1057 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1058 x |= SWC1_MCAST_PROM; 1059 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1060 x |= SWC1_AUTO_MEDIA; 1061 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1062 } 1063 1064 STATIC void 1065 xi_cycle_power(struct xi_softc *sc) 1066 { 1067 bus_space_tag_t bst = sc->sc_bst; 1068 bus_space_handle_t bsh = sc->sc_bsh; 1069 1070 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1071 1072 PAGE(sc, 4); 1073 DELAY(1); 1074 bus_space_write_1(bst, bsh, GP1, 0); 1075 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1076 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1077 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1078 else 1079 /* XXX What is bit 2 (aka AIC)? */ 1080 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1081 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1082 } 1083 1084 STATIC void 1085 xi_full_reset(struct xi_softc *sc) 1086 { 1087 bus_space_tag_t bst = sc->sc_bst; 1088 bus_space_handle_t bsh = sc->sc_bsh; 1089 u_int8_t x; 1090 1091 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1092 1093 /* Do an as extensive reset as possible on all functions. */ 1094 xi_cycle_power(sc); 1095 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1096 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1097 bus_space_write_1(bst, bsh, CR, 0); 1098 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1099 PAGE(sc, 4); 1100 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1101 /* 1102 * Drive GP1 low to power up ML6692 and GP2 high to power up 1103 * the 10MHz chip. XXX What chip is that? The phy? 1104 */ 1105 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1106 } 1107 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1108 1109 /* Get revision information. XXX Symbolic constants. */ 1110 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1111 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1112 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1113 1114 /* Media selection. XXX Maybe manual overriding too? */ 1115 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1116 /* 1117 * XXX I have no idea what this really does, it is from the 1118 * Linux driver. 1119 */ 1120 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1121 } 1122 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1123 1124 /* 1125 * Disable source insertion. 1126 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1127 */ 1128 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1129 PAGE(sc, 0x42); 1130 bus_space_write_1(bst, bsh, SWC0, 0x20); 1131 } 1132 1133 /* Set the local memory dividing line. */ 1134 if (sc->sc_rev != 1) { 1135 PAGE(sc, 2); 1136 /* XXX Symbolic constant preferrable. */ 1137 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1138 } 1139 1140 /* 1141 * Apparently the receive byte pointer can be bad after a reset, so 1142 * we hardwire it correctly. 1143 */ 1144 PAGE(sc, 0); 1145 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1146 1147 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1148 PAGE(sc, 0x40); 1149 bus_space_write_1(bst, bsh, RX0MSK, 1150 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1151 bus_space_write_1(bst, bsh, TX0MSK, 1152 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1153 SQE | TX_ABORT | TX_OK); 1154 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1155 /* XXX From Linux, dunno what 0xb0 means. */ 1156 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1157 bus_space_write_1(bst, bsh, RXST0, 0); 1158 bus_space_write_1(bst, bsh, TXST0, 0); 1159 bus_space_write_1(bst, bsh, TXST1, 0); 1160 1161 PAGE(sc, 2); 1162 1163 /* Enable MII function if available. */ 1164 x = 0; 1165 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1166 x |= SELECT_MII; 1167 bus_space_write_1(bst, bsh, MSR, x); 1168 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1169 1170 /* Configure the LED registers. */ 1171 /* XXX This is not good for 10base2. */ 1172 bus_space_write_1(bst, bsh, LED, 1173 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1174 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1175 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1176 1177 /* 1178 * The Linux driver says this: 1179 * We should switch back to page 0 to avoid a bug in revision 0 1180 * where regs with offset below 8 can't be read after an access 1181 * to the MAC registers. 1182 */ 1183 PAGE(sc, 0); 1184 } 1185