1 /* $NetBSD: if_xi.c,v 1.80 2016/12/15 09:28:06 ozaki-r Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.80 2016/12/15 09:28:06 ozaki-r Exp $"); 59 60 #include "opt_inet.h" 61 62 #include <sys/param.h> 63 #include <sys/systm.h> 64 #include <sys/device.h> 65 #include <sys/ioctl.h> 66 #include <sys/mbuf.h> 67 #include <sys/malloc.h> 68 #include <sys/socket.h> 69 #include <sys/kernel.h> 70 #include <sys/proc.h> 71 72 #include <net/if.h> 73 #include <net/if_dl.h> 74 #include <net/if_media.h> 75 #include <net/if_types.h> 76 #include <net/if_ether.h> 77 78 #ifdef INET 79 #include <netinet/in.h> 80 #include <netinet/in_systm.h> 81 #include <netinet/in_var.h> 82 #include <netinet/ip.h> 83 #include <netinet/if_inarp.h> 84 #endif 85 86 #include <net/bpf.h> 87 #include <net/bpfdesc.h> 88 89 /* 90 * Maximum number of bytes to read per interrupt. Linux recommends 91 * somewhere between 2000-22000. 92 * XXX This is currently a hard maximum. 93 */ 94 #define MAX_BYTES_INTR 12000 95 96 #include <dev/mii/mii.h> 97 #include <dev/mii/miivar.h> 98 99 #include <dev/pcmcia/pcmciareg.h> 100 #include <dev/pcmcia/pcmciavar.h> 101 #include <dev/pcmcia/pcmciadevs.h> 102 103 #include <dev/pcmcia/if_xireg.h> 104 #include <dev/pcmcia/if_xivar.h> 105 106 #ifdef __GNUC__ 107 #define INLINE inline 108 #else 109 #define INLINE 110 #endif /* __GNUC__ */ 111 112 #define XIDEBUG 113 #define XIDEBUG_VALUE 0 114 115 #ifdef XIDEBUG 116 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 117 118 #define XID_CONFIG 0x01 119 #define XID_MII 0x02 120 #define XID_INTR 0x04 121 #define XID_FIFO 0x08 122 #define XID_MCAST 0x10 123 124 #ifdef XIDEBUG_VALUE 125 int xidebug = XIDEBUG_VALUE; 126 #else 127 int xidebug = 0; 128 #endif 129 #else 130 #define DPRINTF(cat, x) (void)0 131 #endif 132 133 #define STATIC 134 135 STATIC int xi_enable(struct xi_softc *); 136 STATIC void xi_disable(struct xi_softc *); 137 STATIC void xi_cycle_power(struct xi_softc *); 138 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 139 STATIC void xi_full_reset(struct xi_softc *); 140 STATIC void xi_init(struct xi_softc *); 141 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 142 STATIC int xi_mdi_read(device_t, int, int); 143 STATIC void xi_mdi_write(device_t, int, int, int); 144 STATIC int xi_mediachange(struct ifnet *); 145 STATIC u_int16_t xi_get(struct xi_softc *); 146 STATIC void xi_reset(struct xi_softc *); 147 STATIC void xi_set_address(struct xi_softc *); 148 STATIC void xi_start(struct ifnet *); 149 STATIC void xi_statchg(struct ifnet *); 150 STATIC void xi_stop(struct xi_softc *); 151 STATIC void xi_watchdog(struct ifnet *); 152 153 void 154 xi_attach(struct xi_softc *sc, u_int8_t *myea) 155 { 156 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 157 158 #if 0 159 /* 160 * Configuration as advised by DINGO documentation. 161 * Dingo has some extra configuration registers in the CCR space. 162 */ 163 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 164 struct pcmcia_mem_handle pcmh; 165 int ccr_window; 166 bus_size_t ccr_offset; 167 168 /* get access to the DINGO CCR space */ 169 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 170 &pcmh)) { 171 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 172 goto fail; 173 } 174 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 175 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 176 &pcmh, &ccr_offset, &ccr_window)) { 177 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 178 pcmcia_mem_free(psc->sc_pf, &pcmh); 179 goto fail; 180 } 181 182 /* enable the second function - usually modem */ 183 bus_space_write_1(pcmh.memt, pcmh.memh, 184 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 185 bus_space_write_1(pcmh.memt, pcmh.memh, 186 ccr_offset + PCMCIA_CCR_DCOR1, 187 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 188 bus_space_write_1(pcmh.memt, pcmh.memh, 189 ccr_offset + PCMCIA_CCR_DCOR2, 0); 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR3, 0); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR4, 0); 194 195 /* We don't need them anymore and can free them (I think). */ 196 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 197 pcmcia_mem_free(psc->sc_pf, &pcmh); 198 } 199 #endif 200 201 /* Reset and initialize the card. */ 202 xi_full_reset(sc); 203 204 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 205 206 ifp = &sc->sc_ethercom.ec_if; 207 /* Initialize the ifnet structure. */ 208 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 209 ifp->if_softc = sc; 210 ifp->if_start = xi_start; 211 ifp->if_ioctl = xi_ioctl; 212 ifp->if_watchdog = xi_watchdog; 213 ifp->if_flags = 214 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 215 IFQ_SET_READY(&ifp->if_snd); 216 217 /* 802.1q capability */ 218 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 219 220 /* Attach the interface. */ 221 if_attach(ifp); 222 if_deferred_start_init(ifp, NULL); 223 ether_ifattach(ifp, myea); 224 225 /* 226 * Initialize our media structures and probe the MII. 227 */ 228 sc->sc_mii.mii_ifp = ifp; 229 sc->sc_mii.mii_readreg = xi_mdi_read; 230 sc->sc_mii.mii_writereg = xi_mdi_write; 231 sc->sc_mii.mii_statchg = xi_statchg; 232 sc->sc_ethercom.ec_mii = &sc->sc_mii; 233 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 234 ether_mediastatus); 235 DPRINTF(XID_MII | XID_CONFIG, 236 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 237 238 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 239 MII_OFFSET_ANY, 0); 240 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 241 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 242 NULL); 243 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 244 245 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 246 RND_TYPE_NET, RND_FLAG_DEFAULT); 247 } 248 249 int 250 xi_detach(device_t self, int flags) 251 { 252 struct xi_softc *sc = device_private(self); 253 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 254 255 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 256 257 xi_disable(sc); 258 259 rnd_detach_source(&sc->sc_rnd_source); 260 261 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 262 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 263 ether_ifdetach(ifp); 264 if_detach(ifp); 265 266 return 0; 267 } 268 269 int 270 xi_intr(void *arg) 271 { 272 struct xi_softc *sc = arg; 273 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 274 u_int8_t esr, rsr, isr, rx_status; 275 u_int16_t tx_status, recvcount = 0, tempint; 276 277 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 278 279 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 280 return (0); 281 282 ifp->if_timer = 0; /* turn watchdog timer off */ 283 284 PAGE(sc, 0); 285 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 286 /* Disable interrupt (Linux does it). */ 287 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 288 } 289 290 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 291 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 292 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 293 294 /* Check to see if card has been ejected. */ 295 if (isr == 0xff) { 296 #ifdef DIAGNOSTIC 297 printf("%s: interrupt for dead card\n", 298 device_xname(sc->sc_dev)); 299 #endif 300 goto end; 301 } 302 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 303 304 PAGE(sc, 0x40); 305 rx_status = 306 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 307 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 308 tx_status = 309 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 310 tx_status |= 311 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 312 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 313 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 314 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 315 tx_status)); 316 317 PAGE(sc, 0); 318 while (esr & FULL_PKT_RCV) { 319 if (!(rsr & RSR_RX_OK)) 320 break; 321 322 /* Compare bytes read this interrupt to hard maximum. */ 323 if (recvcount > MAX_BYTES_INTR) { 324 DPRINTF(XID_INTR, 325 ("xi: too many bytes this interrupt\n")); 326 ifp->if_iqdrops++; 327 /* Drop packet. */ 328 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 329 DO_SKIP_RX_PKT); 330 } 331 tempint = xi_get(sc); /* XXX doesn't check the error! */ 332 recvcount += tempint; 333 ifp->if_ibytes += tempint; 334 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 335 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 336 } 337 338 /* Packet too long? */ 339 if (rsr & RSR_TOO_LONG) { 340 ifp->if_ierrors++; 341 DPRINTF(XID_INTR, ("xi: packet too long\n")); 342 } 343 344 /* CRC error? */ 345 if (rsr & RSR_CRCERR) { 346 ifp->if_ierrors++; 347 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 348 } 349 350 /* Alignment error? */ 351 if (rsr & RSR_ALIGNERR) { 352 ifp->if_ierrors++; 353 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 354 } 355 356 /* Check for rx overrun. */ 357 if (rx_status & RX_OVERRUN) { 358 ifp->if_ierrors++; 359 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 360 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 361 } 362 363 /* Try to start more packets transmitting. */ 364 if_schedule_deferred_start(ifp); 365 366 /* Detected excessive collisions? */ 367 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 368 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 369 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 370 ifp->if_oerrors++; 371 } 372 373 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 374 ifp->if_oerrors++; 375 376 /* have handled the interrupt */ 377 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 378 379 end: 380 /* Reenable interrupts. */ 381 PAGE(sc, 0); 382 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 383 384 return (1); 385 } 386 387 /* 388 * Pull a packet from the card into an mbuf chain. 389 */ 390 STATIC u_int16_t 391 xi_get(struct xi_softc *sc) 392 { 393 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 394 struct mbuf *top, **mp, *m; 395 u_int16_t pktlen, len, recvcount = 0; 396 u_int8_t *data; 397 398 DPRINTF(XID_CONFIG, ("xi_get()\n")); 399 400 PAGE(sc, 0); 401 pktlen = 402 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 403 404 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 405 406 if (pktlen == 0) { 407 /* 408 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 409 * when MPE is set. It is not known why. 410 */ 411 return (0); 412 } 413 414 /* XXX should this be incremented now ? */ 415 recvcount += pktlen; 416 417 MGETHDR(m, M_DONTWAIT, MT_DATA); 418 if (m == NULL) 419 return (recvcount); 420 m_set_rcvif(m, ifp); 421 m->m_pkthdr.len = pktlen; 422 len = MHLEN; 423 top = NULL; 424 mp = ⊤ 425 426 while (pktlen > 0) { 427 if (top) { 428 MGET(m, M_DONTWAIT, MT_DATA); 429 if (m == NULL) { 430 m_freem(top); 431 return (recvcount); 432 } 433 len = MLEN; 434 } 435 if (pktlen >= MINCLSIZE) { 436 MCLGET(m, M_DONTWAIT); 437 if (!(m->m_flags & M_EXT)) { 438 m_freem(m); 439 m_freem(top); 440 return (recvcount); 441 } 442 len = MCLBYTES; 443 } 444 if (top == NULL) { 445 char *newdata = (char *)ALIGN(m->m_data + 446 sizeof(struct ether_header)) - 447 sizeof(struct ether_header); 448 len -= newdata - m->m_data; 449 m->m_data = newdata; 450 } 451 len = min(pktlen, len); 452 data = mtod(m, u_int8_t *); 453 if (len > 1) { 454 len &= ~1; 455 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 456 (u_int16_t *)data, len>>1); 457 } else 458 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 459 m->m_len = len; 460 pktlen -= len; 461 *mp = m; 462 mp = &m->m_next; 463 } 464 465 /* Skip Rx packet. */ 466 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 467 468 if (top == NULL) 469 return recvcount; 470 471 /* Trim the CRC off the end of the packet. */ 472 m_adj(top, -ETHER_CRC_LEN); 473 474 if_percpuq_enqueue(ifp->if_percpuq, top); 475 return (recvcount); 476 } 477 478 /* 479 * Serial management for the MII. 480 * The DELAY's below stem from the fact that the maximum frequency 481 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 482 * go much faster than that. 483 */ 484 485 /* Let the MII serial management be idle for one period. */ 486 static INLINE void xi_mdi_idle(struct xi_softc *); 487 static INLINE void 488 xi_mdi_idle(struct xi_softc *sc) 489 { 490 bus_space_tag_t bst = sc->sc_bst; 491 bus_space_handle_t bsh = sc->sc_bsh; 492 493 /* Drive MDC low... */ 494 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 495 DELAY(1); 496 497 /* and high again. */ 498 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 499 DELAY(1); 500 } 501 502 /* Pulse out one bit of data. */ 503 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 504 static INLINE void 505 xi_mdi_pulse(struct xi_softc *sc, int data) 506 { 507 bus_space_tag_t bst = sc->sc_bst; 508 bus_space_handle_t bsh = sc->sc_bsh; 509 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 510 511 /* First latch the data bit MDIO with clock bit MDC low...*/ 512 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 513 DELAY(1); 514 515 /* then raise the clock again, preserving the data bit. */ 516 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 517 DELAY(1); 518 } 519 520 /* Probe one bit of data. */ 521 static INLINE int xi_mdi_probe(struct xi_softc *sc); 522 static INLINE int 523 xi_mdi_probe(struct xi_softc *sc) 524 { 525 bus_space_tag_t bst = sc->sc_bst; 526 bus_space_handle_t bsh = sc->sc_bsh; 527 u_int8_t x; 528 529 /* Pull clock bit MDCK low... */ 530 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 531 DELAY(1); 532 533 /* Read data and drive clock high again. */ 534 x = bus_space_read_1(bst, bsh, GP2); 535 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 536 DELAY(1); 537 538 return (x & MDIO); 539 } 540 541 /* Pulse out a sequence of data bits. */ 542 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 543 static INLINE void 544 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 545 { 546 u_int32_t mask; 547 548 for (mask = 1 << (len - 1); mask; mask >>= 1) 549 xi_mdi_pulse(sc, data & mask); 550 } 551 552 /* Read a PHY register. */ 553 STATIC int 554 xi_mdi_read(device_t self, int phy, int reg) 555 { 556 struct xi_softc *sc = device_private(self); 557 int i; 558 u_int32_t mask; 559 u_int32_t data = 0; 560 561 PAGE(sc, 2); 562 for (i = 0; i < 32; i++) /* Synchronize. */ 563 xi_mdi_pulse(sc, 1); 564 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 565 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 566 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 567 xi_mdi_idle(sc); /* Turn around. */ 568 xi_mdi_probe(sc); /* Drop initial zero bit. */ 569 570 for (mask = 1 << 15; mask; mask >>= 1) { 571 if (xi_mdi_probe(sc)) 572 data |= mask; 573 } 574 xi_mdi_idle(sc); 575 576 DPRINTF(XID_MII, 577 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 578 579 return (data); 580 } 581 582 /* Write a PHY register. */ 583 STATIC void 584 xi_mdi_write(device_t self, int phy, int reg, int value) 585 { 586 struct xi_softc *sc = device_private(self); 587 int i; 588 589 PAGE(sc, 2); 590 for (i = 0; i < 32; i++) /* Synchronize. */ 591 xi_mdi_pulse(sc, 1); 592 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 593 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 594 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 595 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 596 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 597 xi_mdi_idle(sc); /* Idle away. */ 598 599 DPRINTF(XID_MII, 600 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 601 } 602 603 STATIC void 604 xi_statchg(struct ifnet *ifp) 605 { 606 /* XXX Update ifp->if_baudrate */ 607 } 608 609 /* 610 * Change media according to request. 611 */ 612 STATIC int 613 xi_mediachange(struct ifnet *ifp) 614 { 615 int s; 616 617 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 618 619 if (ifp->if_flags & IFF_UP) { 620 s = splnet(); 621 xi_init(ifp->if_softc); 622 splx(s); 623 } 624 return (0); 625 } 626 627 STATIC void 628 xi_reset(struct xi_softc *sc) 629 { 630 int s; 631 632 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 633 634 s = splnet(); 635 xi_stop(sc); 636 xi_init(sc); 637 splx(s); 638 } 639 640 STATIC void 641 xi_watchdog(struct ifnet *ifp) 642 { 643 struct xi_softc *sc = ifp->if_softc; 644 645 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 646 ++ifp->if_oerrors; 647 648 xi_reset(sc); 649 } 650 651 STATIC void 652 xi_stop(register struct xi_softc *sc) 653 { 654 bus_space_tag_t bst = sc->sc_bst; 655 bus_space_handle_t bsh = sc->sc_bsh; 656 657 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 658 659 PAGE(sc, 0x40); 660 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 661 662 /* Disable interrupts. */ 663 PAGE(sc, 0); 664 bus_space_write_1(bst, bsh, CR, 0); 665 666 PAGE(sc, 1); 667 bus_space_write_1(bst, bsh, IMR0, 0); 668 669 /* Cancel watchdog timer. */ 670 sc->sc_ethercom.ec_if.if_timer = 0; 671 } 672 673 STATIC int 674 xi_enable(struct xi_softc *sc) 675 { 676 int error; 677 678 if (!sc->sc_enabled) { 679 error = (*sc->sc_enable)(sc); 680 if (error) 681 return (error); 682 sc->sc_enabled = 1; 683 xi_full_reset(sc); 684 } 685 return (0); 686 } 687 688 STATIC void 689 xi_disable(struct xi_softc *sc) 690 { 691 692 if (sc->sc_enabled) { 693 sc->sc_enabled = 0; 694 (*sc->sc_disable)(sc); 695 } 696 } 697 698 STATIC void 699 xi_init(struct xi_softc *sc) 700 { 701 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 702 bus_space_tag_t bst = sc->sc_bst; 703 bus_space_handle_t bsh = sc->sc_bsh; 704 705 DPRINTF(XID_CONFIG, ("xi_init()\n")); 706 707 /* Setup the ethernet interrupt mask. */ 708 PAGE(sc, 1); 709 bus_space_write_1(bst, bsh, IMR0, 710 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 711 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 712 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 713 /* XXX What is this? Not for Dingo at least. */ 714 /* Unmask TX underrun detection */ 715 bus_space_write_1(bst, bsh, IMR1, 1); 716 } 717 718 /* Enable interrupts. */ 719 PAGE(sc, 0); 720 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 721 722 xi_set_address(sc); 723 724 PAGE(sc, 0x40); 725 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 726 727 PAGE(sc, 0); 728 729 /* Set current media. */ 730 mii_mediachg(&sc->sc_mii); 731 732 ifp->if_flags |= IFF_RUNNING; 733 ifp->if_flags &= ~IFF_OACTIVE; 734 735 xi_start(ifp); 736 } 737 738 /* 739 * Start outputting on the interface. 740 * Always called as splnet(). 741 */ 742 STATIC void 743 xi_start(struct ifnet *ifp) 744 { 745 struct xi_softc *sc = ifp->if_softc; 746 bus_space_tag_t bst = sc->sc_bst; 747 bus_space_handle_t bsh = sc->sc_bsh; 748 unsigned int s, len, pad = 0; 749 struct mbuf *m0, *m; 750 u_int16_t space; 751 752 DPRINTF(XID_CONFIG, ("xi_start()\n")); 753 754 /* Don't transmit if interface is busy or not running. */ 755 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 756 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 757 return; 758 } 759 760 /* Peek at the next packet. */ 761 IFQ_POLL(&ifp->if_snd, m0); 762 if (m0 == 0) 763 return; 764 765 /* We need to use m->m_pkthdr.len, so require the header. */ 766 if (!(m0->m_flags & M_PKTHDR)) 767 panic("xi_start: no header mbuf"); 768 769 len = m0->m_pkthdr.len; 770 771 #if 1 772 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 773 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 774 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 775 #else 776 pad = 0; 777 #endif 778 779 PAGE(sc, 0); 780 781 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 782 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 783 if (len + pad + 2 > space) { 784 DPRINTF(XID_FIFO, 785 ("xi: not enough space in output FIFO (%d > %d)\n", 786 len + pad + 2, space)); 787 return; 788 } 789 790 IFQ_DEQUEUE(&ifp->if_snd, m0); 791 792 bpf_mtap(ifp, m0); 793 794 /* 795 * Do the output at splhigh() so that an interrupt from another device 796 * won't cause a FIFO underrun. 797 */ 798 s = splhigh(); 799 800 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 801 for (m = m0; m; ) { 802 if (m->m_len > 1) 803 bus_space_write_multi_2(bst, bsh, EDP, 804 mtod(m, u_int16_t *), m->m_len>>1); 805 if (m->m_len & 1) { 806 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 807 bus_space_write_1(bst, bsh, EDP, 808 *(mtod(m, u_int8_t *) + m->m_len - 1)); 809 } 810 m = m0 = m_free(m); 811 } 812 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 813 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 814 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 815 else { 816 for (; pad > 1; pad -= 2) 817 bus_space_write_2(bst, bsh, EDP, 0); 818 if (pad == 1) 819 bus_space_write_1(bst, bsh, EDP, 0); 820 } 821 822 splx(s); 823 824 ifp->if_timer = 5; 825 ++ifp->if_opackets; 826 } 827 828 STATIC int 829 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 830 { 831 struct ifaddr *ifa = (struct ifaddr *)data; 832 struct xi_softc *sc = ifp->if_softc; 833 int error; 834 835 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 836 837 switch (cmd) { 838 case SIOCINITIFADDR: 839 if ((error = xi_enable(sc)) != 0) 840 break; 841 842 ifp->if_flags |= IFF_UP; 843 844 xi_init(sc); 845 switch (ifa->ifa_addr->sa_family) { 846 #ifdef INET 847 case AF_INET: 848 arp_ifinit(ifp, ifa); 849 break; 850 #endif /* INET */ 851 852 853 default: 854 break; 855 } 856 break; 857 858 default: 859 return (EINVAL); 860 } 861 862 return (0); 863 } 864 865 STATIC int 866 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 867 { 868 struct xi_softc *sc = ifp->if_softc; 869 int s, error = 0; 870 871 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 872 873 s = splnet(); 874 875 switch (cmd) { 876 case SIOCINITIFADDR: 877 error = xi_ether_ioctl(ifp, cmd, data); 878 break; 879 880 case SIOCSIFFLAGS: 881 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 882 break; 883 /* XXX re-use ether_ioctl() */ 884 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 885 case IFF_RUNNING: 886 /* 887 * If interface is marked down and it is running, 888 * stop it. 889 */ 890 xi_stop(sc); 891 ifp->if_flags &= ~IFF_RUNNING; 892 xi_disable(sc); 893 break; 894 case IFF_UP: 895 /* 896 * If interface is marked up and it is stopped, 897 * start it. 898 */ 899 if ((error = xi_enable(sc)) != 0) 900 break; 901 xi_init(sc); 902 break; 903 case IFF_UP|IFF_RUNNING: 904 /* 905 * Reset the interface to pick up changes in any 906 * other flags that affect hardware registers. 907 */ 908 xi_set_address(sc); 909 break; 910 case 0: 911 break; 912 } 913 break; 914 915 case SIOCADDMULTI: 916 case SIOCDELMULTI: 917 if (sc->sc_enabled == 0) { 918 error = EIO; 919 break; 920 } 921 /*FALLTHROUGH*/ 922 case SIOCSIFMEDIA: 923 case SIOCGIFMEDIA: 924 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 925 /* 926 * Multicast list has changed; set the hardware 927 * filter accordingly. 928 */ 929 if (ifp->if_flags & IFF_RUNNING) 930 xi_set_address(sc); 931 error = 0; 932 } 933 break; 934 935 default: 936 error = ether_ioctl(ifp, cmd, data); 937 break; 938 } 939 940 splx(s); 941 return (error); 942 } 943 944 STATIC void 945 xi_set_address(struct xi_softc *sc) 946 { 947 bus_space_tag_t bst = sc->sc_bst; 948 bus_space_handle_t bsh = sc->sc_bsh; 949 struct ethercom *ether = &sc->sc_ethercom; 950 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 951 struct ether_multistep step; 952 struct ether_multi *enm; 953 int page, num; 954 int i; 955 u_int8_t x; 956 const u_int8_t *enaddr; 957 u_int8_t indaddr[64]; 958 959 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 960 961 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 962 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 963 for (i = 0; i < 6; i++) 964 indaddr[i] = enaddr[5 - i]; 965 else 966 for (i = 0; i < 6; i++) 967 indaddr[i] = enaddr[i]; 968 num = 1; 969 970 if (ether->ec_multicnt > 9) { 971 ifp->if_flags |= IFF_ALLMULTI; 972 goto done; 973 } 974 975 ETHER_FIRST_MULTI(step, ether, enm); 976 for (; enm; num++) { 977 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 978 sizeof(enm->enm_addrlo)) != 0) { 979 /* 980 * The multicast address is really a range; 981 * it's easier just to accept all multicasts. 982 * XXX should we be setting IFF_ALLMULTI here? 983 */ 984 ifp->if_flags |= IFF_ALLMULTI; 985 goto done; 986 } 987 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 988 for (i = 0; i < 6; i++) 989 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 990 else 991 for (i = 0; i < 6; i++) 992 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 993 ETHER_NEXT_MULTI(step, enm); 994 } 995 ifp->if_flags &= ~IFF_ALLMULTI; 996 997 done: 998 if (num < 10) 999 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1000 1001 for (page = 0; page < 8; page++) { 1002 #ifdef XIDEBUG 1003 if (xidebug & XID_MCAST) { 1004 printf("page %d before:", page); 1005 for (i = 0; i < 8; i++) 1006 printf(" %02x", indaddr[page * 8 + i]); 1007 printf("\n"); 1008 } 1009 #endif 1010 1011 PAGE(sc, 0x50 + page); 1012 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1013 page == 7 ? 4 : 8); 1014 /* 1015 * XXX 1016 * Without this delay, the address registers on my CE2 get 1017 * trashed the first and I have to cycle it. I have no idea 1018 * why. - mycroft, 2004/08/09 1019 */ 1020 DELAY(50); 1021 1022 #ifdef XIDEBUG 1023 if (xidebug & XID_MCAST) { 1024 bus_space_read_region_1(bst, bsh, IA, 1025 &indaddr[page * 8], page == 7 ? 4 : 8); 1026 printf("page %d after: ", page); 1027 for (i = 0; i < 8; i++) 1028 printf(" %02x", indaddr[page * 8 + i]); 1029 printf("\n"); 1030 } 1031 #endif 1032 } 1033 1034 PAGE(sc, 0x42); 1035 x = SWC1_IND_ADDR; 1036 if (ifp->if_flags & IFF_PROMISC) 1037 x |= SWC1_PROMISC; 1038 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1039 x |= SWC1_MCAST_PROM; 1040 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1041 x |= SWC1_AUTO_MEDIA; 1042 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1043 } 1044 1045 STATIC void 1046 xi_cycle_power(struct xi_softc *sc) 1047 { 1048 bus_space_tag_t bst = sc->sc_bst; 1049 bus_space_handle_t bsh = sc->sc_bsh; 1050 1051 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1052 1053 PAGE(sc, 4); 1054 DELAY(1); 1055 bus_space_write_1(bst, bsh, GP1, 0); 1056 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1057 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1058 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1059 else 1060 /* XXX What is bit 2 (aka AIC)? */ 1061 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1062 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1063 } 1064 1065 STATIC void 1066 xi_full_reset(struct xi_softc *sc) 1067 { 1068 bus_space_tag_t bst = sc->sc_bst; 1069 bus_space_handle_t bsh = sc->sc_bsh; 1070 u_int8_t x; 1071 1072 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1073 1074 /* Do an as extensive reset as possible on all functions. */ 1075 xi_cycle_power(sc); 1076 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1077 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1078 bus_space_write_1(bst, bsh, CR, 0); 1079 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1080 PAGE(sc, 4); 1081 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1082 /* 1083 * Drive GP1 low to power up ML6692 and GP2 high to power up 1084 * the 10MHz chip. XXX What chip is that? The phy? 1085 */ 1086 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1087 } 1088 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1089 1090 /* Get revision information. XXX Symbolic constants. */ 1091 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1092 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1093 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1094 1095 /* Media selection. XXX Maybe manual overriding too? */ 1096 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1097 /* 1098 * XXX I have no idea what this really does, it is from the 1099 * Linux driver. 1100 */ 1101 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1102 } 1103 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1104 1105 /* 1106 * Disable source insertion. 1107 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1108 */ 1109 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1110 PAGE(sc, 0x42); 1111 bus_space_write_1(bst, bsh, SWC0, 0x20); 1112 } 1113 1114 /* Set the local memory dividing line. */ 1115 if (sc->sc_rev != 1) { 1116 PAGE(sc, 2); 1117 /* XXX Symbolic constant preferrable. */ 1118 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1119 } 1120 1121 /* 1122 * Apparently the receive byte pointer can be bad after a reset, so 1123 * we hardwire it correctly. 1124 */ 1125 PAGE(sc, 0); 1126 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1127 1128 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1129 PAGE(sc, 0x40); 1130 bus_space_write_1(bst, bsh, RX0MSK, 1131 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1132 bus_space_write_1(bst, bsh, TX0MSK, 1133 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1134 SQE | TX_ABORT | TX_OK); 1135 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1136 /* XXX From Linux, dunno what 0xb0 means. */ 1137 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1138 bus_space_write_1(bst, bsh, RXST0, 0); 1139 bus_space_write_1(bst, bsh, TXST0, 0); 1140 bus_space_write_1(bst, bsh, TXST1, 0); 1141 1142 PAGE(sc, 2); 1143 1144 /* Enable MII function if available. */ 1145 x = 0; 1146 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1147 x |= SELECT_MII; 1148 bus_space_write_1(bst, bsh, MSR, x); 1149 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1150 1151 /* Configure the LED registers. */ 1152 /* XXX This is not good for 10base2. */ 1153 bus_space_write_1(bst, bsh, LED, 1154 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1155 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1156 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1157 1158 /* 1159 * The Linux driver says this: 1160 * We should switch back to page 0 to avoid a bug in revision 0 1161 * where regs with offset below 8 can't be read after an access 1162 * to the MAC registers. 1163 */ 1164 PAGE(sc, 0); 1165 } 1166