1 /* $NetBSD: if_xi.c,v 1.73 2012/07/22 14:33:05 matt Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.73 2012/07/22 14:33:05 matt Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 63 #include <sys/param.h> 64 #include <sys/systm.h> 65 #include <sys/device.h> 66 #include <sys/ioctl.h> 67 #include <sys/mbuf.h> 68 #include <sys/malloc.h> 69 #include <sys/socket.h> 70 #include <sys/kernel.h> 71 #include <sys/proc.h> 72 73 #include <net/if.h> 74 #include <net/if_dl.h> 75 #include <net/if_media.h> 76 #include <net/if_types.h> 77 #include <net/if_ether.h> 78 79 #ifdef INET 80 #include <netinet/in.h> 81 #include <netinet/in_systm.h> 82 #include <netinet/in_var.h> 83 #include <netinet/ip.h> 84 #include <netinet/if_inarp.h> 85 #endif 86 87 #ifdef IPX 88 #include <netipx/ipx.h> 89 #include <netipx/ipx_if.h> 90 #endif 91 92 93 #include <net/bpf.h> 94 #include <net/bpfdesc.h> 95 96 /* 97 * Maximum number of bytes to read per interrupt. Linux recommends 98 * somewhere between 2000-22000. 99 * XXX This is currently a hard maximum. 100 */ 101 #define MAX_BYTES_INTR 12000 102 103 #include <dev/mii/mii.h> 104 #include <dev/mii/miivar.h> 105 106 #include <dev/pcmcia/pcmciareg.h> 107 #include <dev/pcmcia/pcmciavar.h> 108 #include <dev/pcmcia/pcmciadevs.h> 109 110 #include <dev/pcmcia/if_xireg.h> 111 #include <dev/pcmcia/if_xivar.h> 112 113 #ifdef __GNUC__ 114 #define INLINE inline 115 #else 116 #define INLINE 117 #endif /* __GNUC__ */ 118 119 #define XIDEBUG 120 #define XIDEBUG_VALUE 0 121 122 #ifdef XIDEBUG 123 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 124 125 #define XID_CONFIG 0x01 126 #define XID_MII 0x02 127 #define XID_INTR 0x04 128 #define XID_FIFO 0x08 129 #define XID_MCAST 0x10 130 131 #ifdef XIDEBUG_VALUE 132 int xidebug = XIDEBUG_VALUE; 133 #else 134 int xidebug = 0; 135 #endif 136 #else 137 #define DPRINTF(cat, x) (void)0 138 #endif 139 140 #define STATIC 141 142 STATIC int xi_enable(struct xi_softc *); 143 STATIC void xi_disable(struct xi_softc *); 144 STATIC void xi_cycle_power(struct xi_softc *); 145 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 146 STATIC void xi_full_reset(struct xi_softc *); 147 STATIC void xi_init(struct xi_softc *); 148 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 149 STATIC int xi_mdi_read(device_t, int, int); 150 STATIC void xi_mdi_write(device_t, int, int, int); 151 STATIC int xi_mediachange(struct ifnet *); 152 STATIC u_int16_t xi_get(struct xi_softc *); 153 STATIC void xi_reset(struct xi_softc *); 154 STATIC void xi_set_address(struct xi_softc *); 155 STATIC void xi_start(struct ifnet *); 156 STATIC void xi_statchg(struct ifnet *); 157 STATIC void xi_stop(struct xi_softc *); 158 STATIC void xi_watchdog(struct ifnet *); 159 160 void 161 xi_attach(struct xi_softc *sc, u_int8_t *myea) 162 { 163 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 164 165 #if 0 166 /* 167 * Configuration as advised by DINGO documentation. 168 * Dingo has some extra configuration registers in the CCR space. 169 */ 170 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 171 struct pcmcia_mem_handle pcmh; 172 int ccr_window; 173 bus_size_t ccr_offset; 174 175 /* get access to the DINGO CCR space */ 176 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 177 &pcmh)) { 178 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 179 goto fail; 180 } 181 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 182 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 183 &pcmh, &ccr_offset, &ccr_window)) { 184 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 185 pcmcia_mem_free(psc->sc_pf, &pcmh); 186 goto fail; 187 } 188 189 /* enable the second function - usually modem */ 190 bus_space_write_1(pcmh.memt, pcmh.memh, 191 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 192 bus_space_write_1(pcmh.memt, pcmh.memh, 193 ccr_offset + PCMCIA_CCR_DCOR1, 194 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 195 bus_space_write_1(pcmh.memt, pcmh.memh, 196 ccr_offset + PCMCIA_CCR_DCOR2, 0); 197 bus_space_write_1(pcmh.memt, pcmh.memh, 198 ccr_offset + PCMCIA_CCR_DCOR3, 0); 199 bus_space_write_1(pcmh.memt, pcmh.memh, 200 ccr_offset + PCMCIA_CCR_DCOR4, 0); 201 202 /* We don't need them anymore and can free them (I think). */ 203 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 204 pcmcia_mem_free(psc->sc_pf, &pcmh); 205 } 206 #endif 207 208 /* Reset and initialize the card. */ 209 xi_full_reset(sc); 210 211 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 212 213 ifp = &sc->sc_ethercom.ec_if; 214 /* Initialize the ifnet structure. */ 215 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 216 ifp->if_softc = sc; 217 ifp->if_start = xi_start; 218 ifp->if_ioctl = xi_ioctl; 219 ifp->if_watchdog = xi_watchdog; 220 ifp->if_flags = 221 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 222 IFQ_SET_READY(&ifp->if_snd); 223 224 /* 802.1q capability */ 225 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 226 227 /* Attach the interface. */ 228 if_attach(ifp); 229 ether_ifattach(ifp, myea); 230 231 /* 232 * Initialize our media structures and probe the MII. 233 */ 234 sc->sc_mii.mii_ifp = ifp; 235 sc->sc_mii.mii_readreg = xi_mdi_read; 236 sc->sc_mii.mii_writereg = xi_mdi_write; 237 sc->sc_mii.mii_statchg = xi_statchg; 238 sc->sc_ethercom.ec_mii = &sc->sc_mii; 239 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 240 ether_mediastatus); 241 DPRINTF(XID_MII | XID_CONFIG, 242 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 243 244 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 245 MII_OFFSET_ANY, 0); 246 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 247 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 248 NULL); 249 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 250 251 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), 252 RND_TYPE_NET, 0); 253 } 254 255 int 256 xi_detach(device_t self, int flags) 257 { 258 struct xi_softc *sc = device_private(self); 259 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 260 261 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 262 263 xi_disable(sc); 264 265 rnd_detach_source(&sc->sc_rnd_source); 266 267 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 268 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 269 ether_ifdetach(ifp); 270 if_detach(ifp); 271 272 return 0; 273 } 274 275 int 276 xi_intr(void *arg) 277 { 278 struct xi_softc *sc = arg; 279 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 280 u_int8_t esr, rsr, isr, rx_status; 281 u_int16_t tx_status, recvcount = 0, tempint; 282 283 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 284 285 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 286 return (0); 287 288 ifp->if_timer = 0; /* turn watchdog timer off */ 289 290 PAGE(sc, 0); 291 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 292 /* Disable interrupt (Linux does it). */ 293 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 294 } 295 296 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 297 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 298 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 299 300 /* Check to see if card has been ejected. */ 301 if (isr == 0xff) { 302 #ifdef DIAGNOSTIC 303 printf("%s: interrupt for dead card\n", 304 device_xname(sc->sc_dev)); 305 #endif 306 goto end; 307 } 308 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 309 310 PAGE(sc, 0x40); 311 rx_status = 312 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 313 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 314 tx_status = 315 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 316 tx_status |= 317 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 318 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 319 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 320 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 321 tx_status)); 322 323 PAGE(sc, 0); 324 while (esr & FULL_PKT_RCV) { 325 if (!(rsr & RSR_RX_OK)) 326 break; 327 328 /* Compare bytes read this interrupt to hard maximum. */ 329 if (recvcount > MAX_BYTES_INTR) { 330 DPRINTF(XID_INTR, 331 ("xi: too many bytes this interrupt\n")); 332 ifp->if_iqdrops++; 333 /* Drop packet. */ 334 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 335 DO_SKIP_RX_PKT); 336 } 337 tempint = xi_get(sc); /* XXX doesn't check the error! */ 338 recvcount += tempint; 339 ifp->if_ibytes += tempint; 340 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 341 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 342 } 343 344 /* Packet too long? */ 345 if (rsr & RSR_TOO_LONG) { 346 ifp->if_ierrors++; 347 DPRINTF(XID_INTR, ("xi: packet too long\n")); 348 } 349 350 /* CRC error? */ 351 if (rsr & RSR_CRCERR) { 352 ifp->if_ierrors++; 353 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 354 } 355 356 /* Alignment error? */ 357 if (rsr & RSR_ALIGNERR) { 358 ifp->if_ierrors++; 359 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 360 } 361 362 /* Check for rx overrun. */ 363 if (rx_status & RX_OVERRUN) { 364 ifp->if_ierrors++; 365 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 366 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 367 } 368 369 /* Try to start more packets transmitting. */ 370 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 371 xi_start(ifp); 372 373 /* Detected excessive collisions? */ 374 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 375 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 376 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 377 ifp->if_oerrors++; 378 } 379 380 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 381 ifp->if_oerrors++; 382 383 /* have handled the interrupt */ 384 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 385 386 end: 387 /* Reenable interrupts. */ 388 PAGE(sc, 0); 389 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 390 391 return (1); 392 } 393 394 /* 395 * Pull a packet from the card into an mbuf chain. 396 */ 397 STATIC u_int16_t 398 xi_get(struct xi_softc *sc) 399 { 400 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 401 struct mbuf *top, **mp, *m; 402 u_int16_t pktlen, len, recvcount = 0; 403 u_int8_t *data; 404 405 DPRINTF(XID_CONFIG, ("xi_get()\n")); 406 407 PAGE(sc, 0); 408 pktlen = 409 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 410 411 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 412 413 if (pktlen == 0) { 414 /* 415 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 416 * when MPE is set. It is not known why. 417 */ 418 return (0); 419 } 420 421 /* XXX should this be incremented now ? */ 422 recvcount += pktlen; 423 424 MGETHDR(m, M_DONTWAIT, MT_DATA); 425 if (m == NULL) 426 return (recvcount); 427 m->m_pkthdr.rcvif = ifp; 428 m->m_pkthdr.len = pktlen; 429 len = MHLEN; 430 top = NULL; 431 mp = ⊤ 432 433 while (pktlen > 0) { 434 if (top) { 435 MGET(m, M_DONTWAIT, MT_DATA); 436 if (m == NULL) { 437 m_freem(top); 438 return (recvcount); 439 } 440 len = MLEN; 441 } 442 if (pktlen >= MINCLSIZE) { 443 MCLGET(m, M_DONTWAIT); 444 if (!(m->m_flags & M_EXT)) { 445 m_freem(m); 446 m_freem(top); 447 return (recvcount); 448 } 449 len = MCLBYTES; 450 } 451 if (top == NULL) { 452 char *newdata = (char *)ALIGN(m->m_data + 453 sizeof(struct ether_header)) - 454 sizeof(struct ether_header); 455 len -= newdata - m->m_data; 456 m->m_data = newdata; 457 } 458 len = min(pktlen, len); 459 data = mtod(m, u_int8_t *); 460 if (len > 1) { 461 len &= ~1; 462 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 463 (u_int16_t *)data, len>>1); 464 } else 465 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 466 m->m_len = len; 467 pktlen -= len; 468 *mp = m; 469 mp = &m->m_next; 470 } 471 472 /* Skip Rx packet. */ 473 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 474 475 if (top == NULL) 476 return recvcount; 477 478 /* Trim the CRC off the end of the packet. */ 479 m_adj(top, -ETHER_CRC_LEN); 480 481 ifp->if_ipackets++; 482 483 bpf_mtap(ifp, top); 484 485 (*ifp->if_input)(ifp, top); 486 return (recvcount); 487 } 488 489 /* 490 * Serial management for the MII. 491 * The DELAY's below stem from the fact that the maximum frequency 492 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 493 * go much faster than that. 494 */ 495 496 /* Let the MII serial management be idle for one period. */ 497 static INLINE void xi_mdi_idle(struct xi_softc *); 498 static INLINE void 499 xi_mdi_idle(struct xi_softc *sc) 500 { 501 bus_space_tag_t bst = sc->sc_bst; 502 bus_space_handle_t bsh = sc->sc_bsh; 503 504 /* Drive MDC low... */ 505 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 506 DELAY(1); 507 508 /* and high again. */ 509 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 510 DELAY(1); 511 } 512 513 /* Pulse out one bit of data. */ 514 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 515 static INLINE void 516 xi_mdi_pulse(struct xi_softc *sc, int data) 517 { 518 bus_space_tag_t bst = sc->sc_bst; 519 bus_space_handle_t bsh = sc->sc_bsh; 520 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 521 522 /* First latch the data bit MDIO with clock bit MDC low...*/ 523 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 524 DELAY(1); 525 526 /* then raise the clock again, preserving the data bit. */ 527 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 528 DELAY(1); 529 } 530 531 /* Probe one bit of data. */ 532 static INLINE int xi_mdi_probe(struct xi_softc *sc); 533 static INLINE int 534 xi_mdi_probe(struct xi_softc *sc) 535 { 536 bus_space_tag_t bst = sc->sc_bst; 537 bus_space_handle_t bsh = sc->sc_bsh; 538 u_int8_t x; 539 540 /* Pull clock bit MDCK low... */ 541 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 542 DELAY(1); 543 544 /* Read data and drive clock high again. */ 545 x = bus_space_read_1(bst, bsh, GP2); 546 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 547 DELAY(1); 548 549 return (x & MDIO); 550 } 551 552 /* Pulse out a sequence of data bits. */ 553 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 554 static INLINE void 555 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 556 { 557 u_int32_t mask; 558 559 for (mask = 1 << (len - 1); mask; mask >>= 1) 560 xi_mdi_pulse(sc, data & mask); 561 } 562 563 /* Read a PHY register. */ 564 STATIC int 565 xi_mdi_read(device_t self, int phy, int reg) 566 { 567 struct xi_softc *sc = device_private(self); 568 int i; 569 u_int32_t mask; 570 u_int32_t data = 0; 571 572 PAGE(sc, 2); 573 for (i = 0; i < 32; i++) /* Synchronize. */ 574 xi_mdi_pulse(sc, 1); 575 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 576 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 577 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 578 xi_mdi_idle(sc); /* Turn around. */ 579 xi_mdi_probe(sc); /* Drop initial zero bit. */ 580 581 for (mask = 1 << 15; mask; mask >>= 1) { 582 if (xi_mdi_probe(sc)) 583 data |= mask; 584 } 585 xi_mdi_idle(sc); 586 587 DPRINTF(XID_MII, 588 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 589 590 return (data); 591 } 592 593 /* Write a PHY register. */ 594 STATIC void 595 xi_mdi_write(device_t self, int phy, int reg, int value) 596 { 597 struct xi_softc *sc = device_private(self); 598 int i; 599 600 PAGE(sc, 2); 601 for (i = 0; i < 32; i++) /* Synchronize. */ 602 xi_mdi_pulse(sc, 1); 603 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 604 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 605 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 606 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 607 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 608 xi_mdi_idle(sc); /* Idle away. */ 609 610 DPRINTF(XID_MII, 611 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 612 } 613 614 STATIC void 615 xi_statchg(struct ifnet *ifp) 616 { 617 /* XXX Update ifp->if_baudrate */ 618 } 619 620 /* 621 * Change media according to request. 622 */ 623 STATIC int 624 xi_mediachange(struct ifnet *ifp) 625 { 626 int s; 627 628 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 629 630 if (ifp->if_flags & IFF_UP) { 631 s = splnet(); 632 xi_init(ifp->if_softc); 633 splx(s); 634 } 635 return (0); 636 } 637 638 STATIC void 639 xi_reset(struct xi_softc *sc) 640 { 641 int s; 642 643 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 644 645 s = splnet(); 646 xi_stop(sc); 647 xi_init(sc); 648 splx(s); 649 } 650 651 STATIC void 652 xi_watchdog(struct ifnet *ifp) 653 { 654 struct xi_softc *sc = ifp->if_softc; 655 656 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 657 ++ifp->if_oerrors; 658 659 xi_reset(sc); 660 } 661 662 STATIC void 663 xi_stop(register struct xi_softc *sc) 664 { 665 bus_space_tag_t bst = sc->sc_bst; 666 bus_space_handle_t bsh = sc->sc_bsh; 667 668 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 669 670 PAGE(sc, 0x40); 671 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 672 673 /* Disable interrupts. */ 674 PAGE(sc, 0); 675 bus_space_write_1(bst, bsh, CR, 0); 676 677 PAGE(sc, 1); 678 bus_space_write_1(bst, bsh, IMR0, 0); 679 680 /* Cancel watchdog timer. */ 681 sc->sc_ethercom.ec_if.if_timer = 0; 682 } 683 684 STATIC int 685 xi_enable(struct xi_softc *sc) 686 { 687 int error; 688 689 if (!sc->sc_enabled) { 690 error = (*sc->sc_enable)(sc); 691 if (error) 692 return (error); 693 sc->sc_enabled = 1; 694 xi_full_reset(sc); 695 } 696 return (0); 697 } 698 699 STATIC void 700 xi_disable(struct xi_softc *sc) 701 { 702 703 if (sc->sc_enabled) { 704 sc->sc_enabled = 0; 705 (*sc->sc_disable)(sc); 706 } 707 } 708 709 STATIC void 710 xi_init(struct xi_softc *sc) 711 { 712 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 713 bus_space_tag_t bst = sc->sc_bst; 714 bus_space_handle_t bsh = sc->sc_bsh; 715 716 DPRINTF(XID_CONFIG, ("xi_init()\n")); 717 718 /* Setup the ethernet interrupt mask. */ 719 PAGE(sc, 1); 720 bus_space_write_1(bst, bsh, IMR0, 721 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 722 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 723 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 724 /* XXX What is this? Not for Dingo at least. */ 725 /* Unmask TX underrun detection */ 726 bus_space_write_1(bst, bsh, IMR1, 1); 727 } 728 729 /* Enable interrupts. */ 730 PAGE(sc, 0); 731 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 732 733 xi_set_address(sc); 734 735 PAGE(sc, 0x40); 736 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 737 738 PAGE(sc, 0); 739 740 /* Set current media. */ 741 mii_mediachg(&sc->sc_mii); 742 743 ifp->if_flags |= IFF_RUNNING; 744 ifp->if_flags &= ~IFF_OACTIVE; 745 746 xi_start(ifp); 747 } 748 749 /* 750 * Start outputting on the interface. 751 * Always called as splnet(). 752 */ 753 STATIC void 754 xi_start(struct ifnet *ifp) 755 { 756 struct xi_softc *sc = ifp->if_softc; 757 bus_space_tag_t bst = sc->sc_bst; 758 bus_space_handle_t bsh = sc->sc_bsh; 759 unsigned int s, len, pad = 0; 760 struct mbuf *m0, *m; 761 u_int16_t space; 762 763 DPRINTF(XID_CONFIG, ("xi_start()\n")); 764 765 /* Don't transmit if interface is busy or not running. */ 766 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 767 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 768 return; 769 } 770 771 /* Peek at the next packet. */ 772 IFQ_POLL(&ifp->if_snd, m0); 773 if (m0 == 0) 774 return; 775 776 /* We need to use m->m_pkthdr.len, so require the header. */ 777 if (!(m0->m_flags & M_PKTHDR)) 778 panic("xi_start: no header mbuf"); 779 780 len = m0->m_pkthdr.len; 781 782 #if 1 783 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 784 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 785 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 786 #else 787 pad = 0; 788 #endif 789 790 PAGE(sc, 0); 791 792 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 793 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 794 if (len + pad + 2 > space) { 795 DPRINTF(XID_FIFO, 796 ("xi: not enough space in output FIFO (%d > %d)\n", 797 len + pad + 2, space)); 798 return; 799 } 800 801 IFQ_DEQUEUE(&ifp->if_snd, m0); 802 803 bpf_mtap(ifp, m0); 804 805 /* 806 * Do the output at splhigh() so that an interrupt from another device 807 * won't cause a FIFO underrun. 808 */ 809 s = splhigh(); 810 811 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 812 for (m = m0; m; ) { 813 if (m->m_len > 1) 814 bus_space_write_multi_2(bst, bsh, EDP, 815 mtod(m, u_int16_t *), m->m_len>>1); 816 if (m->m_len & 1) { 817 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 818 bus_space_write_1(bst, bsh, EDP, 819 *(mtod(m, u_int8_t *) + m->m_len - 1)); 820 } 821 MFREE(m, m0); 822 m = m0; 823 } 824 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 825 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 826 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 827 else { 828 for (; pad > 1; pad -= 2) 829 bus_space_write_2(bst, bsh, EDP, 0); 830 if (pad == 1) 831 bus_space_write_1(bst, bsh, EDP, 0); 832 } 833 834 splx(s); 835 836 ifp->if_timer = 5; 837 ++ifp->if_opackets; 838 } 839 840 STATIC int 841 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 842 { 843 struct ifaddr *ifa = (struct ifaddr *)data; 844 struct xi_softc *sc = ifp->if_softc; 845 int error; 846 847 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 848 849 switch (cmd) { 850 case SIOCINITIFADDR: 851 if ((error = xi_enable(sc)) != 0) 852 break; 853 854 ifp->if_flags |= IFF_UP; 855 856 xi_init(sc); 857 switch (ifa->ifa_addr->sa_family) { 858 #ifdef INET 859 case AF_INET: 860 arp_ifinit(ifp, ifa); 861 break; 862 #endif /* INET */ 863 864 865 default: 866 break; 867 } 868 break; 869 870 default: 871 return (EINVAL); 872 } 873 874 return (0); 875 } 876 877 STATIC int 878 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 879 { 880 struct xi_softc *sc = ifp->if_softc; 881 int s, error = 0; 882 883 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 884 885 s = splnet(); 886 887 switch (cmd) { 888 case SIOCINITIFADDR: 889 error = xi_ether_ioctl(ifp, cmd, data); 890 break; 891 892 case SIOCSIFFLAGS: 893 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 894 break; 895 /* XXX re-use ether_ioctl() */ 896 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 897 case IFF_RUNNING: 898 /* 899 * If interface is marked down and it is running, 900 * stop it. 901 */ 902 xi_stop(sc); 903 ifp->if_flags &= ~IFF_RUNNING; 904 xi_disable(sc); 905 break; 906 case IFF_UP: 907 /* 908 * If interface is marked up and it is stopped, 909 * start it. 910 */ 911 if ((error = xi_enable(sc)) != 0) 912 break; 913 xi_init(sc); 914 break; 915 case IFF_UP|IFF_RUNNING: 916 /* 917 * Reset the interface to pick up changes in any 918 * other flags that affect hardware registers. 919 */ 920 xi_set_address(sc); 921 break; 922 case 0: 923 break; 924 } 925 break; 926 927 case SIOCADDMULTI: 928 case SIOCDELMULTI: 929 if (sc->sc_enabled == 0) { 930 error = EIO; 931 break; 932 } 933 /*FALLTHROUGH*/ 934 case SIOCSIFMEDIA: 935 case SIOCGIFMEDIA: 936 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 937 /* 938 * Multicast list has changed; set the hardware 939 * filter accordingly. 940 */ 941 if (ifp->if_flags & IFF_RUNNING) 942 xi_set_address(sc); 943 error = 0; 944 } 945 break; 946 947 default: 948 error = ether_ioctl(ifp, cmd, data); 949 break; 950 } 951 952 splx(s); 953 return (error); 954 } 955 956 STATIC void 957 xi_set_address(struct xi_softc *sc) 958 { 959 bus_space_tag_t bst = sc->sc_bst; 960 bus_space_handle_t bsh = sc->sc_bsh; 961 struct ethercom *ether = &sc->sc_ethercom; 962 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 963 struct ether_multistep step; 964 struct ether_multi *enm; 965 int page, num; 966 int i; 967 u_int8_t x; 968 const u_int8_t *enaddr; 969 u_int8_t indaddr[64]; 970 971 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 972 973 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 974 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 975 for (i = 0; i < 6; i++) 976 indaddr[i] = enaddr[5 - i]; 977 else 978 for (i = 0; i < 6; i++) 979 indaddr[i] = enaddr[i]; 980 num = 1; 981 982 if (ether->ec_multicnt > 9) { 983 ifp->if_flags |= IFF_ALLMULTI; 984 goto done; 985 } 986 987 ETHER_FIRST_MULTI(step, ether, enm); 988 for (; enm; num++) { 989 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 990 sizeof(enm->enm_addrlo)) != 0) { 991 /* 992 * The multicast address is really a range; 993 * it's easier just to accept all multicasts. 994 * XXX should we be setting IFF_ALLMULTI here? 995 */ 996 ifp->if_flags |= IFF_ALLMULTI; 997 goto done; 998 } 999 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1000 for (i = 0; i < 6; i++) 1001 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1002 else 1003 for (i = 0; i < 6; i++) 1004 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1005 ETHER_NEXT_MULTI(step, enm); 1006 } 1007 ifp->if_flags &= ~IFF_ALLMULTI; 1008 1009 done: 1010 if (num < 10) 1011 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1012 1013 for (page = 0; page < 8; page++) { 1014 #ifdef XIDEBUG 1015 if (xidebug & XID_MCAST) { 1016 printf("page %d before:", page); 1017 for (i = 0; i < 8; i++) 1018 printf(" %02x", indaddr[page * 8 + i]); 1019 printf("\n"); 1020 } 1021 #endif 1022 1023 PAGE(sc, 0x50 + page); 1024 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1025 page == 7 ? 4 : 8); 1026 /* 1027 * XXX 1028 * Without this delay, the address registers on my CE2 get 1029 * trashed the first and I have to cycle it. I have no idea 1030 * why. - mycroft, 2004/08/09 1031 */ 1032 DELAY(50); 1033 1034 #ifdef XIDEBUG 1035 if (xidebug & XID_MCAST) { 1036 bus_space_read_region_1(bst, bsh, IA, 1037 &indaddr[page * 8], page == 7 ? 4 : 8); 1038 printf("page %d after: ", page); 1039 for (i = 0; i < 8; i++) 1040 printf(" %02x", indaddr[page * 8 + i]); 1041 printf("\n"); 1042 } 1043 #endif 1044 } 1045 1046 PAGE(sc, 0x42); 1047 x = SWC1_IND_ADDR; 1048 if (ifp->if_flags & IFF_PROMISC) 1049 x |= SWC1_PROMISC; 1050 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1051 x |= SWC1_MCAST_PROM; 1052 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1053 x |= SWC1_AUTO_MEDIA; 1054 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1055 } 1056 1057 STATIC void 1058 xi_cycle_power(struct xi_softc *sc) 1059 { 1060 bus_space_tag_t bst = sc->sc_bst; 1061 bus_space_handle_t bsh = sc->sc_bsh; 1062 1063 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1064 1065 PAGE(sc, 4); 1066 DELAY(1); 1067 bus_space_write_1(bst, bsh, GP1, 0); 1068 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1069 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1070 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1071 else 1072 /* XXX What is bit 2 (aka AIC)? */ 1073 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1074 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1075 } 1076 1077 STATIC void 1078 xi_full_reset(struct xi_softc *sc) 1079 { 1080 bus_space_tag_t bst = sc->sc_bst; 1081 bus_space_handle_t bsh = sc->sc_bsh; 1082 u_int8_t x; 1083 1084 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1085 1086 /* Do an as extensive reset as possible on all functions. */ 1087 xi_cycle_power(sc); 1088 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1089 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1090 bus_space_write_1(bst, bsh, CR, 0); 1091 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1092 PAGE(sc, 4); 1093 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1094 /* 1095 * Drive GP1 low to power up ML6692 and GP2 high to power up 1096 * the 10MHz chip. XXX What chip is that? The phy? 1097 */ 1098 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1099 } 1100 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1101 1102 /* Get revision information. XXX Symbolic constants. */ 1103 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1104 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1105 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1106 1107 /* Media selection. XXX Maybe manual overriding too? */ 1108 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1109 /* 1110 * XXX I have no idea what this really does, it is from the 1111 * Linux driver. 1112 */ 1113 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1114 } 1115 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1116 1117 /* 1118 * Disable source insertion. 1119 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1120 */ 1121 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1122 PAGE(sc, 0x42); 1123 bus_space_write_1(bst, bsh, SWC0, 0x20); 1124 } 1125 1126 /* Set the local memory dividing line. */ 1127 if (sc->sc_rev != 1) { 1128 PAGE(sc, 2); 1129 /* XXX Symbolic constant preferrable. */ 1130 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1131 } 1132 1133 /* 1134 * Apparently the receive byte pointer can be bad after a reset, so 1135 * we hardwire it correctly. 1136 */ 1137 PAGE(sc, 0); 1138 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1139 1140 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1141 PAGE(sc, 0x40); 1142 bus_space_write_1(bst, bsh, RX0MSK, 1143 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1144 bus_space_write_1(bst, bsh, TX0MSK, 1145 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1146 SQE | TX_ABORT | TX_OK); 1147 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1148 /* XXX From Linux, dunno what 0xb0 means. */ 1149 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1150 bus_space_write_1(bst, bsh, RXST0, 0); 1151 bus_space_write_1(bst, bsh, TXST0, 0); 1152 bus_space_write_1(bst, bsh, TXST1, 0); 1153 1154 PAGE(sc, 2); 1155 1156 /* Enable MII function if available. */ 1157 x = 0; 1158 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1159 x |= SELECT_MII; 1160 bus_space_write_1(bst, bsh, MSR, x); 1161 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1162 1163 /* Configure the LED registers. */ 1164 /* XXX This is not good for 10base2. */ 1165 bus_space_write_1(bst, bsh, LED, 1166 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1167 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1168 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1169 1170 /* 1171 * The Linux driver says this: 1172 * We should switch back to page 0 to avoid a bug in revision 0 1173 * where regs with offset below 8 can't be read after an access 1174 * to the MAC registers. 1175 */ 1176 PAGE(sc, 0); 1177 } 1178