1 /* $NetBSD: if_xi.c,v 1.14 2001/07/07 16:51:47 thorpej Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include "opt_inet.h" 52 #include "bpfilter.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/device.h> 57 #include <sys/ioctl.h> 58 #include <sys/mbuf.h> 59 #include <sys/malloc.h> 60 #include <sys/socket.h> 61 62 #include "rnd.h" 63 #if NRND > 0 64 #include <sys/rnd.h> 65 #endif 66 67 #include <net/if.h> 68 #include <net/if_dl.h> 69 #include <net/if_media.h> 70 #include <net/if_types.h> 71 #include <net/if_ether.h> 72 73 #ifdef INET 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/in_var.h> 77 #include <netinet/ip.h> 78 #include <netinet/if_inarp.h> 79 #endif 80 81 #ifdef IPX 82 #include <netipx/ipx.h> 83 #include <netipx/ipx_if.h> 84 #endif 85 86 #ifdef NS 87 #include <netns/ns.h> 88 #include <netns/ns_if.h> 89 #endif 90 91 #if NBPFILTER > 0 92 #include <net/bpf.h> 93 #include <net/bpfdesc.h> 94 #endif 95 96 #define ETHER_MIN_LEN 64 97 #define ETHER_CRC_LEN 4 98 99 /* 100 * Maximum number of bytes to read per interrupt. Linux recommends 101 * somewhere between 2000-22000. 102 * XXX This is currently a hard maximum. 103 */ 104 #define MAX_BYTES_INTR 12000 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/pcmcia/pcmciareg.h> 110 #include <dev/pcmcia/pcmciavar.h> 111 #include <dev/pcmcia/pcmciadevs.h> 112 113 #include <dev/pcmcia/if_xireg.h> 114 115 #ifdef __GNUC__ 116 #define INLINE __inline 117 #else 118 #define INLINE 119 #endif /* __GNUC__ */ 120 121 #ifdef XIDEBUG 122 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 123 124 #define XID_CONFIG 0x1 125 #define XID_MII 0x2 126 #define XID_INTR 0x4 127 #define XID_FIFO 0x8 128 129 #ifdef XIDEBUG_VALUE 130 int xidebug = XIDEBUG_VALUE; 131 #else 132 int xidebug = 0; 133 #endif 134 #else 135 #define DPRINTF(cat, x) (void)0 136 #endif 137 138 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 139 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 140 int xi_pcmcia_detach __P((struct device *, int)); 141 int xi_pcmcia_activate __P((struct device *, enum devact)); 142 143 /* 144 * In case this chipset ever turns up out of pcmcia attachments (very 145 * unlikely) do the driver splitup. 146 */ 147 struct xi_softc { 148 struct device sc_dev; /* Generic device info */ 149 struct ethercom sc_ethercom; /* Ethernet common part */ 150 151 struct mii_data sc_mii; /* MII media information */ 152 153 bus_space_tag_t sc_bst; /* Bus cookie */ 154 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 155 bus_addr_t sc_offset; /* Offset of registers */ 156 157 u_int8_t sc_rev; /* Chip revision */ 158 u_int32_t sc_flags; /* Misc. flags */ 159 int sc_all_mcasts; /* Receive all multicasts */ 160 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 161 #if NRND > 0 162 rndsource_element_t sc_rnd_source; 163 #endif 164 }; 165 166 struct xi_pcmcia_softc { 167 struct xi_softc sc_xi; /* Generic device info */ 168 169 /* PCMCIA-specific goo */ 170 struct pcmcia_function *sc_pf; /* PCMCIA function */ 171 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 172 int sc_io_window; /* io window info */ 173 void *sc_ih; /* Interrupt handler */ 174 void *sc_powerhook; /* power hook descriptor */ 175 int sc_resource; /* resource allocated */ 176 #define XI_RES_PCIC 1 177 #define XI_RES_IO_ALLOC 2 178 #define XI_RES_IO_MAP 4 179 #define XI_RES_MI 8 180 }; 181 182 struct cfattach xi_pcmcia_ca = { 183 sizeof(struct xi_pcmcia_softc), 184 xi_pcmcia_match, 185 xi_pcmcia_attach, 186 xi_pcmcia_detach, 187 xi_pcmcia_activate 188 }; 189 190 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 191 static void xi_cycle_power __P((struct xi_softc *)); 192 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 193 static void xi_full_reset __P((struct xi_softc *)); 194 static void xi_init __P((struct xi_softc *)); 195 static int xi_intr __P((void *)); 196 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 197 static int xi_mdi_read __P((struct device *, int, int)); 198 static void xi_mdi_write __P((struct device *, int, int, int)); 199 static int xi_mediachange __P((struct ifnet *)); 200 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 201 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 202 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 203 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 204 static u_int16_t xi_get __P((struct xi_softc *)); 205 static void xi_reset __P((struct xi_softc *)); 206 static void xi_set_address __P((struct xi_softc *)); 207 static void xi_start __P((struct ifnet *)); 208 static void xi_statchg __P((struct device *)); 209 static void xi_stop __P((struct xi_softc *)); 210 static void xi_watchdog __P((struct ifnet *)); 211 const struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 212 struct pcmcia_attach_args *)); 213 static int xi_pcmcia_enable __P((struct xi_pcmcia_softc *)); 214 static void xi_pcmcia_disable __P((struct xi_pcmcia_softc *)); 215 static void xi_pcmcia_power __P((int, void *)); 216 217 /* flags */ 218 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 219 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 220 #define XIFLAGS_MODEM 0x004 /* modem also present */ 221 222 const struct xi_pcmcia_product { 223 u_int32_t xpp_vendor; /* vendor ID */ 224 u_int32_t xpp_product; /* product ID */ 225 int xpp_expfunc; /* expected function number */ 226 int xpp_flags; /* initial softc flags */ 227 const char *xpp_name; /* device name */ 228 } xi_pcmcia_products[] = { 229 #ifdef NOT_SUPPORTED 230 { PCMCIA_VENDOR_XIRCOM, 0x0141, 231 0, 0, 232 PCMCIA_STR_XIRCOM_CE }, 233 #endif 234 { PCMCIA_VENDOR_XIRCOM, 0x0141, 235 0, 0, 236 PCMCIA_STR_XIRCOM_CE2 }, 237 { PCMCIA_VENDOR_XIRCOM, 0x0142, 238 0, 0, 239 PCMCIA_STR_XIRCOM_CE2 }, 240 { PCMCIA_VENDOR_XIRCOM, 0x0143, 241 0, XIFLAGS_MOHAWK, 242 PCMCIA_STR_XIRCOM_CE3 }, 243 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 244 0, XIFLAGS_MOHAWK, 245 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 246 { PCMCIA_VENDOR_INTEL, 0x0143, 247 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 248 PCMCIA_STR_INTEL_EEPRO100 }, 249 #ifdef NOT_SUPPORTED 250 { PCMCIA_VENDOR_XIRCOM, 0x1141, 251 0, XIFLAGS_MODEM, 252 PCMCIA_STR_XIRCOM_CEM }, 253 #endif 254 { PCMCIA_VENDOR_XIRCOM, 0x1142, 255 0, XIFLAGS_MODEM, 256 PCMCIA_STR_XIRCOM_CEM }, 257 { PCMCIA_VENDOR_XIRCOM, 0x1143, 258 0, XIFLAGS_MODEM, 259 PCMCIA_STR_XIRCOM_CEM }, 260 { PCMCIA_VENDOR_XIRCOM, 0x1144, 261 0, XIFLAGS_MODEM, 262 PCMCIA_STR_XIRCOM_CEM33 }, 263 { PCMCIA_VENDOR_XIRCOM, 0x1145, 264 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 265 PCMCIA_STR_XIRCOM_CEM56 }, 266 { PCMCIA_VENDOR_XIRCOM, 0x1146, 267 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 268 PCMCIA_STR_XIRCOM_REM56 }, 269 { PCMCIA_VENDOR_XIRCOM, 0x1147, 270 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 271 PCMCIA_STR_XIRCOM_REM56 }, 272 { 0, 0, 273 0, 0, 274 NULL }, 275 }; 276 277 278 const struct xi_pcmcia_product * 279 xi_pcmcia_identify(dev, pa) 280 struct device *dev; 281 struct pcmcia_attach_args *pa; 282 { 283 const struct xi_pcmcia_product *xpp; 284 u_int8_t id; 285 u_int32_t prod; 286 287 /* 288 * The Xircom ethernet cards swap the revision and product fields 289 * inside the CIS, which makes identification just a little 290 * bit different. 291 */ 292 293 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 294 295 prod = (pa->product & ~0xff) | id; 296 297 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 298 299 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 300 if (pa->manufacturer == xpp->xpp_vendor && 301 prod == xpp->xpp_product && 302 pa->pf->number == xpp->xpp_expfunc) 303 return (xpp); 304 return (NULL); 305 } 306 307 /* 308 * The quirks are done here instead of the traditional framework because 309 * of the difficulty in identifying the devices. 310 */ 311 static int 312 xi_pcmcia_cis_quirks(pf) 313 struct pcmcia_function *pf; 314 { 315 struct pcmcia_config_entry *cfe; 316 317 /* Tell the pcmcia framework where the CCR is. */ 318 pf->ccr_base = 0x800; 319 pf->ccr_mask = 0x67; 320 321 /* Fake a cfe. */ 322 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 323 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT); 324 325 if (cfe == NULL) 326 return -1; 327 memset(cfe, 0, sizeof(*cfe)); 328 329 /* 330 * XXX Use preprocessor symbols instead. 331 * Enable ethernet & its interrupts, wiring them to -INT 332 * No I/O base. 333 */ 334 cfe->number = 0x5; 335 cfe->flags = 0; /* XXX Check! */ 336 cfe->iftype = PCMCIA_IFTYPE_IO; 337 cfe->num_iospace = 0; 338 cfe->num_memspace = 0; 339 cfe->irqmask = 0x8eb0; 340 341 return 0; 342 } 343 344 int 345 xi_pcmcia_match(parent, match, aux) 346 struct device *parent; 347 struct cfdata *match; 348 void *aux; 349 { 350 struct pcmcia_attach_args *pa = aux; 351 352 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 353 return (0); 354 355 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 356 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 357 return (1); 358 359 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 360 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 361 return (1); 362 363 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 364 ((pa->product >> 8) == XIMEDIA_ETHER || 365 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 366 return (1); 367 368 return (0); 369 } 370 371 void 372 xi_pcmcia_attach(parent, self, aux) 373 struct device *parent, *self; 374 void *aux; 375 { 376 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 377 struct xi_softc *sc = &psc->sc_xi; 378 struct pcmcia_attach_args *pa = aux; 379 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 380 const struct xi_pcmcia_product *xpp; 381 382 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 383 printf(": function enable failed\n"); 384 return; 385 } 386 387 /* Enable the card */ 388 psc->sc_pf = pa->pf; 389 pcmcia_function_init(psc->sc_pf, psc->sc_pf->cfe_head.sqh_first); 390 if (pcmcia_function_enable(psc->sc_pf)) { 391 printf(": function enable failed\n"); 392 goto fail; 393 } 394 psc->sc_resource |= XI_RES_PCIC; 395 396 /* allocate/map ISA I/O space */ 397 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZE, XI_IOSIZE, 398 &psc->sc_pcioh) != 0) { 399 printf(": I/O allocation failed\n"); 400 goto fail; 401 } 402 psc->sc_resource |= XI_RES_IO_ALLOC; 403 404 sc->sc_bst = psc->sc_pcioh.iot; 405 sc->sc_bsh = psc->sc_pcioh.ioh; 406 sc->sc_offset = 0; 407 408 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_AUTO, 0, XI_IOSIZE, 409 &psc->sc_pcioh, &psc->sc_io_window)) { 410 printf(": can't map I/O space\n"); 411 goto fail; 412 } 413 psc->sc_resource |= XI_RES_IO_MAP; 414 415 /* 416 * Configuration as advised by DINGO documentation. 417 * Dingo has some extra configuration registers in the CCR space. 418 */ 419 if (sc->sc_flags & XIFLAGS_DINGO) { 420 struct pcmcia_mem_handle pcmh; 421 int ccr_window; 422 bus_addr_t ccr_offset; 423 424 /* get access to the DINGO CCR space */ 425 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 426 &pcmh)) { 427 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 428 goto fail; 429 } 430 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 431 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 432 &pcmh, &ccr_offset, &ccr_window)) { 433 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 434 pcmcia_mem_free(psc->sc_pf, &pcmh); 435 goto fail; 436 } 437 438 /* enable the second function - usually modem */ 439 bus_space_write_1(pcmh.memt, pcmh.memh, 440 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 441 bus_space_write_1(pcmh.memt, pcmh.memh, 442 ccr_offset + PCMCIA_CCR_DCOR1, 443 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 444 bus_space_write_1(pcmh.memt, pcmh.memh, 445 ccr_offset + PCMCIA_CCR_DCOR2, 0); 446 bus_space_write_1(pcmh.memt, pcmh.memh, 447 ccr_offset + PCMCIA_CCR_DCOR3, 0); 448 bus_space_write_1(pcmh.memt, pcmh.memh, 449 ccr_offset + PCMCIA_CCR_DCOR4, 0); 450 451 /* We don't need them anymore and can free them (I think). */ 452 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 453 pcmcia_mem_free(psc->sc_pf, &pcmh); 454 } 455 456 xpp = xi_pcmcia_identify(parent,pa); 457 if (xpp == NULL) { 458 printf(": unrecognised model\n"); 459 return; 460 } 461 sc->sc_flags = xpp->xpp_flags; 462 463 printf(": %s\n", xpp->xpp_name); 464 465 /* 466 * Get the ethernet address from FUNCE/LAN_NID tuple. 467 */ 468 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 469 if (!sc->sc_enaddr) { 470 printf("%s: unable to get ethernet address\n", 471 sc->sc_dev.dv_xname); 472 goto fail; 473 } 474 475 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 476 ether_sprintf(sc->sc_enaddr)); 477 478 ifp = &sc->sc_ethercom.ec_if; 479 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 480 ifp->if_softc = sc; 481 ifp->if_start = xi_start; 482 ifp->if_ioctl = xi_ioctl; 483 ifp->if_watchdog = xi_watchdog; 484 ifp->if_flags = 485 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 486 IFQ_SET_READY(&ifp->if_snd); 487 488 /* Reset and initialize the card. */ 489 xi_full_reset(sc); 490 491 /* 492 * Initialize our media structures and probe the MII. 493 */ 494 sc->sc_mii.mii_ifp = ifp; 495 sc->sc_mii.mii_readreg = xi_mdi_read; 496 sc->sc_mii.mii_writereg = xi_mdi_write; 497 sc->sc_mii.mii_statchg = xi_statchg; 498 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 499 xi_mediastatus); 500 DPRINTF(XID_MII | XID_CONFIG, 501 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 502 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 503 MII_OFFSET_ANY, 0); 504 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 505 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 506 NULL); 507 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 508 509 /* 802.1q capability */ 510 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 511 /* Attach the interface. */ 512 if_attach(ifp); 513 ether_ifattach(ifp, sc->sc_enaddr); 514 psc->sc_resource |= XI_RES_MI; 515 516 #if NRND > 0 517 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 518 RND_TYPE_NET, 0); 519 #endif 520 521 /* 522 * Reset and initialize the card again for DINGO (as found in Linux 523 * driver). Without this Dingo will get a watchdog timeout the first 524 * time. The ugly media tickling seems to be necessary for getting 525 * autonegotiation to work too. 526 */ 527 if (sc->sc_flags & XIFLAGS_DINGO) { 528 xi_full_reset(sc); 529 xi_init(sc); 530 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 531 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 532 xi_stop(sc); 533 } 534 535 psc->sc_powerhook = powerhook_establish(xi_pcmcia_power, sc); 536 537 pcmcia_function_disable(psc->sc_pf); 538 psc->sc_resource &= ~XI_RES_PCIC; 539 540 return; 541 542 fail: 543 if ((psc->sc_resource & XI_RES_IO_MAP) != 0) { 544 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 545 psc->sc_resource &= ~XI_RES_IO_MAP; 546 } 547 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 548 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 549 psc->sc_resource &= ~XI_RES_IO_ALLOC; 550 } 551 if (psc->sc_resource & XI_RES_PCIC) { 552 pcmcia_function_disable(pa->pf); 553 psc->sc_resource &= ~XI_RES_PCIC; 554 } 555 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 556 } 557 558 int 559 xi_pcmcia_detach(self, flags) 560 struct device *self; 561 int flags; 562 { 563 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 564 struct xi_softc *sc = &psc->sc_xi; 565 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 566 567 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 568 569 if (psc->sc_powerhook != NULL) 570 powerhook_disestablish(psc->sc_powerhook); 571 572 #if NRND > 0 573 rnd_detach_source(&sc->sc_rnd_source); 574 #endif 575 576 if ((psc->sc_resource & XI_RES_MI) != 0) { 577 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 578 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 579 ether_ifdetach(ifp); 580 if_detach(ifp); 581 psc->sc_resource &= ~XI_RES_MI; 582 } 583 if (psc->sc_resource & XI_RES_IO_MAP) { 584 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 585 psc->sc_resource &= ~XI_RES_IO_MAP; 586 } 587 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 588 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 589 psc->sc_resource &= ~XI_RES_IO_ALLOC; 590 } 591 592 xi_pcmcia_disable(psc); 593 594 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 595 596 return 0; 597 } 598 599 int 600 xi_pcmcia_activate(self, act) 601 struct device *self; 602 enum devact act; 603 { 604 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 605 struct xi_softc *sc = &psc->sc_xi; 606 int s, rv=0; 607 608 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 609 610 s = splnet(); 611 switch (act) { 612 case DVACT_ACTIVATE: 613 rv = EOPNOTSUPP; 614 break; 615 616 case DVACT_DEACTIVATE: 617 if_deactivate(&sc->sc_ethercom.ec_if); 618 break; 619 } 620 splx(s); 621 return (rv); 622 } 623 624 static int 625 xi_pcmcia_enable(psc) 626 struct xi_pcmcia_softc *psc; 627 { 628 struct xi_softc *sc = &psc->sc_xi; 629 630 DPRINTF(XID_CONFIG,("xi_pcmcia_enable()\n")); 631 632 /* establish the interrupt. */ 633 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 634 if (psc->sc_ih == NULL) { 635 printf("%s: couldn't establish interrupt\n", 636 sc->sc_dev.dv_xname); 637 return (1); 638 } 639 640 if (pcmcia_function_enable(psc->sc_pf)) { 641 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 642 return (1); 643 } 644 psc->sc_resource |= XI_RES_PCIC; 645 646 xi_full_reset(sc); 647 648 return (0); 649 } 650 651 652 static void 653 xi_pcmcia_disable(psc) 654 struct xi_pcmcia_softc *psc; 655 { 656 DPRINTF(XID_CONFIG,("xi_pcmcia_disable()\n")); 657 658 if (psc->sc_resource & XI_RES_PCIC) { 659 pcmcia_function_disable(psc->sc_pf); 660 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 661 psc->sc_resource &= ~XI_RES_PCIC; 662 } 663 } 664 665 666 static void 667 xi_pcmcia_power(why, arg) 668 int why; 669 void *arg; 670 { 671 struct xi_pcmcia_softc *psc = arg; 672 struct xi_softc *sc = &psc->sc_xi; 673 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 674 int s; 675 676 DPRINTF(XID_CONFIG,("xi_pcmcia_power()\n")); 677 678 s = splnet(); 679 680 switch (why) { 681 case PWR_SUSPEND: 682 case PWR_STANDBY: 683 if (ifp->if_flags & IFF_RUNNING) { 684 xi_stop(sc); 685 } 686 ifp->if_flags &= ~IFF_RUNNING; 687 ifp->if_timer = 0; 688 break; 689 case PWR_RESUME: 690 if ((ifp->if_flags & IFF_RUNNING) == 0) { 691 xi_init(sc); 692 } 693 ifp->if_flags |= IFF_RUNNING; 694 break; 695 case PWR_SOFTSUSPEND: 696 case PWR_SOFTSTANDBY: 697 case PWR_SOFTRESUME: 698 break; 699 } 700 splx(s); 701 } 702 703 /* 704 * XXX These two functions might be OK to factor out into pcmcia.c since 705 * if_sm_pcmcia.c uses similar ones. 706 */ 707 static int 708 xi_pcmcia_funce_enaddr(parent, myla) 709 struct device *parent; 710 u_int8_t *myla; 711 { 712 /* XXX The Linux driver has more ways to do this in case of failure. */ 713 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 714 } 715 716 static int 717 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 718 struct pcmcia_tuple *tuple; 719 void *arg; 720 { 721 u_int8_t *myla = arg; 722 int i; 723 724 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 725 726 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 727 if (tuple->length < 2) 728 return (0); 729 730 switch (pcmcia_tuple_read_1(tuple, 0)) { 731 case PCMCIA_TPLFE_TYPE_LAN_NID: 732 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 733 return (0); 734 break; 735 736 case 0x02: 737 /* 738 * Not sure about this, I don't have a CE2 739 * that puts the ethernet addr here. 740 */ 741 if (pcmcia_tuple_read_1(tuple, 1) != 13) 742 return (0); 743 break; 744 745 default: 746 return (0); 747 } 748 749 for (i = 0; i < ETHER_ADDR_LEN; i++) 750 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 751 return (1); 752 } 753 754 /* Yet another spot where this might be. */ 755 if (tuple->code == 0x89) { 756 pcmcia_tuple_read_1(tuple, 1); 757 for (i = 0; i < ETHER_ADDR_LEN; i++) 758 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 759 return (1); 760 } 761 return (0); 762 } 763 764 int 765 xi_pcmcia_manfid_ciscallback(tuple, arg) 766 struct pcmcia_tuple *tuple; 767 void *arg; 768 { 769 u_int8_t *id = arg; 770 771 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 772 773 if (tuple->code != PCMCIA_CISTPL_MANFID) 774 return (0); 775 776 if (tuple->length < 2) 777 return (0); 778 779 *id = pcmcia_tuple_read_1(tuple, 4); 780 return (1); 781 } 782 783 static int 784 xi_intr(arg) 785 void *arg; 786 { 787 struct xi_softc *sc = arg; 788 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 789 u_int8_t esr, rsr, isr, rx_status, savedpage; 790 u_int16_t tx_status, recvcount = 0, tempint; 791 792 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 793 794 #if 0 795 if (!(ifp->if_flags & IFF_RUNNING)) 796 return (0); 797 #endif 798 799 ifp->if_timer = 0; /* turn watchdog timer off */ 800 801 if (sc->sc_flags & XIFLAGS_MOHAWK) { 802 /* Disable interrupt (Linux does it). */ 803 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 804 0); 805 } 806 807 savedpage = 808 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 809 810 PAGE(sc, 0); 811 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 812 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 813 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 814 815 /* Check to see if card has been ejected. */ 816 if (isr == 0xff) { 817 #ifdef DIAGNOSTIC 818 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 819 #endif 820 goto end; 821 } 822 823 PAGE(sc, 40); 824 rx_status = 825 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 826 tx_status = 827 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 828 829 /* 830 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine 831 * without it, and I can't see an obvious reason for it. 832 */ 833 834 PAGE(sc, 0); 835 while (esr & FULL_PKT_RCV) { 836 if (!(rsr & RSR_RX_OK)) 837 break; 838 839 /* Compare bytes read this interrupt to hard maximum. */ 840 if (recvcount > MAX_BYTES_INTR) { 841 DPRINTF(XID_INTR, 842 ("xi: too many bytes this interrupt\n")); 843 ifp->if_iqdrops++; 844 /* Drop packet. */ 845 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 846 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 847 } 848 tempint = xi_get(sc); /* XXX doesn't check the error! */ 849 recvcount += tempint; 850 ifp->if_ibytes += tempint; 851 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 852 sc->sc_offset + ESR); 853 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 854 sc->sc_offset + RSR); 855 } 856 857 /* Packet too long? */ 858 if (rsr & RSR_TOO_LONG) { 859 ifp->if_ierrors++; 860 DPRINTF(XID_INTR, ("xi: packet too long\n")); 861 } 862 863 /* CRC error? */ 864 if (rsr & RSR_CRCERR) { 865 ifp->if_ierrors++; 866 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 867 } 868 869 /* Alignment error? */ 870 if (rsr & RSR_ALIGNERR) { 871 ifp->if_ierrors++; 872 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 873 } 874 875 /* Check for rx overrun. */ 876 if (rx_status & RX_OVERRUN) { 877 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 878 CLR_RX_OVERRUN); 879 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 880 } 881 882 /* Try to start more packets transmitting. */ 883 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 884 xi_start(ifp); 885 886 /* Detected excessive collisions? */ 887 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 888 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 889 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 890 RESTART_TX); 891 ifp->if_oerrors++; 892 } 893 894 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 895 ifp->if_oerrors++; 896 897 end: 898 /* Reenable interrupts. */ 899 PAGE(sc, savedpage); 900 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 901 ENABLE_INT); 902 903 /* have handled the interrupt */ 904 #if NRND > 0 905 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 906 #endif 907 908 return (1); 909 } 910 911 /* 912 * Pull a packet from the card into an mbuf chain. 913 */ 914 static u_int16_t 915 xi_get(sc) 916 struct xi_softc *sc; 917 { 918 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 919 struct mbuf *top, **mp, *m; 920 u_int16_t pktlen, len, recvcount = 0; 921 u_int8_t *data; 922 u_int8_t rsr; 923 924 DPRINTF(XID_CONFIG, ("xi_get()\n")); 925 926 PAGE(sc, 0); 927 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 928 929 pktlen = 930 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 931 RBC_COUNT_MASK; 932 933 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 934 935 if (pktlen == 0) { 936 /* 937 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 938 * when MPE is set. It is not known why. 939 */ 940 return (0); 941 } 942 943 /* XXX should this be incremented now ? */ 944 recvcount += pktlen; 945 946 MGETHDR(m, M_DONTWAIT, MT_DATA); 947 if (m == 0) 948 return (recvcount); 949 m->m_pkthdr.rcvif = ifp; 950 m->m_pkthdr.len = pktlen; 951 m->m_flags |= M_HASFCS; 952 len = MHLEN; 953 top = 0; 954 mp = ⊤ 955 956 while (pktlen > 0) { 957 if (top) { 958 MGET(m, M_DONTWAIT, MT_DATA); 959 if (m == 0) { 960 m_freem(top); 961 return (recvcount); 962 } 963 len = MLEN; 964 } 965 if (pktlen >= MINCLSIZE) { 966 MCLGET(m, M_DONTWAIT); 967 if (!(m->m_flags & M_EXT)) { 968 m_freem(m); 969 m_freem(top); 970 return (recvcount); 971 } 972 len = MCLBYTES; 973 } 974 if (!top) { 975 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 976 sizeof(struct ether_header)) - 977 sizeof(struct ether_header); 978 len -= newdata - m->m_data; 979 m->m_data = newdata; 980 } 981 len = min(pktlen, len); 982 data = mtod(m, u_int8_t *); 983 if (len > 1) { 984 len &= ~1; 985 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 986 sc->sc_offset + EDP, data, len>>1); 987 } else 988 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 989 sc->sc_offset + EDP); 990 m->m_len = len; 991 pktlen -= len; 992 *mp = m; 993 mp = &m->m_next; 994 } 995 996 /* Skip Rx packet. */ 997 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 998 DO_SKIP_RX_PKT); 999 1000 ifp->if_ipackets++; 1001 1002 #if NBPFILTER > 0 1003 if (ifp->if_bpf) 1004 bpf_mtap(ifp->if_bpf, top); 1005 #endif 1006 1007 (*ifp->if_input)(ifp, top); 1008 return (recvcount); 1009 } 1010 1011 /* 1012 * Serial management for the MII. 1013 * The DELAY's below stem from the fact that the maximum frequency 1014 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 1015 * go much faster than that. 1016 */ 1017 1018 /* Let the MII serial management be idle for one period. */ 1019 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 1020 static INLINE void 1021 xi_mdi_idle(sc) 1022 struct xi_softc *sc; 1023 { 1024 bus_space_tag_t bst = sc->sc_bst; 1025 bus_space_handle_t bsh = sc->sc_bsh; 1026 bus_addr_t offset = sc->sc_offset; 1027 1028 /* Drive MDC low... */ 1029 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1030 DELAY(1); 1031 1032 /* and high again. */ 1033 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1034 DELAY(1); 1035 } 1036 1037 /* Pulse out one bit of data. */ 1038 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 1039 static INLINE void 1040 xi_mdi_pulse(sc, data) 1041 struct xi_softc *sc; 1042 int data; 1043 { 1044 bus_space_tag_t bst = sc->sc_bst; 1045 bus_space_handle_t bsh = sc->sc_bsh; 1046 bus_addr_t offset = sc->sc_offset; 1047 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 1048 1049 /* First latch the data bit MDIO with clock bit MDC low...*/ 1050 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 1051 DELAY(1); 1052 1053 /* then raise the clock again, preserving the data bit. */ 1054 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 1055 DELAY(1); 1056 } 1057 1058 /* Probe one bit of data. */ 1059 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 1060 static INLINE int 1061 xi_mdi_probe(sc) 1062 struct xi_softc *sc; 1063 { 1064 bus_space_tag_t bst = sc->sc_bst; 1065 bus_space_handle_t bsh = sc->sc_bsh; 1066 bus_addr_t offset = sc->sc_offset; 1067 u_int8_t x; 1068 1069 /* Pull clock bit MDCK low... */ 1070 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1071 DELAY(1); 1072 1073 /* Read data and drive clock high again. */ 1074 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 1075 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1076 DELAY(1); 1077 1078 return (x); 1079 } 1080 1081 /* Pulse out a sequence of data bits. */ 1082 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 1083 static INLINE void 1084 xi_mdi_pulse_bits(sc, data, len) 1085 struct xi_softc *sc; 1086 u_int32_t data; 1087 int len; 1088 { 1089 u_int32_t mask; 1090 1091 for (mask = 1 << (len - 1); mask; mask >>= 1) 1092 xi_mdi_pulse(sc, data & mask); 1093 } 1094 1095 /* Read a PHY register. */ 1096 static int 1097 xi_mdi_read(self, phy, reg) 1098 struct device *self; 1099 int phy; 1100 int reg; 1101 { 1102 struct xi_softc *sc = (struct xi_softc *)self; 1103 int i; 1104 u_int32_t mask; 1105 u_int32_t data = 0; 1106 1107 PAGE(sc, 2); 1108 for (i = 0; i < 32; i++) /* Synchronize. */ 1109 xi_mdi_pulse(sc, 1); 1110 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1111 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1112 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1113 xi_mdi_idle(sc); /* Turn around. */ 1114 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1115 1116 for (mask = 1 << 15; mask; mask >>= 1) { 1117 if (xi_mdi_probe(sc)) 1118 data |= mask; 1119 } 1120 xi_mdi_idle(sc); 1121 1122 DPRINTF(XID_MII, 1123 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1124 1125 return (data); 1126 } 1127 1128 /* Write a PHY register. */ 1129 static void 1130 xi_mdi_write(self, phy, reg, value) 1131 struct device *self; 1132 int phy; 1133 int reg; 1134 int value; 1135 { 1136 struct xi_softc *sc = (struct xi_softc *)self; 1137 int i; 1138 1139 PAGE(sc, 2); 1140 for (i = 0; i < 32; i++) /* Synchronize. */ 1141 xi_mdi_pulse(sc, 1); 1142 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1143 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1144 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1145 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1146 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1147 xi_mdi_idle(sc); /* Idle away. */ 1148 1149 DPRINTF(XID_MII, 1150 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1151 } 1152 1153 static void 1154 xi_statchg(self) 1155 struct device *self; 1156 { 1157 /* XXX Update ifp->if_baudrate */ 1158 } 1159 1160 /* 1161 * Change media according to request. 1162 */ 1163 static int 1164 xi_mediachange(ifp) 1165 struct ifnet *ifp; 1166 { 1167 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1168 1169 if (ifp->if_flags & IFF_UP) 1170 xi_init(ifp->if_softc); 1171 return (0); 1172 } 1173 1174 /* 1175 * Notify the world which media we're using. 1176 */ 1177 static void 1178 xi_mediastatus(ifp, ifmr) 1179 struct ifnet *ifp; 1180 struct ifmediareq *ifmr; 1181 { 1182 struct xi_softc *sc = ifp->if_softc; 1183 1184 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1185 1186 mii_pollstat(&sc->sc_mii); 1187 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1188 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1189 } 1190 1191 static void 1192 xi_reset(sc) 1193 struct xi_softc *sc; 1194 { 1195 int s; 1196 1197 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1198 1199 s = splnet(); 1200 xi_stop(sc); 1201 xi_full_reset(sc); 1202 xi_init(sc); 1203 splx(s); 1204 } 1205 1206 static void 1207 xi_watchdog(ifp) 1208 struct ifnet *ifp; 1209 { 1210 struct xi_softc *sc = ifp->if_softc; 1211 1212 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1213 ++ifp->if_oerrors; 1214 1215 xi_reset(sc); 1216 } 1217 1218 static void 1219 xi_stop(sc) 1220 register struct xi_softc *sc; 1221 { 1222 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1223 1224 /* Disable interrupts. */ 1225 PAGE(sc, 0); 1226 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1227 1228 PAGE(sc, 1); 1229 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1230 1231 /* Power down, wait. */ 1232 PAGE(sc, 4); 1233 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1234 DELAY(40000); 1235 1236 /* Cancel watchdog timer. */ 1237 sc->sc_ethercom.ec_if.if_timer = 0; 1238 } 1239 1240 static void 1241 xi_init(sc) 1242 struct xi_softc *sc; 1243 { 1244 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)sc; 1245 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1246 int s; 1247 1248 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1249 1250 if ((psc->sc_resource & XI_RES_PCIC) == 0) 1251 xi_pcmcia_enable(psc); 1252 1253 s = splnet(); 1254 1255 xi_set_address(sc); 1256 1257 /* Set current media. */ 1258 mii_mediachg(&sc->sc_mii); 1259 1260 ifp->if_flags |= IFF_RUNNING; 1261 ifp->if_flags &= ~IFF_OACTIVE; 1262 splx(s); 1263 } 1264 1265 /* 1266 * Start outputting on the interface. 1267 * Always called as splnet(). 1268 */ 1269 static void 1270 xi_start(ifp) 1271 struct ifnet *ifp; 1272 { 1273 struct xi_softc *sc = ifp->if_softc; 1274 bus_space_tag_t bst = sc->sc_bst; 1275 bus_space_handle_t bsh = sc->sc_bsh; 1276 bus_addr_t offset = sc->sc_offset; 1277 unsigned int s, len, pad = 0; 1278 struct mbuf *m0, *m; 1279 u_int16_t space; 1280 1281 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1282 1283 /* Don't transmit if interface is busy or not running. */ 1284 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1285 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1286 return; 1287 } 1288 1289 /* Peek at the next packet. */ 1290 IFQ_POLL(&ifp->if_snd, m0); 1291 if (m0 == 0) 1292 return; 1293 1294 /* We need to use m->m_pkthdr.len, so require the header. */ 1295 if (!(m0->m_flags & M_PKTHDR)) 1296 panic("xi_start: no header mbuf"); 1297 1298 len = m0->m_pkthdr.len; 1299 1300 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1301 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1302 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1303 1304 PAGE(sc, 0); 1305 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1306 if (len + pad + 2 > space) { 1307 DPRINTF(XID_FIFO, 1308 ("xi: not enough space in output FIFO (%d > %d)\n", 1309 len + pad + 2, space)); 1310 return; 1311 } 1312 1313 IFQ_DEQUEUE(&ifp->if_snd, m0); 1314 1315 #if NBPFILTER > 0 1316 if (ifp->if_bpf) 1317 bpf_mtap(ifp->if_bpf, m0); 1318 #endif 1319 1320 /* 1321 * Do the output at splhigh() so that an interrupt from another device 1322 * won't cause a FIFO underrun. 1323 */ 1324 s = splhigh(); 1325 1326 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1327 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1328 for (m = m0; m; ) { 1329 if (m->m_len > 1) 1330 bus_space_write_multi_2(bst, bsh, offset + EDP, 1331 mtod(m, u_int8_t *), m->m_len>>1); 1332 if (m->m_len & 1) 1333 bus_space_write_1(bst, bsh, offset + EDP, 1334 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1335 MFREE(m, m0); 1336 m = m0; 1337 } 1338 if (sc->sc_flags & XIFLAGS_MOHAWK) 1339 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1340 else { 1341 for (; pad > 1; pad -= 2) 1342 bus_space_write_2(bst, bsh, offset + EDP, 0); 1343 if (pad == 1) 1344 bus_space_write_1(bst, bsh, offset + EDP, 0); 1345 } 1346 1347 splx(s); 1348 1349 ifp->if_timer = 5; 1350 ++ifp->if_opackets; 1351 } 1352 1353 static int 1354 xi_ether_ioctl(ifp, cmd, data) 1355 struct ifnet *ifp; 1356 u_long cmd; 1357 caddr_t data; 1358 { 1359 struct ifaddr *ifa = (struct ifaddr *)data; 1360 struct xi_softc *sc = ifp->if_softc; 1361 1362 1363 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1364 1365 switch (cmd) { 1366 case SIOCSIFADDR: 1367 ifp->if_flags |= IFF_UP; 1368 1369 switch (ifa->ifa_addr->sa_family) { 1370 #ifdef INET 1371 case AF_INET: 1372 xi_init(sc); 1373 arp_ifinit(ifp, ifa); 1374 break; 1375 #endif /* INET */ 1376 1377 #ifdef NS 1378 case AF_NS: 1379 { 1380 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1381 1382 if (ns_nullhost(*ina)) 1383 ina->x_host = *(union ns_host *) 1384 LLADDR(ifp->if_sadl); 1385 else 1386 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1387 ifp->if_addrlen); 1388 /* Set new address. */ 1389 xi_init(sc); 1390 break; 1391 } 1392 #endif /* NS */ 1393 1394 default: 1395 xi_init(sc); 1396 break; 1397 } 1398 break; 1399 1400 default: 1401 return (EINVAL); 1402 } 1403 1404 return (0); 1405 } 1406 1407 static int 1408 xi_ioctl(ifp, command, data) 1409 struct ifnet *ifp; 1410 u_long command; 1411 caddr_t data; 1412 { 1413 struct xi_pcmcia_softc *psc = ifp->if_softc; 1414 struct xi_softc *sc = &psc->sc_xi; 1415 struct ifreq *ifr = (struct ifreq *)data; 1416 int s, error = 0; 1417 1418 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1419 1420 s = splnet(); 1421 1422 switch (command) { 1423 case SIOCSIFADDR: 1424 error = xi_ether_ioctl(ifp, command, data); 1425 break; 1426 1427 case SIOCSIFFLAGS: 1428 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1429 1430 PAGE(sc, 0x42); 1431 if ((ifp->if_flags & IFF_PROMISC) || 1432 (ifp->if_flags & IFF_ALLMULTI)) 1433 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1434 sc->sc_offset + SWC1, 1435 SWC1_PROMISC | SWC1_MCAST_PROM); 1436 else 1437 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1438 sc->sc_offset + SWC1, 0); 1439 1440 /* 1441 * If interface is marked up and not running, then start it. 1442 * If it is marked down and running, stop it. 1443 * XXX If it's up then re-initialize it. This is so flags 1444 * such as IFF_PROMISC are handled. 1445 */ 1446 if (ifp->if_flags & IFF_UP) { 1447 xi_init(sc); 1448 } else { 1449 if (ifp->if_flags & IFF_RUNNING) { 1450 xi_pcmcia_disable(psc); 1451 xi_stop(sc); 1452 ifp->if_flags &= ~IFF_RUNNING; 1453 } 1454 } 1455 break; 1456 1457 case SIOCADDMULTI: 1458 case SIOCDELMULTI: 1459 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1460 error = (command == SIOCADDMULTI) ? 1461 ether_addmulti(ifr, &sc->sc_ethercom) : 1462 ether_delmulti(ifr, &sc->sc_ethercom); 1463 1464 if (error == ENETRESET) { 1465 /* 1466 * Multicast list has changed; set the hardware 1467 * filter accordingly. 1468 */ 1469 if (!sc->sc_all_mcasts && 1470 !(ifp->if_flags & IFF_PROMISC)) 1471 xi_set_address(sc); 1472 1473 /* 1474 * xi_set_address() can turn on all_mcasts if we run 1475 * out of space, so check it again rather than else {}. 1476 */ 1477 if (sc->sc_all_mcasts) 1478 xi_init(sc); 1479 error = 0; 1480 } 1481 break; 1482 1483 case SIOCSIFMEDIA: 1484 case SIOCGIFMEDIA: 1485 error = 1486 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1487 break; 1488 1489 default: 1490 error = EINVAL; 1491 } 1492 splx(s); 1493 return (error); 1494 } 1495 1496 static void 1497 xi_set_address(sc) 1498 struct xi_softc *sc; 1499 { 1500 bus_space_tag_t bst = sc->sc_bst; 1501 bus_space_handle_t bsh = sc->sc_bsh; 1502 bus_addr_t offset = sc->sc_offset; 1503 struct ethercom *ether = &sc->sc_ethercom; 1504 #if 0 1505 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1506 #endif 1507 #if WORKING_MULTICAST 1508 struct ether_multistep step; 1509 struct ether_multi *enm; 1510 int page, pos, num; 1511 #endif 1512 int i; 1513 1514 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1515 1516 PAGE(sc, 0x50); 1517 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1518 bus_space_write_1(bst, bsh, offset + IA + i, 1519 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1520 } 1521 1522 if (ether->ec_multicnt > 0) { 1523 #ifdef WORKING_MULTICAST 1524 if (ether->ec_multicnt > 9) { 1525 #else 1526 { 1527 #endif 1528 PAGE(sc, 0x42); 1529 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1530 sc->sc_offset + SWC1, 1531 SWC1_PROMISC | SWC1_MCAST_PROM); 1532 return; 1533 } 1534 1535 #ifdef WORKING_MULTICAST 1536 1537 ETHER_FIRST_MULTI(step, ether, enm); 1538 1539 pos = IA + 6; 1540 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1541 num--) { 1542 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1543 sizeof(enm->enm_addrlo)) != 0) { 1544 /* 1545 * The multicast address is really a range; 1546 * it's easier just to accept all multicasts. 1547 * XXX should we be setting IFF_ALLMULTI here? 1548 */ 1549 #if 0 1550 ifp->if_flags |= IFF_ALLMULTI; 1551 #endif 1552 sc->sc_all_mcasts=1; 1553 break; 1554 } 1555 1556 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1557 printf("%x:", enm->enm_addrlo[i]); 1558 bus_space_write_1(bst, bsh, offset + pos, 1559 enm->enm_addrlo[ 1560 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1561 1562 if (++pos > 15) { 1563 pos = IA; 1564 page++; 1565 PAGE(sc, page); 1566 } 1567 } 1568 printf("\n"); 1569 ETHER_NEXT_MULTI(step, enm); 1570 } 1571 #endif 1572 } 1573 } 1574 1575 static void 1576 xi_cycle_power(sc) 1577 struct xi_softc *sc; 1578 { 1579 bus_space_tag_t bst = sc->sc_bst; 1580 bus_space_handle_t bsh = sc->sc_bsh; 1581 bus_addr_t offset = sc->sc_offset; 1582 1583 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1584 1585 PAGE(sc, 4); 1586 DELAY(1); 1587 bus_space_write_1(bst, bsh, offset + GP1, 0); 1588 DELAY(40000); 1589 if (sc->sc_flags & XIFLAGS_MOHAWK) 1590 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1591 else 1592 /* XXX What is bit 2 (aka AIC)? */ 1593 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1594 DELAY(20000); 1595 } 1596 1597 static void 1598 xi_full_reset(sc) 1599 struct xi_softc *sc; 1600 { 1601 bus_space_tag_t bst = sc->sc_bst; 1602 bus_space_handle_t bsh = sc->sc_bsh; 1603 bus_addr_t offset = sc->sc_offset; 1604 1605 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1606 1607 /* Do an as extensive reset as possible on all functions. */ 1608 xi_cycle_power(sc); 1609 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1610 DELAY(20000); 1611 bus_space_write_1(bst, bsh, offset + CR, 0); 1612 DELAY(20000); 1613 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1614 PAGE(sc, 4); 1615 /* 1616 * Drive GP1 low to power up ML6692 and GP2 high to power up 1617 * the 10Mhz chip. XXX What chip is that? The phy? 1618 */ 1619 bus_space_write_1(bst, bsh, offset + GP0, 1620 GP1_OUT | GP2_OUT | GP2_WR); 1621 } 1622 DELAY(500000); 1623 1624 /* Get revision information. XXX Symbolic constants. */ 1625 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1626 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1627 1628 /* Media selection. XXX Maybe manual overriding too? */ 1629 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1630 PAGE(sc, 4); 1631 /* 1632 * XXX I have no idea what this really does, it is from the 1633 * Linux driver. 1634 */ 1635 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1636 } 1637 DELAY(40000); 1638 1639 /* Setup the ethernet interrupt mask. */ 1640 PAGE(sc, 1); 1641 #if 1 1642 bus_space_write_1(bst, bsh, offset + IMR0, 1643 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1644 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1645 #else 1646 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1647 #endif 1648 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1649 /* XXX What is this? Not for Dingo at least. */ 1650 /* Unmask TX underrun detection */ 1651 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1652 } 1653 1654 /* 1655 * Disable source insertion. 1656 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1657 */ 1658 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1659 PAGE(sc, 0x42); 1660 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1661 } 1662 1663 /* Set the local memory dividing line. */ 1664 if (sc->sc_rev != 1) { 1665 PAGE(sc, 2); 1666 /* XXX Symbolic constant preferrable. */ 1667 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1668 } 1669 1670 xi_set_address(sc); 1671 1672 /* 1673 * Apparently the receive byte pointer can be bad after a reset, so 1674 * we hardwire it correctly. 1675 */ 1676 PAGE(sc, 0); 1677 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1678 1679 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1680 PAGE(sc, 0x40); 1681 bus_space_write_1(bst, bsh, offset + RX0MSK, 1682 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1683 bus_space_write_1(bst, bsh, offset + TX0MSK, 1684 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1685 SQE | TX_ABORT | TX_OK); 1686 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1687 /* XXX From Linux, dunno what 0xb0 means. */ 1688 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1689 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1690 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1691 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1692 1693 /* Enable MII function if available. */ 1694 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1695 PAGE(sc, 2); 1696 bus_space_write_1(bst, bsh, offset + MSR, 1697 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1698 DELAY(20000); 1699 } else { 1700 PAGE(sc, 0); 1701 1702 /* XXX Do we need to do this? */ 1703 PAGE(sc, 0x42); 1704 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1705 DELAY(50000); 1706 1707 /* XXX Linux probes the media here. */ 1708 } 1709 1710 /* Configure the LED registers. */ 1711 PAGE(sc, 2); 1712 1713 /* XXX This is not good for 10base2. */ 1714 bus_space_write_1(bst, bsh, offset + LED, 1715 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1716 if (sc->sc_flags & XIFLAGS_DINGO) 1717 bus_space_write_1(bst, bsh, offset + LED3, 1718 LED_100MB_LINK << LED3_SHIFT); 1719 1720 /* Enable receiver and go online. */ 1721 PAGE(sc, 0x40); 1722 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1723 1724 #if 0 1725 /* XXX Linux does this here - is it necessary? */ 1726 PAGE(sc, 1); 1727 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1728 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1729 /* XXX What is this? Not for Dingo at least. */ 1730 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1731 } 1732 #endif 1733 1734 /* Enable interrupts. */ 1735 PAGE(sc, 0); 1736 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1737 1738 /* XXX This is pure magic for me, found in the Linux driver. */ 1739 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1740 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1741 /* Unmask the master interrupt bit. */ 1742 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1743 } 1744 1745 /* 1746 * The Linux driver says this: 1747 * We should switch back to page 0 to avoid a bug in revision 0 1748 * where regs with offset below 8 can't be read after an access 1749 * to the MAC registers. 1750 */ 1751 PAGE(sc, 0); 1752 } 1753