1 /* $NetBSD: if_xi.c,v 1.69 2009/12/06 23:05:39 dyoung Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.69 2009/12/06 23:05:39 dyoung Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 /* 100 * Maximum number of bytes to read per interrupt. Linux recommends 101 * somewhere between 2000-22000. 102 * XXX This is currently a hard maximum. 103 */ 104 #define MAX_BYTES_INTR 12000 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/pcmcia/pcmciareg.h> 110 #include <dev/pcmcia/pcmciavar.h> 111 #include <dev/pcmcia/pcmciadevs.h> 112 113 #include <dev/pcmcia/if_xireg.h> 114 #include <dev/pcmcia/if_xivar.h> 115 116 #ifdef __GNUC__ 117 #define INLINE inline 118 #else 119 #define INLINE 120 #endif /* __GNUC__ */ 121 122 #define XIDEBUG 123 #define XIDEBUG_VALUE 0 124 125 #ifdef XIDEBUG 126 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 127 128 #define XID_CONFIG 0x01 129 #define XID_MII 0x02 130 #define XID_INTR 0x04 131 #define XID_FIFO 0x08 132 #define XID_MCAST 0x10 133 134 #ifdef XIDEBUG_VALUE 135 int xidebug = XIDEBUG_VALUE; 136 #else 137 int xidebug = 0; 138 #endif 139 #else 140 #define DPRINTF(cat, x) (void)0 141 #endif 142 143 #define STATIC 144 145 STATIC int xi_enable(struct xi_softc *); 146 STATIC void xi_disable(struct xi_softc *); 147 STATIC void xi_cycle_power(struct xi_softc *); 148 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 149 STATIC void xi_full_reset(struct xi_softc *); 150 STATIC void xi_init(struct xi_softc *); 151 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 152 STATIC int xi_mdi_read(device_t, int, int); 153 STATIC void xi_mdi_write(device_t, int, int, int); 154 STATIC int xi_mediachange(struct ifnet *); 155 STATIC u_int16_t xi_get(struct xi_softc *); 156 STATIC void xi_reset(struct xi_softc *); 157 STATIC void xi_set_address(struct xi_softc *); 158 STATIC void xi_start(struct ifnet *); 159 STATIC void xi_statchg(device_t); 160 STATIC void xi_stop(struct xi_softc *); 161 STATIC void xi_watchdog(struct ifnet *); 162 163 void 164 xi_attach(struct xi_softc *sc, u_int8_t *myea) 165 { 166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 167 168 #if 0 169 /* 170 * Configuration as advised by DINGO documentation. 171 * Dingo has some extra configuration registers in the CCR space. 172 */ 173 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 174 struct pcmcia_mem_handle pcmh; 175 int ccr_window; 176 bus_size_t ccr_offset; 177 178 /* get access to the DINGO CCR space */ 179 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 180 &pcmh)) { 181 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 182 goto fail; 183 } 184 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 185 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 186 &pcmh, &ccr_offset, &ccr_window)) { 187 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 188 pcmcia_mem_free(psc->sc_pf, &pcmh); 189 goto fail; 190 } 191 192 /* enable the second function - usually modem */ 193 bus_space_write_1(pcmh.memt, pcmh.memh, 194 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 195 bus_space_write_1(pcmh.memt, pcmh.memh, 196 ccr_offset + PCMCIA_CCR_DCOR1, 197 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 198 bus_space_write_1(pcmh.memt, pcmh.memh, 199 ccr_offset + PCMCIA_CCR_DCOR2, 0); 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR3, 0); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR4, 0); 204 205 /* We don't need them anymore and can free them (I think). */ 206 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 207 pcmcia_mem_free(psc->sc_pf, &pcmh); 208 } 209 #endif 210 211 /* Reset and initialize the card. */ 212 xi_full_reset(sc); 213 214 printf("%s: MAC address %s\n", device_xname(sc->sc_dev), ether_sprintf(myea)); 215 216 ifp = &sc->sc_ethercom.ec_if; 217 /* Initialize the ifnet structure. */ 218 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 219 ifp->if_softc = sc; 220 ifp->if_start = xi_start; 221 ifp->if_ioctl = xi_ioctl; 222 ifp->if_watchdog = xi_watchdog; 223 ifp->if_flags = 224 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 225 IFQ_SET_READY(&ifp->if_snd); 226 227 /* 802.1q capability */ 228 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 229 230 /* Attach the interface. */ 231 if_attach(ifp); 232 ether_ifattach(ifp, myea); 233 234 /* 235 * Initialize our media structures and probe the MII. 236 */ 237 sc->sc_mii.mii_ifp = ifp; 238 sc->sc_mii.mii_readreg = xi_mdi_read; 239 sc->sc_mii.mii_writereg = xi_mdi_write; 240 sc->sc_mii.mii_statchg = xi_statchg; 241 sc->sc_ethercom.ec_mii = &sc->sc_mii; 242 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 243 ether_mediastatus); 244 DPRINTF(XID_MII | XID_CONFIG, 245 ("xi: bmsr %x\n", xi_mdi_read(sc->sc_dev, 0, 1))); 246 247 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 248 MII_OFFSET_ANY, 0); 249 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 250 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 251 NULL); 252 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 253 254 #if NRND > 0 255 rnd_attach_source(&sc->sc_rnd_source, device_xname(sc->sc_dev), RND_TYPE_NET, 0); 256 #endif 257 } 258 259 int 260 xi_detach(device_t self, int flags) 261 { 262 struct xi_softc *sc = device_private(self); 263 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 264 265 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 266 267 xi_disable(sc); 268 269 #if NRND > 0 270 rnd_detach_source(&sc->sc_rnd_source); 271 #endif 272 273 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 274 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 275 ether_ifdetach(ifp); 276 if_detach(ifp); 277 278 return 0; 279 } 280 281 int 282 xi_intr(void *arg) 283 { 284 struct xi_softc *sc = arg; 285 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 286 u_int8_t esr, rsr, isr, rx_status; 287 u_int16_t tx_status, recvcount = 0, tempint; 288 289 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 290 291 if (sc->sc_enabled == 0 || !device_is_active(sc->sc_dev)) 292 return (0); 293 294 ifp->if_timer = 0; /* turn watchdog timer off */ 295 296 PAGE(sc, 0); 297 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 298 /* Disable interrupt (Linux does it). */ 299 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 300 } 301 302 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 303 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 304 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 305 306 /* Check to see if card has been ejected. */ 307 if (isr == 0xff) { 308 #ifdef DIAGNOSTIC 309 printf("%s: interrupt for dead card\n", 310 device_xname(sc->sc_dev)); 311 #endif 312 goto end; 313 } 314 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 315 316 PAGE(sc, 0x40); 317 rx_status = 318 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 319 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 320 tx_status = 321 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 322 tx_status |= 323 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 324 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 325 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 326 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 327 tx_status)); 328 329 PAGE(sc, 0); 330 while (esr & FULL_PKT_RCV) { 331 if (!(rsr & RSR_RX_OK)) 332 break; 333 334 /* Compare bytes read this interrupt to hard maximum. */ 335 if (recvcount > MAX_BYTES_INTR) { 336 DPRINTF(XID_INTR, 337 ("xi: too many bytes this interrupt\n")); 338 ifp->if_iqdrops++; 339 /* Drop packet. */ 340 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 341 DO_SKIP_RX_PKT); 342 } 343 tempint = xi_get(sc); /* XXX doesn't check the error! */ 344 recvcount += tempint; 345 ifp->if_ibytes += tempint; 346 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 347 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 348 } 349 350 /* Packet too long? */ 351 if (rsr & RSR_TOO_LONG) { 352 ifp->if_ierrors++; 353 DPRINTF(XID_INTR, ("xi: packet too long\n")); 354 } 355 356 /* CRC error? */ 357 if (rsr & RSR_CRCERR) { 358 ifp->if_ierrors++; 359 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 360 } 361 362 /* Alignment error? */ 363 if (rsr & RSR_ALIGNERR) { 364 ifp->if_ierrors++; 365 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 366 } 367 368 /* Check for rx overrun. */ 369 if (rx_status & RX_OVERRUN) { 370 ifp->if_ierrors++; 371 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 372 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 373 } 374 375 /* Try to start more packets transmitting. */ 376 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 377 xi_start(ifp); 378 379 /* Detected excessive collisions? */ 380 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 381 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 382 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 383 ifp->if_oerrors++; 384 } 385 386 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 387 ifp->if_oerrors++; 388 389 /* have handled the interrupt */ 390 #if NRND > 0 391 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 392 #endif 393 394 end: 395 /* Reenable interrupts. */ 396 PAGE(sc, 0); 397 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 398 399 return (1); 400 } 401 402 /* 403 * Pull a packet from the card into an mbuf chain. 404 */ 405 STATIC u_int16_t 406 xi_get(struct xi_softc *sc) 407 { 408 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 409 struct mbuf *top, **mp, *m; 410 u_int16_t pktlen, len, recvcount = 0; 411 u_int8_t *data; 412 413 DPRINTF(XID_CONFIG, ("xi_get()\n")); 414 415 PAGE(sc, 0); 416 pktlen = 417 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 418 419 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 420 421 if (pktlen == 0) { 422 /* 423 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 424 * when MPE is set. It is not known why. 425 */ 426 return (0); 427 } 428 429 /* XXX should this be incremented now ? */ 430 recvcount += pktlen; 431 432 MGETHDR(m, M_DONTWAIT, MT_DATA); 433 if (m == NULL) 434 return (recvcount); 435 m->m_pkthdr.rcvif = ifp; 436 m->m_pkthdr.len = pktlen; 437 len = MHLEN; 438 top = NULL; 439 mp = ⊤ 440 441 while (pktlen > 0) { 442 if (top) { 443 MGET(m, M_DONTWAIT, MT_DATA); 444 if (m == NULL) { 445 m_freem(top); 446 return (recvcount); 447 } 448 len = MLEN; 449 } 450 if (pktlen >= MINCLSIZE) { 451 MCLGET(m, M_DONTWAIT); 452 if (!(m->m_flags & M_EXT)) { 453 m_freem(m); 454 m_freem(top); 455 return (recvcount); 456 } 457 len = MCLBYTES; 458 } 459 if (top == NULL) { 460 char *newdata = (char *)ALIGN(m->m_data + 461 sizeof(struct ether_header)) - 462 sizeof(struct ether_header); 463 len -= newdata - m->m_data; 464 m->m_data = newdata; 465 } 466 len = min(pktlen, len); 467 data = mtod(m, u_int8_t *); 468 if (len > 1) { 469 len &= ~1; 470 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 471 (u_int16_t *)data, len>>1); 472 } else 473 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 474 m->m_len = len; 475 pktlen -= len; 476 *mp = m; 477 mp = &m->m_next; 478 } 479 480 /* Skip Rx packet. */ 481 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 482 483 if (top == NULL) 484 return recvcount; 485 486 /* Trim the CRC off the end of the packet. */ 487 m_adj(top, -ETHER_CRC_LEN); 488 489 ifp->if_ipackets++; 490 491 #if NBPFILTER > 0 492 if (ifp->if_bpf) 493 bpf_mtap(ifp->if_bpf, top); 494 #endif 495 496 (*ifp->if_input)(ifp, top); 497 return (recvcount); 498 } 499 500 /* 501 * Serial management for the MII. 502 * The DELAY's below stem from the fact that the maximum frequency 503 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 504 * go much faster than that. 505 */ 506 507 /* Let the MII serial management be idle for one period. */ 508 static INLINE void xi_mdi_idle(struct xi_softc *); 509 static INLINE void 510 xi_mdi_idle(struct xi_softc *sc) 511 { 512 bus_space_tag_t bst = sc->sc_bst; 513 bus_space_handle_t bsh = sc->sc_bsh; 514 515 /* Drive MDC low... */ 516 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 517 DELAY(1); 518 519 /* and high again. */ 520 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 521 DELAY(1); 522 } 523 524 /* Pulse out one bit of data. */ 525 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 526 static INLINE void 527 xi_mdi_pulse(struct xi_softc *sc, int data) 528 { 529 bus_space_tag_t bst = sc->sc_bst; 530 bus_space_handle_t bsh = sc->sc_bsh; 531 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 532 533 /* First latch the data bit MDIO with clock bit MDC low...*/ 534 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 535 DELAY(1); 536 537 /* then raise the clock again, preserving the data bit. */ 538 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 539 DELAY(1); 540 } 541 542 /* Probe one bit of data. */ 543 static INLINE int xi_mdi_probe(struct xi_softc *sc); 544 static INLINE int 545 xi_mdi_probe(struct xi_softc *sc) 546 { 547 bus_space_tag_t bst = sc->sc_bst; 548 bus_space_handle_t bsh = sc->sc_bsh; 549 u_int8_t x; 550 551 /* Pull clock bit MDCK low... */ 552 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 553 DELAY(1); 554 555 /* Read data and drive clock high again. */ 556 x = bus_space_read_1(bst, bsh, GP2); 557 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 558 DELAY(1); 559 560 return (x & MDIO); 561 } 562 563 /* Pulse out a sequence of data bits. */ 564 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 565 static INLINE void 566 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 567 { 568 u_int32_t mask; 569 570 for (mask = 1 << (len - 1); mask; mask >>= 1) 571 xi_mdi_pulse(sc, data & mask); 572 } 573 574 /* Read a PHY register. */ 575 STATIC int 576 xi_mdi_read(device_t self, int phy, int reg) 577 { 578 struct xi_softc *sc = device_private(self); 579 int i; 580 u_int32_t mask; 581 u_int32_t data = 0; 582 583 PAGE(sc, 2); 584 for (i = 0; i < 32; i++) /* Synchronize. */ 585 xi_mdi_pulse(sc, 1); 586 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 587 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 588 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 589 xi_mdi_idle(sc); /* Turn around. */ 590 xi_mdi_probe(sc); /* Drop initial zero bit. */ 591 592 for (mask = 1 << 15; mask; mask >>= 1) { 593 if (xi_mdi_probe(sc)) 594 data |= mask; 595 } 596 xi_mdi_idle(sc); 597 598 DPRINTF(XID_MII, 599 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 600 601 return (data); 602 } 603 604 /* Write a PHY register. */ 605 STATIC void 606 xi_mdi_write(device_t self, int phy, int reg, int value) 607 { 608 struct xi_softc *sc = device_private(self); 609 int i; 610 611 PAGE(sc, 2); 612 for (i = 0; i < 32; i++) /* Synchronize. */ 613 xi_mdi_pulse(sc, 1); 614 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 615 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 616 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 617 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 618 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 619 xi_mdi_idle(sc); /* Idle away. */ 620 621 DPRINTF(XID_MII, 622 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 623 } 624 625 STATIC void 626 xi_statchg(device_t self) 627 { 628 /* XXX Update ifp->if_baudrate */ 629 } 630 631 /* 632 * Change media according to request. 633 */ 634 STATIC int 635 xi_mediachange(struct ifnet *ifp) 636 { 637 int s; 638 639 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 640 641 if (ifp->if_flags & IFF_UP) { 642 s = splnet(); 643 xi_init(ifp->if_softc); 644 splx(s); 645 } 646 return (0); 647 } 648 649 STATIC void 650 xi_reset(struct xi_softc *sc) 651 { 652 int s; 653 654 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 655 656 s = splnet(); 657 xi_stop(sc); 658 xi_init(sc); 659 splx(s); 660 } 661 662 STATIC void 663 xi_watchdog(struct ifnet *ifp) 664 { 665 struct xi_softc *sc = ifp->if_softc; 666 667 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 668 ++ifp->if_oerrors; 669 670 xi_reset(sc); 671 } 672 673 STATIC void 674 xi_stop(register struct xi_softc *sc) 675 { 676 bus_space_tag_t bst = sc->sc_bst; 677 bus_space_handle_t bsh = sc->sc_bsh; 678 679 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 680 681 PAGE(sc, 0x40); 682 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 683 684 /* Disable interrupts. */ 685 PAGE(sc, 0); 686 bus_space_write_1(bst, bsh, CR, 0); 687 688 PAGE(sc, 1); 689 bus_space_write_1(bst, bsh, IMR0, 0); 690 691 /* Cancel watchdog timer. */ 692 sc->sc_ethercom.ec_if.if_timer = 0; 693 } 694 695 STATIC int 696 xi_enable(struct xi_softc *sc) 697 { 698 int error; 699 700 if (!sc->sc_enabled) { 701 error = (*sc->sc_enable)(sc); 702 if (error) 703 return (error); 704 sc->sc_enabled = 1; 705 xi_full_reset(sc); 706 } 707 return (0); 708 } 709 710 STATIC void 711 xi_disable(struct xi_softc *sc) 712 { 713 714 if (sc->sc_enabled) { 715 sc->sc_enabled = 0; 716 (*sc->sc_disable)(sc); 717 } 718 } 719 720 STATIC void 721 xi_init(struct xi_softc *sc) 722 { 723 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 724 bus_space_tag_t bst = sc->sc_bst; 725 bus_space_handle_t bsh = sc->sc_bsh; 726 727 DPRINTF(XID_CONFIG, ("xi_init()\n")); 728 729 /* Setup the ethernet interrupt mask. */ 730 PAGE(sc, 1); 731 bus_space_write_1(bst, bsh, IMR0, 732 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 733 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 734 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 735 /* XXX What is this? Not for Dingo at least. */ 736 /* Unmask TX underrun detection */ 737 bus_space_write_1(bst, bsh, IMR1, 1); 738 } 739 740 /* Enable interrupts. */ 741 PAGE(sc, 0); 742 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 743 744 xi_set_address(sc); 745 746 PAGE(sc, 0x40); 747 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 748 749 PAGE(sc, 0); 750 751 /* Set current media. */ 752 mii_mediachg(&sc->sc_mii); 753 754 ifp->if_flags |= IFF_RUNNING; 755 ifp->if_flags &= ~IFF_OACTIVE; 756 757 xi_start(ifp); 758 } 759 760 /* 761 * Start outputting on the interface. 762 * Always called as splnet(). 763 */ 764 STATIC void 765 xi_start(struct ifnet *ifp) 766 { 767 struct xi_softc *sc = ifp->if_softc; 768 bus_space_tag_t bst = sc->sc_bst; 769 bus_space_handle_t bsh = sc->sc_bsh; 770 unsigned int s, len, pad = 0; 771 struct mbuf *m0, *m; 772 u_int16_t space; 773 774 DPRINTF(XID_CONFIG, ("xi_start()\n")); 775 776 /* Don't transmit if interface is busy or not running. */ 777 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 778 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 779 return; 780 } 781 782 /* Peek at the next packet. */ 783 IFQ_POLL(&ifp->if_snd, m0); 784 if (m0 == 0) 785 return; 786 787 /* We need to use m->m_pkthdr.len, so require the header. */ 788 if (!(m0->m_flags & M_PKTHDR)) 789 panic("xi_start: no header mbuf"); 790 791 len = m0->m_pkthdr.len; 792 793 #if 1 794 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 795 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 796 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 797 #else 798 pad = 0; 799 #endif 800 801 PAGE(sc, 0); 802 803 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 804 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 805 if (len + pad + 2 > space) { 806 DPRINTF(XID_FIFO, 807 ("xi: not enough space in output FIFO (%d > %d)\n", 808 len + pad + 2, space)); 809 return; 810 } 811 812 IFQ_DEQUEUE(&ifp->if_snd, m0); 813 814 #if NBPFILTER > 0 815 if (ifp->if_bpf) 816 bpf_mtap(ifp->if_bpf, m0); 817 #endif 818 819 /* 820 * Do the output at splhigh() so that an interrupt from another device 821 * won't cause a FIFO underrun. 822 */ 823 s = splhigh(); 824 825 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 826 for (m = m0; m; ) { 827 if (m->m_len > 1) 828 bus_space_write_multi_2(bst, bsh, EDP, 829 mtod(m, u_int16_t *), m->m_len>>1); 830 if (m->m_len & 1) { 831 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 832 bus_space_write_1(bst, bsh, EDP, 833 *(mtod(m, u_int8_t *) + m->m_len - 1)); 834 } 835 MFREE(m, m0); 836 m = m0; 837 } 838 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 839 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 840 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 841 else { 842 for (; pad > 1; pad -= 2) 843 bus_space_write_2(bst, bsh, EDP, 0); 844 if (pad == 1) 845 bus_space_write_1(bst, bsh, EDP, 0); 846 } 847 848 splx(s); 849 850 ifp->if_timer = 5; 851 ++ifp->if_opackets; 852 } 853 854 STATIC int 855 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 856 { 857 struct ifaddr *ifa = (struct ifaddr *)data; 858 struct xi_softc *sc = ifp->if_softc; 859 int error; 860 861 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 862 863 switch (cmd) { 864 case SIOCINITIFADDR: 865 if ((error = xi_enable(sc)) != 0) 866 break; 867 868 ifp->if_flags |= IFF_UP; 869 870 xi_init(sc); 871 switch (ifa->ifa_addr->sa_family) { 872 #ifdef INET 873 case AF_INET: 874 arp_ifinit(ifp, ifa); 875 break; 876 #endif /* INET */ 877 878 879 default: 880 break; 881 } 882 break; 883 884 default: 885 return (EINVAL); 886 } 887 888 return (0); 889 } 890 891 STATIC int 892 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 893 { 894 struct xi_softc *sc = ifp->if_softc; 895 int s, error = 0; 896 897 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 898 899 s = splnet(); 900 901 switch (cmd) { 902 case SIOCINITIFADDR: 903 error = xi_ether_ioctl(ifp, cmd, data); 904 break; 905 906 case SIOCSIFFLAGS: 907 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 908 break; 909 /* XXX re-use ether_ioctl() */ 910 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 911 case IFF_RUNNING: 912 /* 913 * If interface is marked down and it is running, 914 * stop it. 915 */ 916 xi_stop(sc); 917 ifp->if_flags &= ~IFF_RUNNING; 918 xi_disable(sc); 919 break; 920 case IFF_UP: 921 /* 922 * If interface is marked up and it is stopped, 923 * start it. 924 */ 925 if ((error = xi_enable(sc)) != 0) 926 break; 927 xi_init(sc); 928 break; 929 case IFF_UP|IFF_RUNNING: 930 /* 931 * Reset the interface to pick up changes in any 932 * other flags that affect hardware registers. 933 */ 934 xi_set_address(sc); 935 break; 936 case 0: 937 break; 938 } 939 break; 940 941 case SIOCADDMULTI: 942 case SIOCDELMULTI: 943 if (sc->sc_enabled == 0) { 944 error = EIO; 945 break; 946 } 947 /*FALLTHROUGH*/ 948 case SIOCSIFMEDIA: 949 case SIOCGIFMEDIA: 950 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 951 /* 952 * Multicast list has changed; set the hardware 953 * filter accordingly. 954 */ 955 if (ifp->if_flags & IFF_RUNNING) 956 xi_set_address(sc); 957 error = 0; 958 } 959 break; 960 961 default: 962 error = ether_ioctl(ifp, cmd, data); 963 break; 964 } 965 966 splx(s); 967 return (error); 968 } 969 970 STATIC void 971 xi_set_address(struct xi_softc *sc) 972 { 973 bus_space_tag_t bst = sc->sc_bst; 974 bus_space_handle_t bsh = sc->sc_bsh; 975 struct ethercom *ether = &sc->sc_ethercom; 976 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 977 struct ether_multistep step; 978 struct ether_multi *enm; 979 int page, num; 980 int i; 981 u_int8_t x; 982 const u_int8_t *enaddr; 983 u_int8_t indaddr[64]; 984 985 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 986 987 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 988 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 989 for (i = 0; i < 6; i++) 990 indaddr[i] = enaddr[5 - i]; 991 else 992 for (i = 0; i < 6; i++) 993 indaddr[i] = enaddr[i]; 994 num = 1; 995 996 if (ether->ec_multicnt > 9) { 997 ifp->if_flags |= IFF_ALLMULTI; 998 goto done; 999 } 1000 1001 ETHER_FIRST_MULTI(step, ether, enm); 1002 for (; enm; num++) { 1003 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1004 sizeof(enm->enm_addrlo)) != 0) { 1005 /* 1006 * The multicast address is really a range; 1007 * it's easier just to accept all multicasts. 1008 * XXX should we be setting IFF_ALLMULTI here? 1009 */ 1010 ifp->if_flags |= IFF_ALLMULTI; 1011 goto done; 1012 } 1013 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1014 for (i = 0; i < 6; i++) 1015 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1016 else 1017 for (i = 0; i < 6; i++) 1018 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1019 ETHER_NEXT_MULTI(step, enm); 1020 } 1021 ifp->if_flags &= ~IFF_ALLMULTI; 1022 1023 done: 1024 if (num < 10) 1025 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1026 1027 for (page = 0; page < 8; page++) { 1028 #ifdef XIDEBUG 1029 if (xidebug & XID_MCAST) { 1030 printf("page %d before:", page); 1031 for (i = 0; i < 8; i++) 1032 printf(" %02x", indaddr[page * 8 + i]); 1033 printf("\n"); 1034 } 1035 #endif 1036 1037 PAGE(sc, 0x50 + page); 1038 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1039 page == 7 ? 4 : 8); 1040 /* 1041 * XXX 1042 * Without this delay, the address registers on my CE2 get 1043 * trashed the first and I have to cycle it. I have no idea 1044 * why. - mycroft, 2004/08/09 1045 */ 1046 DELAY(50); 1047 1048 #ifdef XIDEBUG 1049 if (xidebug & XID_MCAST) { 1050 bus_space_read_region_1(bst, bsh, IA, 1051 &indaddr[page * 8], page == 7 ? 4 : 8); 1052 printf("page %d after: ", page); 1053 for (i = 0; i < 8; i++) 1054 printf(" %02x", indaddr[page * 8 + i]); 1055 printf("\n"); 1056 } 1057 #endif 1058 } 1059 1060 PAGE(sc, 0x42); 1061 x = SWC1_IND_ADDR; 1062 if (ifp->if_flags & IFF_PROMISC) 1063 x |= SWC1_PROMISC; 1064 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1065 x |= SWC1_MCAST_PROM; 1066 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1067 x |= SWC1_AUTO_MEDIA; 1068 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1069 } 1070 1071 STATIC void 1072 xi_cycle_power(struct xi_softc *sc) 1073 { 1074 bus_space_tag_t bst = sc->sc_bst; 1075 bus_space_handle_t bsh = sc->sc_bsh; 1076 1077 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1078 1079 PAGE(sc, 4); 1080 DELAY(1); 1081 bus_space_write_1(bst, bsh, GP1, 0); 1082 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1083 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1084 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1085 else 1086 /* XXX What is bit 2 (aka AIC)? */ 1087 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1088 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1089 } 1090 1091 STATIC void 1092 xi_full_reset(struct xi_softc *sc) 1093 { 1094 bus_space_tag_t bst = sc->sc_bst; 1095 bus_space_handle_t bsh = sc->sc_bsh; 1096 u_int8_t x; 1097 1098 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1099 1100 /* Do an as extensive reset as possible on all functions. */ 1101 xi_cycle_power(sc); 1102 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1103 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1104 bus_space_write_1(bst, bsh, CR, 0); 1105 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1106 PAGE(sc, 4); 1107 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1108 /* 1109 * Drive GP1 low to power up ML6692 and GP2 high to power up 1110 * the 10MHz chip. XXX What chip is that? The phy? 1111 */ 1112 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1113 } 1114 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1115 1116 /* Get revision information. XXX Symbolic constants. */ 1117 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1118 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1119 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1120 1121 /* Media selection. XXX Maybe manual overriding too? */ 1122 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1123 /* 1124 * XXX I have no idea what this really does, it is from the 1125 * Linux driver. 1126 */ 1127 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1128 } 1129 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1130 1131 /* 1132 * Disable source insertion. 1133 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1134 */ 1135 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1136 PAGE(sc, 0x42); 1137 bus_space_write_1(bst, bsh, SWC0, 0x20); 1138 } 1139 1140 /* Set the local memory dividing line. */ 1141 if (sc->sc_rev != 1) { 1142 PAGE(sc, 2); 1143 /* XXX Symbolic constant preferrable. */ 1144 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1145 } 1146 1147 /* 1148 * Apparently the receive byte pointer can be bad after a reset, so 1149 * we hardwire it correctly. 1150 */ 1151 PAGE(sc, 0); 1152 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1153 1154 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1155 PAGE(sc, 0x40); 1156 bus_space_write_1(bst, bsh, RX0MSK, 1157 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1158 bus_space_write_1(bst, bsh, TX0MSK, 1159 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1160 SQE | TX_ABORT | TX_OK); 1161 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1162 /* XXX From Linux, dunno what 0xb0 means. */ 1163 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1164 bus_space_write_1(bst, bsh, RXST0, 0); 1165 bus_space_write_1(bst, bsh, TXST0, 0); 1166 bus_space_write_1(bst, bsh, TXST1, 0); 1167 1168 PAGE(sc, 2); 1169 1170 /* Enable MII function if available. */ 1171 x = 0; 1172 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1173 x |= SELECT_MII; 1174 bus_space_write_1(bst, bsh, MSR, x); 1175 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1176 1177 /* Configure the LED registers. */ 1178 /* XXX This is not good for 10base2. */ 1179 bus_space_write_1(bst, bsh, LED, 1180 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1181 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1182 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1183 1184 /* 1185 * The Linux driver says this: 1186 * We should switch back to page 0 to avoid a bug in revision 0 1187 * where regs with offset below 8 can't be read after an access 1188 * to the MAC registers. 1189 */ 1190 PAGE(sc, 0); 1191 } 1192