1 /* $NetBSD: if_xi.c,v 1.66 2009/03/14 15:36:20 dsl Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * Copyright (c) 2004 Charles M. Hannum. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Charles M. Hannum. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 */ 21 22 /* 23 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 24 * All rights reserved. 25 * 26 * Redistribution and use in source and binary forms, with or without 27 * modification, are permitted provided that the following conditions 28 * are met: 29 * 1. Redistributions of source code must retain the above copyright 30 * notice, this list of conditions and the following disclaimer. 31 * 2. Redistributions in binary form must reproduce the above copyright 32 * notice, this list of conditions and the following disclaimer in the 33 * documentation and/or other materials provided with the distribution. 34 * 3. All advertising materials mentioning features or use of this software 35 * must display the following acknowledgement: 36 * This product includes software developed by Niklas Hallqvist, 37 * Brandon Creighton and Job de Haas. 38 * 4. The name of the author may not be used to endorse or promote products 39 * derived from this software without specific prior written permission 40 * 41 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 42 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 43 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 44 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 45 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 46 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 47 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 48 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 49 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 50 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 51 */ 52 53 /* 54 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 55 */ 56 57 #include <sys/cdefs.h> 58 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.66 2009/03/14 15:36:20 dsl Exp $"); 59 60 #include "opt_inet.h" 61 #include "opt_ipx.h" 62 #include "bpfilter.h" 63 64 #include <sys/param.h> 65 #include <sys/systm.h> 66 #include <sys/device.h> 67 #include <sys/ioctl.h> 68 #include <sys/mbuf.h> 69 #include <sys/malloc.h> 70 #include <sys/socket.h> 71 #include <sys/kernel.h> 72 #include <sys/proc.h> 73 74 #include <net/if.h> 75 #include <net/if_dl.h> 76 #include <net/if_media.h> 77 #include <net/if_types.h> 78 #include <net/if_ether.h> 79 80 #ifdef INET 81 #include <netinet/in.h> 82 #include <netinet/in_systm.h> 83 #include <netinet/in_var.h> 84 #include <netinet/ip.h> 85 #include <netinet/if_inarp.h> 86 #endif 87 88 #ifdef IPX 89 #include <netipx/ipx.h> 90 #include <netipx/ipx_if.h> 91 #endif 92 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 /* 100 * Maximum number of bytes to read per interrupt. Linux recommends 101 * somewhere between 2000-22000. 102 * XXX This is currently a hard maximum. 103 */ 104 #define MAX_BYTES_INTR 12000 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/pcmcia/pcmciareg.h> 110 #include <dev/pcmcia/pcmciavar.h> 111 #include <dev/pcmcia/pcmciadevs.h> 112 113 #include <dev/pcmcia/if_xireg.h> 114 #include <dev/pcmcia/if_xivar.h> 115 116 #ifdef __GNUC__ 117 #define INLINE inline 118 #else 119 #define INLINE 120 #endif /* __GNUC__ */ 121 122 #define XIDEBUG 123 #define XIDEBUG_VALUE 0 124 125 #ifdef XIDEBUG 126 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 127 128 #define XID_CONFIG 0x01 129 #define XID_MII 0x02 130 #define XID_INTR 0x04 131 #define XID_FIFO 0x08 132 #define XID_MCAST 0x10 133 134 #ifdef XIDEBUG_VALUE 135 int xidebug = XIDEBUG_VALUE; 136 #else 137 int xidebug = 0; 138 #endif 139 #else 140 #define DPRINTF(cat, x) (void)0 141 #endif 142 143 #define STATIC 144 145 STATIC int xi_enable(struct xi_softc *); 146 STATIC void xi_disable(struct xi_softc *); 147 STATIC void xi_cycle_power(struct xi_softc *); 148 STATIC int xi_ether_ioctl(struct ifnet *, u_long cmd, void *); 149 STATIC void xi_full_reset(struct xi_softc *); 150 STATIC void xi_init(struct xi_softc *); 151 STATIC int xi_ioctl(struct ifnet *, u_long, void *); 152 STATIC int xi_mdi_read(struct device *, int, int); 153 STATIC void xi_mdi_write(struct device *, int, int, int); 154 STATIC int xi_mediachange(struct ifnet *); 155 STATIC u_int16_t xi_get(struct xi_softc *); 156 STATIC void xi_reset(struct xi_softc *); 157 STATIC void xi_set_address(struct xi_softc *); 158 STATIC void xi_start(struct ifnet *); 159 STATIC void xi_statchg(struct device *); 160 STATIC void xi_stop(struct xi_softc *); 161 STATIC void xi_watchdog(struct ifnet *); 162 163 void 164 xi_attach(struct xi_softc *sc, u_int8_t *myea) 165 { 166 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 167 168 #if 0 169 /* 170 * Configuration as advised by DINGO documentation. 171 * Dingo has some extra configuration registers in the CCR space. 172 */ 173 if (sc->sc_chipset >= XI_CHIPSET_DINGO) { 174 struct pcmcia_mem_handle pcmh; 175 int ccr_window; 176 bus_size_t ccr_offset; 177 178 /* get access to the DINGO CCR space */ 179 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 180 &pcmh)) { 181 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 182 goto fail; 183 } 184 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 185 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 186 &pcmh, &ccr_offset, &ccr_window)) { 187 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 188 pcmcia_mem_free(psc->sc_pf, &pcmh); 189 goto fail; 190 } 191 192 /* enable the second function - usually modem */ 193 bus_space_write_1(pcmh.memt, pcmh.memh, 194 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 195 bus_space_write_1(pcmh.memt, pcmh.memh, 196 ccr_offset + PCMCIA_CCR_DCOR1, 197 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 198 bus_space_write_1(pcmh.memt, pcmh.memh, 199 ccr_offset + PCMCIA_CCR_DCOR2, 0); 200 bus_space_write_1(pcmh.memt, pcmh.memh, 201 ccr_offset + PCMCIA_CCR_DCOR3, 0); 202 bus_space_write_1(pcmh.memt, pcmh.memh, 203 ccr_offset + PCMCIA_CCR_DCOR4, 0); 204 205 /* We don't need them anymore and can free them (I think). */ 206 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 207 pcmcia_mem_free(psc->sc_pf, &pcmh); 208 } 209 #endif 210 211 /* Reset and initialize the card. */ 212 xi_full_reset(sc); 213 214 printf("%s: MAC address %s\n", device_xname(&sc->sc_dev), ether_sprintf(myea)); 215 216 ifp = &sc->sc_ethercom.ec_if; 217 /* Initialize the ifnet structure. */ 218 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 219 ifp->if_softc = sc; 220 ifp->if_start = xi_start; 221 ifp->if_ioctl = xi_ioctl; 222 ifp->if_watchdog = xi_watchdog; 223 ifp->if_flags = 224 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 225 IFQ_SET_READY(&ifp->if_snd); 226 227 /* 802.1q capability */ 228 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 229 230 /* Attach the interface. */ 231 if_attach(ifp); 232 ether_ifattach(ifp, myea); 233 234 /* 235 * Initialize our media structures and probe the MII. 236 */ 237 sc->sc_mii.mii_ifp = ifp; 238 sc->sc_mii.mii_readreg = xi_mdi_read; 239 sc->sc_mii.mii_writereg = xi_mdi_write; 240 sc->sc_mii.mii_statchg = xi_statchg; 241 sc->sc_ethercom.ec_mii = &sc->sc_mii; 242 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 243 ether_mediastatus); 244 DPRINTF(XID_MII | XID_CONFIG, 245 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 246 247 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 248 MII_OFFSET_ANY, 0); 249 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 250 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 251 NULL); 252 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 253 254 #if NRND > 0 255 rnd_attach_source(&sc->sc_rnd_source, device_xname(&sc->sc_dev), RND_TYPE_NET, 0); 256 #endif 257 } 258 259 int 260 xi_detach(struct device *self, int flags) 261 { 262 struct xi_softc *sc = (void *)self; 263 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 264 265 DPRINTF(XID_CONFIG, ("xi_detach()\n")); 266 267 xi_disable(sc); 268 269 #if NRND > 0 270 rnd_detach_source(&sc->sc_rnd_source); 271 #endif 272 273 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 274 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 275 ether_ifdetach(ifp); 276 if_detach(ifp); 277 278 return 0; 279 } 280 281 int 282 xi_activate(struct device *self, enum devact act) 283 { 284 struct xi_softc *sc = (void *)self; 285 int s, rv = 0; 286 287 DPRINTF(XID_CONFIG, ("xi_activate()\n")); 288 289 s = splnet(); 290 switch (act) { 291 case DVACT_ACTIVATE: 292 rv = EOPNOTSUPP; 293 break; 294 295 case DVACT_DEACTIVATE: 296 if_deactivate(&sc->sc_ethercom.ec_if); 297 break; 298 } 299 splx(s); 300 return (rv); 301 } 302 303 int 304 xi_intr(void *arg) 305 { 306 struct xi_softc *sc = arg; 307 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 308 u_int8_t esr, rsr, isr, rx_status; 309 u_int16_t tx_status, recvcount = 0, tempint; 310 311 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 312 313 if (sc->sc_enabled == 0 || 314 !device_is_active(&sc->sc_dev)) 315 return (0); 316 317 ifp->if_timer = 0; /* turn watchdog timer off */ 318 319 PAGE(sc, 0); 320 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 321 /* Disable interrupt (Linux does it). */ 322 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, 0); 323 } 324 325 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 326 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ISR0); 327 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 328 329 /* Check to see if card has been ejected. */ 330 if (isr == 0xff) { 331 #ifdef DIAGNOSTIC 332 printf("%s: interrupt for dead card\n", device_xname(&sc->sc_dev)); 333 #endif 334 goto end; 335 } 336 DPRINTF(XID_INTR, ("xi: isr=%02x\n", isr)); 337 338 PAGE(sc, 0x40); 339 rx_status = 340 bus_space_read_1(sc->sc_bst, sc->sc_bsh, RXST0); 341 bus_space_write_1(sc->sc_bst, sc->sc_bsh, RXST0, ~rx_status & 0xff); 342 tx_status = 343 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST0); 344 tx_status |= 345 bus_space_read_1(sc->sc_bst, sc->sc_bsh, TXST1) << 8; 346 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST0, 0); 347 bus_space_write_1(sc->sc_bst, sc->sc_bsh, TXST1, 0); 348 DPRINTF(XID_INTR, ("xi: rx_status=%02x tx_status=%04x\n", rx_status, 349 tx_status)); 350 351 PAGE(sc, 0); 352 while (esr & FULL_PKT_RCV) { 353 if (!(rsr & RSR_RX_OK)) 354 break; 355 356 /* Compare bytes read this interrupt to hard maximum. */ 357 if (recvcount > MAX_BYTES_INTR) { 358 DPRINTF(XID_INTR, 359 ("xi: too many bytes this interrupt\n")); 360 ifp->if_iqdrops++; 361 /* Drop packet. */ 362 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, 363 DO_SKIP_RX_PKT); 364 } 365 tempint = xi_get(sc); /* XXX doesn't check the error! */ 366 recvcount += tempint; 367 ifp->if_ibytes += tempint; 368 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, ESR); 369 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, RSR); 370 } 371 372 /* Packet too long? */ 373 if (rsr & RSR_TOO_LONG) { 374 ifp->if_ierrors++; 375 DPRINTF(XID_INTR, ("xi: packet too long\n")); 376 } 377 378 /* CRC error? */ 379 if (rsr & RSR_CRCERR) { 380 ifp->if_ierrors++; 381 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 382 } 383 384 /* Alignment error? */ 385 if (rsr & RSR_ALIGNERR) { 386 ifp->if_ierrors++; 387 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 388 } 389 390 /* Check for rx overrun. */ 391 if (rx_status & RX_OVERRUN) { 392 ifp->if_ierrors++; 393 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, CLR_RX_OVERRUN); 394 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 395 } 396 397 /* Try to start more packets transmitting. */ 398 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 399 xi_start(ifp); 400 401 /* Detected excessive collisions? */ 402 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 403 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 404 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, RESTART_TX); 405 ifp->if_oerrors++; 406 } 407 408 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 409 ifp->if_oerrors++; 410 411 /* have handled the interrupt */ 412 #if NRND > 0 413 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 414 #endif 415 416 end: 417 /* Reenable interrupts. */ 418 PAGE(sc, 0); 419 bus_space_write_1(sc->sc_bst, sc->sc_bsh, CR, ENABLE_INT); 420 421 return (1); 422 } 423 424 /* 425 * Pull a packet from the card into an mbuf chain. 426 */ 427 STATIC u_int16_t 428 xi_get(struct xi_softc *sc) 429 { 430 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 431 struct mbuf *top, **mp, *m; 432 u_int16_t pktlen, len, recvcount = 0; 433 u_int8_t *data; 434 435 DPRINTF(XID_CONFIG, ("xi_get()\n")); 436 437 PAGE(sc, 0); 438 pktlen = 439 bus_space_read_2(sc->sc_bst, sc->sc_bsh, RBC0) & RBC_COUNT_MASK; 440 441 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 442 443 if (pktlen == 0) { 444 /* 445 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 446 * when MPE is set. It is not known why. 447 */ 448 return (0); 449 } 450 451 /* XXX should this be incremented now ? */ 452 recvcount += pktlen; 453 454 MGETHDR(m, M_DONTWAIT, MT_DATA); 455 if (m == NULL) 456 return (recvcount); 457 m->m_pkthdr.rcvif = ifp; 458 m->m_pkthdr.len = pktlen; 459 len = MHLEN; 460 top = NULL; 461 mp = ⊤ 462 463 while (pktlen > 0) { 464 if (top) { 465 MGET(m, M_DONTWAIT, MT_DATA); 466 if (m == NULL) { 467 m_freem(top); 468 return (recvcount); 469 } 470 len = MLEN; 471 } 472 if (pktlen >= MINCLSIZE) { 473 MCLGET(m, M_DONTWAIT); 474 if (!(m->m_flags & M_EXT)) { 475 m_freem(m); 476 m_freem(top); 477 return (recvcount); 478 } 479 len = MCLBYTES; 480 } 481 if (top == NULL) { 482 char *newdata = (char *)ALIGN(m->m_data + 483 sizeof(struct ether_header)) - 484 sizeof(struct ether_header); 485 len -= newdata - m->m_data; 486 m->m_data = newdata; 487 } 488 len = min(pktlen, len); 489 data = mtod(m, u_int8_t *); 490 if (len > 1) { 491 len &= ~1; 492 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, EDP, 493 (u_int16_t *)data, len>>1); 494 } else 495 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, EDP); 496 m->m_len = len; 497 pktlen -= len; 498 *mp = m; 499 mp = &m->m_next; 500 } 501 502 /* Skip Rx packet. */ 503 bus_space_write_2(sc->sc_bst, sc->sc_bsh, DO0, DO_SKIP_RX_PKT); 504 505 if (top == NULL) 506 return recvcount; 507 508 /* Trim the CRC off the end of the packet. */ 509 m_adj(top, -ETHER_CRC_LEN); 510 511 ifp->if_ipackets++; 512 513 #if NBPFILTER > 0 514 if (ifp->if_bpf) 515 bpf_mtap(ifp->if_bpf, top); 516 #endif 517 518 (*ifp->if_input)(ifp, top); 519 return (recvcount); 520 } 521 522 /* 523 * Serial management for the MII. 524 * The DELAY's below stem from the fact that the maximum frequency 525 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 526 * go much faster than that. 527 */ 528 529 /* Let the MII serial management be idle for one period. */ 530 static INLINE void xi_mdi_idle(struct xi_softc *); 531 static INLINE void 532 xi_mdi_idle(struct xi_softc *sc) 533 { 534 bus_space_tag_t bst = sc->sc_bst; 535 bus_space_handle_t bsh = sc->sc_bsh; 536 537 /* Drive MDC low... */ 538 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 539 DELAY(1); 540 541 /* and high again. */ 542 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 543 DELAY(1); 544 } 545 546 /* Pulse out one bit of data. */ 547 static INLINE void xi_mdi_pulse(struct xi_softc *, int); 548 static INLINE void 549 xi_mdi_pulse(struct xi_softc *sc, int data) 550 { 551 bus_space_tag_t bst = sc->sc_bst; 552 bus_space_handle_t bsh = sc->sc_bsh; 553 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 554 555 /* First latch the data bit MDIO with clock bit MDC low...*/ 556 bus_space_write_1(bst, bsh, GP2, bit | MDC_LOW); 557 DELAY(1); 558 559 /* then raise the clock again, preserving the data bit. */ 560 bus_space_write_1(bst, bsh, GP2, bit | MDC_HIGH); 561 DELAY(1); 562 } 563 564 /* Probe one bit of data. */ 565 static INLINE int xi_mdi_probe(struct xi_softc *sc); 566 static INLINE int 567 xi_mdi_probe(struct xi_softc *sc) 568 { 569 bus_space_tag_t bst = sc->sc_bst; 570 bus_space_handle_t bsh = sc->sc_bsh; 571 u_int8_t x; 572 573 /* Pull clock bit MDCK low... */ 574 bus_space_write_1(bst, bsh, GP2, MDC_LOW); 575 DELAY(1); 576 577 /* Read data and drive clock high again. */ 578 x = bus_space_read_1(bst, bsh, GP2); 579 bus_space_write_1(bst, bsh, GP2, MDC_HIGH); 580 DELAY(1); 581 582 return (x & MDIO); 583 } 584 585 /* Pulse out a sequence of data bits. */ 586 static INLINE void xi_mdi_pulse_bits(struct xi_softc *, u_int32_t, int); 587 static INLINE void 588 xi_mdi_pulse_bits(struct xi_softc *sc, u_int32_t data, int len) 589 { 590 u_int32_t mask; 591 592 for (mask = 1 << (len - 1); mask; mask >>= 1) 593 xi_mdi_pulse(sc, data & mask); 594 } 595 596 /* Read a PHY register. */ 597 STATIC int 598 xi_mdi_read(struct device *self, int phy, int reg) 599 { 600 struct xi_softc *sc = (struct xi_softc *)self; 601 int i; 602 u_int32_t mask; 603 u_int32_t data = 0; 604 605 PAGE(sc, 2); 606 for (i = 0; i < 32; i++) /* Synchronize. */ 607 xi_mdi_pulse(sc, 1); 608 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 609 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 610 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 611 xi_mdi_idle(sc); /* Turn around. */ 612 xi_mdi_probe(sc); /* Drop initial zero bit. */ 613 614 for (mask = 1 << 15; mask; mask >>= 1) { 615 if (xi_mdi_probe(sc)) 616 data |= mask; 617 } 618 xi_mdi_idle(sc); 619 620 DPRINTF(XID_MII, 621 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 622 623 return (data); 624 } 625 626 /* Write a PHY register. */ 627 STATIC void 628 xi_mdi_write(struct device *self, int phy, int reg, int value) 629 { 630 struct xi_softc *sc = (struct xi_softc *)self; 631 int i; 632 633 PAGE(sc, 2); 634 for (i = 0; i < 32; i++) /* Synchronize. */ 635 xi_mdi_pulse(sc, 1); 636 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 637 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 638 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 639 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 640 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 641 xi_mdi_idle(sc); /* Idle away. */ 642 643 DPRINTF(XID_MII, 644 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 645 } 646 647 STATIC void 648 xi_statchg(struct device *self) 649 { 650 /* XXX Update ifp->if_baudrate */ 651 } 652 653 /* 654 * Change media according to request. 655 */ 656 STATIC int 657 xi_mediachange(struct ifnet *ifp) 658 { 659 int s; 660 661 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 662 663 if (ifp->if_flags & IFF_UP) { 664 s = splnet(); 665 xi_init(ifp->if_softc); 666 splx(s); 667 } 668 return (0); 669 } 670 671 STATIC void 672 xi_reset(struct xi_softc *sc) 673 { 674 int s; 675 676 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 677 678 s = splnet(); 679 xi_stop(sc); 680 xi_init(sc); 681 splx(s); 682 } 683 684 STATIC void 685 xi_watchdog(struct ifnet *ifp) 686 { 687 struct xi_softc *sc = ifp->if_softc; 688 689 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 690 ++ifp->if_oerrors; 691 692 xi_reset(sc); 693 } 694 695 STATIC void 696 xi_stop(register struct xi_softc *sc) 697 { 698 bus_space_tag_t bst = sc->sc_bst; 699 bus_space_handle_t bsh = sc->sc_bsh; 700 701 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 702 703 PAGE(sc, 0x40); 704 bus_space_write_1(bst, bsh, CMD0, DISABLE_RX); 705 706 /* Disable interrupts. */ 707 PAGE(sc, 0); 708 bus_space_write_1(bst, bsh, CR, 0); 709 710 PAGE(sc, 1); 711 bus_space_write_1(bst, bsh, IMR0, 0); 712 713 /* Cancel watchdog timer. */ 714 sc->sc_ethercom.ec_if.if_timer = 0; 715 } 716 717 STATIC int 718 xi_enable(struct xi_softc *sc) 719 { 720 int error; 721 722 if (!sc->sc_enabled) { 723 error = (*sc->sc_enable)(sc); 724 if (error) 725 return (error); 726 sc->sc_enabled = 1; 727 xi_full_reset(sc); 728 } 729 return (0); 730 } 731 732 STATIC void 733 xi_disable(struct xi_softc *sc) 734 { 735 736 if (sc->sc_enabled) { 737 sc->sc_enabled = 0; 738 (*sc->sc_disable)(sc); 739 } 740 } 741 742 STATIC void 743 xi_init(struct xi_softc *sc) 744 { 745 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 746 bus_space_tag_t bst = sc->sc_bst; 747 bus_space_handle_t bsh = sc->sc_bsh; 748 749 DPRINTF(XID_CONFIG, ("xi_init()\n")); 750 751 /* Setup the ethernet interrupt mask. */ 752 PAGE(sc, 1); 753 bus_space_write_1(bst, bsh, IMR0, 754 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 755 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 756 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 757 /* XXX What is this? Not for Dingo at least. */ 758 /* Unmask TX underrun detection */ 759 bus_space_write_1(bst, bsh, IMR1, 1); 760 } 761 762 /* Enable interrupts. */ 763 PAGE(sc, 0); 764 bus_space_write_1(bst, bsh, CR, ENABLE_INT); 765 766 xi_set_address(sc); 767 768 PAGE(sc, 0x40); 769 bus_space_write_1(bst, bsh, CMD0, ENABLE_RX | ONLINE); 770 771 PAGE(sc, 0); 772 773 /* Set current media. */ 774 mii_mediachg(&sc->sc_mii); 775 776 ifp->if_flags |= IFF_RUNNING; 777 ifp->if_flags &= ~IFF_OACTIVE; 778 779 xi_start(ifp); 780 } 781 782 /* 783 * Start outputting on the interface. 784 * Always called as splnet(). 785 */ 786 STATIC void 787 xi_start(struct ifnet *ifp) 788 { 789 struct xi_softc *sc = ifp->if_softc; 790 bus_space_tag_t bst = sc->sc_bst; 791 bus_space_handle_t bsh = sc->sc_bsh; 792 unsigned int s, len, pad = 0; 793 struct mbuf *m0, *m; 794 u_int16_t space; 795 796 DPRINTF(XID_CONFIG, ("xi_start()\n")); 797 798 /* Don't transmit if interface is busy or not running. */ 799 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 800 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 801 return; 802 } 803 804 /* Peek at the next packet. */ 805 IFQ_POLL(&ifp->if_snd, m0); 806 if (m0 == 0) 807 return; 808 809 /* We need to use m->m_pkthdr.len, so require the header. */ 810 if (!(m0->m_flags & M_PKTHDR)) 811 panic("xi_start: no header mbuf"); 812 813 len = m0->m_pkthdr.len; 814 815 #if 1 816 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 817 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 818 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 819 #else 820 pad = 0; 821 #endif 822 823 PAGE(sc, 0); 824 825 bus_space_write_2(bst, bsh, TRS, (u_int16_t)len + pad + 2); 826 space = bus_space_read_2(bst, bsh, TSO) & 0x7fff; 827 if (len + pad + 2 > space) { 828 DPRINTF(XID_FIFO, 829 ("xi: not enough space in output FIFO (%d > %d)\n", 830 len + pad + 2, space)); 831 return; 832 } 833 834 IFQ_DEQUEUE(&ifp->if_snd, m0); 835 836 #if NBPFILTER > 0 837 if (ifp->if_bpf) 838 bpf_mtap(ifp->if_bpf, m0); 839 #endif 840 841 /* 842 * Do the output at splhigh() so that an interrupt from another device 843 * won't cause a FIFO underrun. 844 */ 845 s = splhigh(); 846 847 bus_space_write_2(bst, bsh, EDP, (u_int16_t)len + pad); 848 for (m = m0; m; ) { 849 if (m->m_len > 1) 850 bus_space_write_multi_2(bst, bsh, EDP, 851 mtod(m, u_int16_t *), m->m_len>>1); 852 if (m->m_len & 1) { 853 DPRINTF(XID_CONFIG, ("xi: XXX odd!\n")); 854 bus_space_write_1(bst, bsh, EDP, 855 *(mtod(m, u_int8_t *) + m->m_len - 1)); 856 } 857 MFREE(m, m0); 858 m = m0; 859 } 860 DPRINTF(XID_CONFIG, ("xi: len=%d pad=%d total=%d\n", len, pad, len+pad+4)); 861 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 862 bus_space_write_1(bst, bsh, CR, TX_PKT | ENABLE_INT); 863 else { 864 for (; pad > 1; pad -= 2) 865 bus_space_write_2(bst, bsh, EDP, 0); 866 if (pad == 1) 867 bus_space_write_1(bst, bsh, EDP, 0); 868 } 869 870 splx(s); 871 872 ifp->if_timer = 5; 873 ++ifp->if_opackets; 874 } 875 876 STATIC int 877 xi_ether_ioctl(struct ifnet *ifp, u_long cmd, void *data) 878 { 879 struct ifaddr *ifa = (struct ifaddr *)data; 880 struct xi_softc *sc = ifp->if_softc; 881 int error; 882 883 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 884 885 switch (cmd) { 886 case SIOCINITIFADDR: 887 if ((error = xi_enable(sc)) != 0) 888 break; 889 890 ifp->if_flags |= IFF_UP; 891 892 xi_init(sc); 893 switch (ifa->ifa_addr->sa_family) { 894 #ifdef INET 895 case AF_INET: 896 arp_ifinit(ifp, ifa); 897 break; 898 #endif /* INET */ 899 900 901 default: 902 break; 903 } 904 break; 905 906 default: 907 return (EINVAL); 908 } 909 910 return (0); 911 } 912 913 STATIC int 914 xi_ioctl(struct ifnet *ifp, u_long cmd, void *data) 915 { 916 struct xi_softc *sc = ifp->if_softc; 917 int s, error = 0; 918 919 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 920 921 s = splnet(); 922 923 switch (cmd) { 924 case SIOCINITIFADDR: 925 error = xi_ether_ioctl(ifp, cmd, data); 926 break; 927 928 case SIOCSIFFLAGS: 929 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 930 break; 931 /* XXX re-use ether_ioctl() */ 932 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 933 case IFF_RUNNING: 934 /* 935 * If interface is marked down and it is running, 936 * stop it. 937 */ 938 xi_stop(sc); 939 ifp->if_flags &= ~IFF_RUNNING; 940 xi_disable(sc); 941 break; 942 case IFF_UP: 943 /* 944 * If interface is marked up and it is stopped, 945 * start it. 946 */ 947 if ((error = xi_enable(sc)) != 0) 948 break; 949 xi_init(sc); 950 break; 951 case IFF_UP|IFF_RUNNING: 952 /* 953 * Reset the interface to pick up changes in any 954 * other flags that affect hardware registers. 955 */ 956 xi_set_address(sc); 957 break; 958 case 0: 959 break; 960 } 961 break; 962 963 case SIOCADDMULTI: 964 case SIOCDELMULTI: 965 if (sc->sc_enabled == 0) { 966 error = EIO; 967 break; 968 } 969 /*FALLTHROUGH*/ 970 case SIOCSIFMEDIA: 971 case SIOCGIFMEDIA: 972 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 973 /* 974 * Multicast list has changed; set the hardware 975 * filter accordingly. 976 */ 977 if (ifp->if_flags & IFF_RUNNING) 978 xi_set_address(sc); 979 error = 0; 980 } 981 break; 982 983 default: 984 error = ether_ioctl(ifp, cmd, data); 985 break; 986 } 987 988 splx(s); 989 return (error); 990 } 991 992 STATIC void 993 xi_set_address(struct xi_softc *sc) 994 { 995 bus_space_tag_t bst = sc->sc_bst; 996 bus_space_handle_t bsh = sc->sc_bsh; 997 struct ethercom *ether = &sc->sc_ethercom; 998 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 999 struct ether_multistep step; 1000 struct ether_multi *enm; 1001 int page, num; 1002 int i; 1003 u_int8_t x; 1004 const u_int8_t *enaddr; 1005 u_int8_t indaddr[64]; 1006 1007 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1008 1009 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 1010 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1011 for (i = 0; i < 6; i++) 1012 indaddr[i] = enaddr[5 - i]; 1013 else 1014 for (i = 0; i < 6; i++) 1015 indaddr[i] = enaddr[i]; 1016 num = 1; 1017 1018 if (ether->ec_multicnt > 9) { 1019 ifp->if_flags |= IFF_ALLMULTI; 1020 goto done; 1021 } 1022 1023 ETHER_FIRST_MULTI(step, ether, enm); 1024 for (; enm; num++) { 1025 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1026 sizeof(enm->enm_addrlo)) != 0) { 1027 /* 1028 * The multicast address is really a range; 1029 * it's easier just to accept all multicasts. 1030 * XXX should we be setting IFF_ALLMULTI here? 1031 */ 1032 ifp->if_flags |= IFF_ALLMULTI; 1033 goto done; 1034 } 1035 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1036 for (i = 0; i < 6; i++) 1037 indaddr[num * 6 + i] = enm->enm_addrlo[5 - i]; 1038 else 1039 for (i = 0; i < 6; i++) 1040 indaddr[num * 6 + i] = enm->enm_addrlo[i]; 1041 ETHER_NEXT_MULTI(step, enm); 1042 } 1043 ifp->if_flags &= ~IFF_ALLMULTI; 1044 1045 done: 1046 if (num < 10) 1047 memset(&indaddr[num * 6], 0xff, 6 * (10 - num)); 1048 1049 for (page = 0; page < 8; page++) { 1050 #ifdef XIDEBUG 1051 if (xidebug & XID_MCAST) { 1052 printf("page %d before:", page); 1053 for (i = 0; i < 8; i++) 1054 printf(" %02x", indaddr[page * 8 + i]); 1055 printf("\n"); 1056 } 1057 #endif 1058 1059 PAGE(sc, 0x50 + page); 1060 bus_space_write_region_1(bst, bsh, IA, &indaddr[page * 8], 1061 page == 7 ? 4 : 8); 1062 /* 1063 * XXX 1064 * Without this delay, the address registers on my CE2 get 1065 * trashed the first and I have to cycle it. I have no idea 1066 * why. - mycroft, 2004/08/09 1067 */ 1068 DELAY(50); 1069 1070 #ifdef XIDEBUG 1071 if (xidebug & XID_MCAST) { 1072 bus_space_read_region_1(bst, bsh, IA, 1073 &indaddr[page * 8], page == 7 ? 4 : 8); 1074 printf("page %d after: ", page); 1075 for (i = 0; i < 8; i++) 1076 printf(" %02x", indaddr[page * 8 + i]); 1077 printf("\n"); 1078 } 1079 #endif 1080 } 1081 1082 PAGE(sc, 0x42); 1083 x = SWC1_IND_ADDR; 1084 if (ifp->if_flags & IFF_PROMISC) 1085 x |= SWC1_PROMISC; 1086 if (ifp->if_flags & (IFF_ALLMULTI|IFF_PROMISC)) 1087 x |= SWC1_MCAST_PROM; 1088 if (!LIST_FIRST(&sc->sc_mii.mii_phys)) 1089 x |= SWC1_AUTO_MEDIA; 1090 bus_space_write_1(sc->sc_bst, sc->sc_bsh, SWC1, x); 1091 } 1092 1093 STATIC void 1094 xi_cycle_power(struct xi_softc *sc) 1095 { 1096 bus_space_tag_t bst = sc->sc_bst; 1097 bus_space_handle_t bsh = sc->sc_bsh; 1098 1099 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1100 1101 PAGE(sc, 4); 1102 DELAY(1); 1103 bus_space_write_1(bst, bsh, GP1, 0); 1104 tsleep(&xi_cycle_power, PWAIT, "xipwr1", hz * 40 / 1000); 1105 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) 1106 bus_space_write_1(bst, bsh, GP1, POWER_UP); 1107 else 1108 /* XXX What is bit 2 (aka AIC)? */ 1109 bus_space_write_1(bst, bsh, GP1, POWER_UP | 4); 1110 tsleep(&xi_cycle_power, PWAIT, "xipwr2", hz * 20 / 1000); 1111 } 1112 1113 STATIC void 1114 xi_full_reset(struct xi_softc *sc) 1115 { 1116 bus_space_tag_t bst = sc->sc_bst; 1117 bus_space_handle_t bsh = sc->sc_bsh; 1118 u_int8_t x; 1119 1120 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1121 1122 /* Do an as extensive reset as possible on all functions. */ 1123 xi_cycle_power(sc); 1124 bus_space_write_1(bst, bsh, CR, SOFT_RESET); 1125 tsleep(&xi_full_reset, PWAIT, "xirst1", hz * 20 / 1000); 1126 bus_space_write_1(bst, bsh, CR, 0); 1127 tsleep(&xi_full_reset, PWAIT, "xirst2", hz * 20 / 1000); 1128 PAGE(sc, 4); 1129 if (sc->sc_chipset >= XI_CHIPSET_MOHAWK) { 1130 /* 1131 * Drive GP1 low to power up ML6692 and GP2 high to power up 1132 * the 10MHz chip. XXX What chip is that? The phy? 1133 */ 1134 bus_space_write_1(bst, bsh, GP0, GP1_OUT | GP2_OUT | GP2_WR); 1135 } 1136 tsleep(&xi_full_reset, PWAIT, "xirst3", hz * 500 / 1000); 1137 1138 /* Get revision information. XXX Symbolic constants. */ 1139 sc->sc_rev = bus_space_read_1(bst, bsh, BV) & 1140 ((sc->sc_chipset >= XI_CHIPSET_MOHAWK) ? 0x70 : 0x30) >> 4; 1141 DPRINTF(XID_CONFIG, ("xi: rev=%02x\n", sc->sc_rev)); 1142 1143 /* Media selection. XXX Maybe manual overriding too? */ 1144 if (sc->sc_chipset < XI_CHIPSET_MOHAWK) { 1145 /* 1146 * XXX I have no idea what this really does, it is from the 1147 * Linux driver. 1148 */ 1149 bus_space_write_1(bst, bsh, GP0, GP1_OUT); 1150 } 1151 tsleep(&xi_full_reset, PWAIT, "xirst4", hz * 40 / 1000); 1152 1153 /* 1154 * Disable source insertion. 1155 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1156 */ 1157 if (sc->sc_chipset < XI_CHIPSET_DINGO) { 1158 PAGE(sc, 0x42); 1159 bus_space_write_1(bst, bsh, SWC0, 0x20); 1160 } 1161 1162 /* Set the local memory dividing line. */ 1163 if (sc->sc_rev != 1) { 1164 PAGE(sc, 2); 1165 /* XXX Symbolic constant preferrable. */ 1166 bus_space_write_2(bst, bsh, RBS0, 0x2000); 1167 } 1168 1169 /* 1170 * Apparently the receive byte pointer can be bad after a reset, so 1171 * we hardwire it correctly. 1172 */ 1173 PAGE(sc, 0); 1174 bus_space_write_2(bst, bsh, DO0, DO_CHG_OFFSET); 1175 1176 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1177 PAGE(sc, 0x40); 1178 bus_space_write_1(bst, bsh, RX0MSK, 1179 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1180 bus_space_write_1(bst, bsh, TX0MSK, 1181 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1182 SQE | TX_ABORT | TX_OK); 1183 if (sc->sc_chipset < XI_CHIPSET_DINGO) 1184 /* XXX From Linux, dunno what 0xb0 means. */ 1185 bus_space_write_1(bst, bsh, TX1MSK, 0xb0); 1186 bus_space_write_1(bst, bsh, RXST0, 0); 1187 bus_space_write_1(bst, bsh, TXST0, 0); 1188 bus_space_write_1(bst, bsh, TXST1, 0); 1189 1190 PAGE(sc, 2); 1191 1192 /* Enable MII function if available. */ 1193 x = 0; 1194 if (LIST_FIRST(&sc->sc_mii.mii_phys)) 1195 x |= SELECT_MII; 1196 bus_space_write_1(bst, bsh, MSR, x); 1197 tsleep(&xi_full_reset, PWAIT, "xirst5", hz * 20 / 1000); 1198 1199 /* Configure the LED registers. */ 1200 /* XXX This is not good for 10base2. */ 1201 bus_space_write_1(bst, bsh, LED, 1202 (LED_TX_ACT << LED1_SHIFT) | (LED_10MB_LINK << LED0_SHIFT)); 1203 if (sc->sc_chipset >= XI_CHIPSET_DINGO) 1204 bus_space_write_1(bst, bsh, LED3, LED_100MB_LINK << LED3_SHIFT); 1205 1206 /* 1207 * The Linux driver says this: 1208 * We should switch back to page 0 to avoid a bug in revision 0 1209 * where regs with offset below 8 can't be read after an access 1210 * to the MAC registers. 1211 */ 1212 PAGE(sc, 0); 1213 } 1214