1 /* $NetBSD: if_xi.c,v 1.18 2001/11/13 07:26:33 lukem Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.18 2001/11/13 07:26:33 lukem Exp $"); 53 54 #include "opt_inet.h" 55 #include "bpfilter.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/socket.h> 64 65 #include "rnd.h" 66 #if NRND > 0 67 #include <sys/rnd.h> 68 #endif 69 70 #include <net/if.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 #include <net/if_types.h> 74 #include <net/if_ether.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #include <netinet/if_inarp.h> 82 #endif 83 84 #ifdef IPX 85 #include <netipx/ipx.h> 86 #include <netipx/ipx_if.h> 87 #endif 88 89 #ifdef NS 90 #include <netns/ns.h> 91 #include <netns/ns_if.h> 92 #endif 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 #define ETHER_MIN_LEN 64 100 #define ETHER_CRC_LEN 4 101 102 /* 103 * Maximum number of bytes to read per interrupt. Linux recommends 104 * somewhere between 2000-22000. 105 * XXX This is currently a hard maximum. 106 */ 107 #define MAX_BYTES_INTR 12000 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 112 #include <dev/pcmcia/pcmciareg.h> 113 #include <dev/pcmcia/pcmciavar.h> 114 #include <dev/pcmcia/pcmciadevs.h> 115 116 #include <dev/pcmcia/if_xireg.h> 117 118 #ifdef __GNUC__ 119 #define INLINE __inline 120 #else 121 #define INLINE 122 #endif /* __GNUC__ */ 123 124 #ifdef XIDEBUG 125 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 126 127 #define XID_CONFIG 0x1 128 #define XID_MII 0x2 129 #define XID_INTR 0x4 130 #define XID_FIFO 0x8 131 132 #ifdef XIDEBUG_VALUE 133 int xidebug = XIDEBUG_VALUE; 134 #else 135 int xidebug = 0; 136 #endif 137 #else 138 #define DPRINTF(cat, x) (void)0 139 #endif 140 141 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 142 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 143 int xi_pcmcia_detach __P((struct device *, int)); 144 int xi_pcmcia_activate __P((struct device *, enum devact)); 145 146 /* 147 * In case this chipset ever turns up out of pcmcia attachments (very 148 * unlikely) do the driver splitup. 149 */ 150 struct xi_softc { 151 struct device sc_dev; /* Generic device info */ 152 struct ethercom sc_ethercom; /* Ethernet common part */ 153 154 struct mii_data sc_mii; /* MII media information */ 155 156 bus_space_tag_t sc_bst; /* Bus cookie */ 157 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 158 bus_addr_t sc_offset; /* Offset of registers */ 159 160 u_int8_t sc_rev; /* Chip revision */ 161 u_int32_t sc_flags; /* Misc. flags */ 162 int sc_all_mcasts; /* Receive all multicasts */ 163 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 164 #if NRND > 0 165 rndsource_element_t sc_rnd_source; 166 #endif 167 }; 168 169 struct xi_pcmcia_softc { 170 struct xi_softc sc_xi; /* Generic device info */ 171 172 /* PCMCIA-specific goo */ 173 struct pcmcia_function *sc_pf; /* PCMCIA function */ 174 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 175 int sc_io_window; /* io window info */ 176 void *sc_ih; /* Interrupt handler */ 177 void *sc_powerhook; /* power hook descriptor */ 178 int sc_resource; /* resource allocated */ 179 #define XI_RES_PCIC 1 180 #define XI_RES_IO_ALLOC 2 181 #define XI_RES_IO_MAP 4 182 #define XI_RES_MI 8 183 }; 184 185 struct cfattach xi_pcmcia_ca = { 186 sizeof(struct xi_pcmcia_softc), 187 xi_pcmcia_match, 188 xi_pcmcia_attach, 189 xi_pcmcia_detach, 190 xi_pcmcia_activate 191 }; 192 193 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 194 static void xi_cycle_power __P((struct xi_softc *)); 195 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 196 static void xi_full_reset __P((struct xi_softc *)); 197 static void xi_init __P((struct xi_softc *)); 198 static int xi_intr __P((void *)); 199 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 200 static int xi_mdi_read __P((struct device *, int, int)); 201 static void xi_mdi_write __P((struct device *, int, int, int)); 202 static int xi_mediachange __P((struct ifnet *)); 203 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 204 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 205 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 206 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 207 static u_int16_t xi_get __P((struct xi_softc *)); 208 static void xi_reset __P((struct xi_softc *)); 209 static void xi_set_address __P((struct xi_softc *)); 210 static void xi_start __P((struct ifnet *)); 211 static void xi_statchg __P((struct device *)); 212 static void xi_stop __P((struct xi_softc *)); 213 static void xi_watchdog __P((struct ifnet *)); 214 const struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 215 struct pcmcia_attach_args *)); 216 static int xi_pcmcia_enable __P((struct xi_pcmcia_softc *)); 217 static void xi_pcmcia_disable __P((struct xi_pcmcia_softc *)); 218 static void xi_pcmcia_power __P((int, void *)); 219 220 /* flags */ 221 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 222 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 223 #define XIFLAGS_MODEM 0x004 /* modem also present */ 224 225 const struct xi_pcmcia_product { 226 u_int32_t xpp_vendor; /* vendor ID */ 227 u_int32_t xpp_product; /* product ID */ 228 int xpp_expfunc; /* expected function number */ 229 int xpp_flags; /* initial softc flags */ 230 const char *xpp_name; /* device name */ 231 } xi_pcmcia_products[] = { 232 #ifdef NOT_SUPPORTED 233 { PCMCIA_VENDOR_XIRCOM, 0x0141, 234 0, 0, 235 PCMCIA_STR_XIRCOM_CE }, 236 #endif 237 { PCMCIA_VENDOR_XIRCOM, 0x0141, 238 0, 0, 239 PCMCIA_STR_XIRCOM_CE2 }, 240 { PCMCIA_VENDOR_XIRCOM, 0x0142, 241 0, 0, 242 PCMCIA_STR_XIRCOM_CE2 }, 243 { PCMCIA_VENDOR_XIRCOM, 0x0143, 244 0, XIFLAGS_MOHAWK, 245 PCMCIA_STR_XIRCOM_CE3 }, 246 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 247 0, XIFLAGS_MOHAWK, 248 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 249 { PCMCIA_VENDOR_INTEL, 0x0143, 250 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 251 PCMCIA_STR_INTEL_EEPRO100 }, 252 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_XE2000, 253 0, XIFLAGS_MOHAWK, 254 PCMCIA_STR_XIRCOM_XE2000 }, 255 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_REM56, 256 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 257 PCMCIA_STR_XIRCOM_REM56 }, 258 #ifdef NOT_SUPPORTED 259 { PCMCIA_VENDOR_XIRCOM, 0x1141, 260 0, XIFLAGS_MODEM, 261 PCMCIA_STR_XIRCOM_CEM }, 262 #endif 263 { PCMCIA_VENDOR_XIRCOM, 0x1142, 264 0, XIFLAGS_MODEM, 265 PCMCIA_STR_XIRCOM_CEM }, 266 { PCMCIA_VENDOR_XIRCOM, 0x1143, 267 0, XIFLAGS_MODEM, 268 PCMCIA_STR_XIRCOM_CEM }, 269 { PCMCIA_VENDOR_XIRCOM, 0x1144, 270 0, XIFLAGS_MODEM, 271 PCMCIA_STR_XIRCOM_CEM33 }, 272 { PCMCIA_VENDOR_XIRCOM, 0x1145, 273 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 274 PCMCIA_STR_XIRCOM_CEM56 }, 275 { PCMCIA_VENDOR_XIRCOM, 0x1146, 276 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 277 PCMCIA_STR_XIRCOM_REM56 }, 278 { PCMCIA_VENDOR_XIRCOM, 0x1147, 279 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 280 PCMCIA_STR_XIRCOM_REM56 }, 281 { 0, 0, 282 0, 0, 283 NULL }, 284 }; 285 286 287 const struct xi_pcmcia_product * 288 xi_pcmcia_identify(dev, pa) 289 struct device *dev; 290 struct pcmcia_attach_args *pa; 291 { 292 const struct xi_pcmcia_product *xpp; 293 u_int8_t id; 294 u_int32_t prod; 295 296 /* 297 * The Xircom ethernet cards swap the revision and product fields 298 * inside the CIS, which makes identification just a little 299 * bit different. 300 */ 301 302 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 303 304 prod = (pa->product & ~0xff) | id; 305 306 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 307 308 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 309 if (pa->manufacturer == xpp->xpp_vendor && 310 prod == xpp->xpp_product && 311 pa->pf->number == xpp->xpp_expfunc) 312 return (xpp); 313 return (NULL); 314 } 315 316 /* 317 * The quirks are done here instead of the traditional framework because 318 * of the difficulty in identifying the devices. 319 */ 320 static int 321 xi_pcmcia_cis_quirks(pf) 322 struct pcmcia_function *pf; 323 { 324 struct pcmcia_config_entry *cfe; 325 326 /* Tell the pcmcia framework where the CCR is. */ 327 pf->ccr_base = 0x800; 328 pf->ccr_mask = 0x67; 329 330 /* Fake a cfe. */ 331 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 332 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT); 333 334 if (cfe == NULL) 335 return -1; 336 memset(cfe, 0, sizeof(*cfe)); 337 338 /* 339 * XXX Use preprocessor symbols instead. 340 * Enable ethernet & its interrupts, wiring them to -INT 341 * No I/O base. 342 */ 343 cfe->number = 0x5; 344 cfe->flags = 0; /* XXX Check! */ 345 cfe->iftype = PCMCIA_IFTYPE_IO; 346 cfe->num_iospace = 0; 347 cfe->num_memspace = 0; 348 cfe->irqmask = 0x8eb0; 349 350 return 0; 351 } 352 353 int 354 xi_pcmcia_match(parent, match, aux) 355 struct device *parent; 356 struct cfdata *match; 357 void *aux; 358 { 359 struct pcmcia_attach_args *pa = aux; 360 361 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 362 pa->product == 0x110a) 363 return (2); /* prevent attach to com_pcmcia */ 364 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 365 return (0); 366 367 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 368 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 369 return (1); 370 371 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 372 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 373 return (1); 374 375 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 376 ((pa->product >> 8) == XIMEDIA_ETHER || 377 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 378 return (1); 379 380 return (0); 381 } 382 383 void 384 xi_pcmcia_attach(parent, self, aux) 385 struct device *parent, *self; 386 void *aux; 387 { 388 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 389 struct xi_softc *sc = &psc->sc_xi; 390 struct pcmcia_attach_args *pa = aux; 391 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 392 const struct xi_pcmcia_product *xpp; 393 394 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 395 printf(": function enable failed\n"); 396 return; 397 } 398 399 /* Enable the card */ 400 psc->sc_pf = pa->pf; 401 pcmcia_function_init(psc->sc_pf, psc->sc_pf->cfe_head.sqh_first); 402 if (pcmcia_function_enable(psc->sc_pf)) { 403 printf(": function enable failed\n"); 404 goto fail; 405 } 406 psc->sc_resource |= XI_RES_PCIC; 407 408 /* allocate/map ISA I/O space */ 409 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZE, XI_IOSIZE, 410 &psc->sc_pcioh) != 0) { 411 printf(": I/O allocation failed\n"); 412 goto fail; 413 } 414 psc->sc_resource |= XI_RES_IO_ALLOC; 415 416 sc->sc_bst = psc->sc_pcioh.iot; 417 sc->sc_bsh = psc->sc_pcioh.ioh; 418 sc->sc_offset = 0; 419 420 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_AUTO, 0, XI_IOSIZE, 421 &psc->sc_pcioh, &psc->sc_io_window)) { 422 printf(": can't map I/O space\n"); 423 goto fail; 424 } 425 psc->sc_resource |= XI_RES_IO_MAP; 426 427 xpp = xi_pcmcia_identify(parent,pa); 428 if (xpp == NULL) { 429 printf(": unrecognised model\n"); 430 return; 431 } 432 sc->sc_flags = xpp->xpp_flags; 433 434 printf(": %s\n", xpp->xpp_name); 435 436 /* 437 * Configuration as advised by DINGO documentation. 438 * Dingo has some extra configuration registers in the CCR space. 439 */ 440 if (sc->sc_flags & XIFLAGS_DINGO) { 441 struct pcmcia_mem_handle pcmh; 442 int ccr_window; 443 bus_addr_t ccr_offset; 444 445 /* get access to the DINGO CCR space */ 446 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 447 &pcmh)) { 448 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 449 goto fail; 450 } 451 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 452 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 453 &pcmh, &ccr_offset, &ccr_window)) { 454 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 455 pcmcia_mem_free(psc->sc_pf, &pcmh); 456 goto fail; 457 } 458 459 /* enable the second function - usually modem */ 460 bus_space_write_1(pcmh.memt, pcmh.memh, 461 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 462 bus_space_write_1(pcmh.memt, pcmh.memh, 463 ccr_offset + PCMCIA_CCR_DCOR1, 464 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 465 bus_space_write_1(pcmh.memt, pcmh.memh, 466 ccr_offset + PCMCIA_CCR_DCOR2, 0); 467 bus_space_write_1(pcmh.memt, pcmh.memh, 468 ccr_offset + PCMCIA_CCR_DCOR3, 0); 469 bus_space_write_1(pcmh.memt, pcmh.memh, 470 ccr_offset + PCMCIA_CCR_DCOR4, 0); 471 472 /* We don't need them anymore and can free them (I think). */ 473 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 474 pcmcia_mem_free(psc->sc_pf, &pcmh); 475 } 476 477 /* 478 * Get the ethernet address from FUNCE/LAN_NID tuple. 479 */ 480 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 481 if (!sc->sc_enaddr) { 482 printf("%s: unable to get ethernet address\n", 483 sc->sc_dev.dv_xname); 484 goto fail; 485 } 486 487 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 488 ether_sprintf(sc->sc_enaddr)); 489 490 ifp = &sc->sc_ethercom.ec_if; 491 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 492 ifp->if_softc = sc; 493 ifp->if_start = xi_start; 494 ifp->if_ioctl = xi_ioctl; 495 ifp->if_watchdog = xi_watchdog; 496 ifp->if_flags = 497 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 498 IFQ_SET_READY(&ifp->if_snd); 499 500 /* Reset and initialize the card. */ 501 xi_full_reset(sc); 502 503 /* 504 * Initialize our media structures and probe the MII. 505 */ 506 sc->sc_mii.mii_ifp = ifp; 507 sc->sc_mii.mii_readreg = xi_mdi_read; 508 sc->sc_mii.mii_writereg = xi_mdi_write; 509 sc->sc_mii.mii_statchg = xi_statchg; 510 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 511 xi_mediastatus); 512 DPRINTF(XID_MII | XID_CONFIG, 513 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 514 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 515 MII_OFFSET_ANY, 0); 516 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 517 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 518 NULL); 519 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 520 521 /* 802.1q capability */ 522 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 523 /* Attach the interface. */ 524 if_attach(ifp); 525 ether_ifattach(ifp, sc->sc_enaddr); 526 psc->sc_resource |= XI_RES_MI; 527 528 #if NRND > 0 529 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 530 RND_TYPE_NET, 0); 531 #endif 532 533 /* 534 * Reset and initialize the card again for DINGO (as found in Linux 535 * driver). Without this Dingo will get a watchdog timeout the first 536 * time. The ugly media tickling seems to be necessary for getting 537 * autonegotiation to work too. 538 */ 539 if (sc->sc_flags & XIFLAGS_DINGO) { 540 xi_full_reset(sc); 541 xi_init(sc); 542 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 543 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 544 xi_stop(sc); 545 } 546 547 psc->sc_powerhook = powerhook_establish(xi_pcmcia_power, sc); 548 549 pcmcia_function_disable(psc->sc_pf); 550 psc->sc_resource &= ~XI_RES_PCIC; 551 552 return; 553 554 fail: 555 if ((psc->sc_resource & XI_RES_IO_MAP) != 0) { 556 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 557 psc->sc_resource &= ~XI_RES_IO_MAP; 558 } 559 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 560 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 561 psc->sc_resource &= ~XI_RES_IO_ALLOC; 562 } 563 if (psc->sc_resource & XI_RES_PCIC) { 564 pcmcia_function_disable(pa->pf); 565 psc->sc_resource &= ~XI_RES_PCIC; 566 } 567 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 568 } 569 570 int 571 xi_pcmcia_detach(self, flags) 572 struct device *self; 573 int flags; 574 { 575 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 576 struct xi_softc *sc = &psc->sc_xi; 577 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 578 579 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 580 581 if (psc->sc_powerhook != NULL) 582 powerhook_disestablish(psc->sc_powerhook); 583 584 #if NRND > 0 585 rnd_detach_source(&sc->sc_rnd_source); 586 #endif 587 588 if ((psc->sc_resource & XI_RES_MI) != 0) { 589 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 590 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 591 ether_ifdetach(ifp); 592 if_detach(ifp); 593 psc->sc_resource &= ~XI_RES_MI; 594 } 595 if (psc->sc_resource & XI_RES_IO_MAP) { 596 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 597 psc->sc_resource &= ~XI_RES_IO_MAP; 598 } 599 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 600 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 601 psc->sc_resource &= ~XI_RES_IO_ALLOC; 602 } 603 604 xi_pcmcia_disable(psc); 605 606 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 607 608 return 0; 609 } 610 611 int 612 xi_pcmcia_activate(self, act) 613 struct device *self; 614 enum devact act; 615 { 616 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 617 struct xi_softc *sc = &psc->sc_xi; 618 int s, rv=0; 619 620 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 621 622 s = splnet(); 623 switch (act) { 624 case DVACT_ACTIVATE: 625 rv = EOPNOTSUPP; 626 break; 627 628 case DVACT_DEACTIVATE: 629 if_deactivate(&sc->sc_ethercom.ec_if); 630 break; 631 } 632 splx(s); 633 return (rv); 634 } 635 636 static int 637 xi_pcmcia_enable(psc) 638 struct xi_pcmcia_softc *psc; 639 { 640 struct xi_softc *sc = &psc->sc_xi; 641 642 DPRINTF(XID_CONFIG,("xi_pcmcia_enable()\n")); 643 644 if (pcmcia_function_enable(psc->sc_pf)) 645 return (1); 646 psc->sc_resource |= XI_RES_PCIC; 647 648 /* establish the interrupt. */ 649 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 650 if (psc->sc_ih == NULL) { 651 printf("%s: couldn't establish interrupt\n", 652 sc->sc_dev.dv_xname); 653 pcmcia_function_disable(psc->sc_pf); 654 psc->sc_resource &= ~XI_RES_PCIC; 655 return (1); 656 } 657 658 xi_full_reset(sc); 659 660 return (0); 661 } 662 663 664 static void 665 xi_pcmcia_disable(psc) 666 struct xi_pcmcia_softc *psc; 667 { 668 DPRINTF(XID_CONFIG,("xi_pcmcia_disable()\n")); 669 670 if (psc->sc_resource & XI_RES_PCIC) { 671 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 672 pcmcia_function_disable(psc->sc_pf); 673 psc->sc_resource &= ~XI_RES_PCIC; 674 } 675 } 676 677 678 static void 679 xi_pcmcia_power(why, arg) 680 int why; 681 void *arg; 682 { 683 struct xi_pcmcia_softc *psc = arg; 684 struct xi_softc *sc = &psc->sc_xi; 685 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 686 int s; 687 688 DPRINTF(XID_CONFIG,("xi_pcmcia_power()\n")); 689 690 s = splnet(); 691 692 switch (why) { 693 case PWR_SUSPEND: 694 case PWR_STANDBY: 695 if (ifp->if_flags & IFF_RUNNING) { 696 xi_stop(sc); 697 } 698 ifp->if_flags &= ~IFF_RUNNING; 699 ifp->if_timer = 0; 700 break; 701 case PWR_RESUME: 702 if ((ifp->if_flags & IFF_RUNNING) == 0) { 703 xi_init(sc); 704 } 705 ifp->if_flags |= IFF_RUNNING; 706 break; 707 case PWR_SOFTSUSPEND: 708 case PWR_SOFTSTANDBY: 709 case PWR_SOFTRESUME: 710 break; 711 } 712 splx(s); 713 } 714 715 /* 716 * XXX These two functions might be OK to factor out into pcmcia.c since 717 * if_sm_pcmcia.c uses similar ones. 718 */ 719 static int 720 xi_pcmcia_funce_enaddr(parent, myla) 721 struct device *parent; 722 u_int8_t *myla; 723 { 724 /* XXX The Linux driver has more ways to do this in case of failure. */ 725 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 726 } 727 728 static int 729 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 730 struct pcmcia_tuple *tuple; 731 void *arg; 732 { 733 u_int8_t *myla = arg; 734 int i; 735 736 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 737 738 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 739 if (tuple->length < 2) 740 return (0); 741 742 switch (pcmcia_tuple_read_1(tuple, 0)) { 743 case PCMCIA_TPLFE_TYPE_LAN_NID: 744 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 745 return (0); 746 break; 747 748 case 0x02: 749 /* 750 * Not sure about this, I don't have a CE2 751 * that puts the ethernet addr here. 752 */ 753 if (pcmcia_tuple_read_1(tuple, 1) != 13) 754 return (0); 755 break; 756 757 default: 758 return (0); 759 } 760 761 for (i = 0; i < ETHER_ADDR_LEN; i++) 762 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 763 return (1); 764 } 765 766 /* Yet another spot where this might be. */ 767 if (tuple->code == 0x89) { 768 pcmcia_tuple_read_1(tuple, 1); 769 for (i = 0; i < ETHER_ADDR_LEN; i++) 770 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 771 return (1); 772 } 773 return (0); 774 } 775 776 int 777 xi_pcmcia_manfid_ciscallback(tuple, arg) 778 struct pcmcia_tuple *tuple; 779 void *arg; 780 { 781 u_int8_t *id = arg; 782 783 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 784 785 if (tuple->code != PCMCIA_CISTPL_MANFID) 786 return (0); 787 788 if (tuple->length < 2) 789 return (0); 790 791 *id = pcmcia_tuple_read_1(tuple, 4); 792 return (1); 793 } 794 795 static int 796 xi_intr(arg) 797 void *arg; 798 { 799 struct xi_softc *sc = arg; 800 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 801 u_int8_t esr, rsr, isr, rx_status, savedpage; 802 u_int16_t tx_status, recvcount = 0, tempint; 803 804 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 805 806 #if 0 807 if (!(ifp->if_flags & IFF_RUNNING)) 808 return (0); 809 #endif 810 811 ifp->if_timer = 0; /* turn watchdog timer off */ 812 813 if (sc->sc_flags & XIFLAGS_MOHAWK) { 814 /* Disable interrupt (Linux does it). */ 815 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 816 0); 817 } 818 819 savedpage = 820 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 821 822 PAGE(sc, 0); 823 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 824 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 825 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 826 827 /* Check to see if card has been ejected. */ 828 if (isr == 0xff) { 829 #ifdef DIAGNOSTIC 830 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 831 #endif 832 goto end; 833 } 834 835 PAGE(sc, 40); 836 rx_status = 837 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 838 tx_status = 839 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 840 841 /* 842 * XXX Linux writes to RXST0 and TXST* here. My CE2 works just fine 843 * without it, and I can't see an obvious reason for it. 844 */ 845 846 PAGE(sc, 0); 847 while (esr & FULL_PKT_RCV) { 848 if (!(rsr & RSR_RX_OK)) 849 break; 850 851 /* Compare bytes read this interrupt to hard maximum. */ 852 if (recvcount > MAX_BYTES_INTR) { 853 DPRINTF(XID_INTR, 854 ("xi: too many bytes this interrupt\n")); 855 ifp->if_iqdrops++; 856 /* Drop packet. */ 857 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 858 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 859 } 860 tempint = xi_get(sc); /* XXX doesn't check the error! */ 861 recvcount += tempint; 862 ifp->if_ibytes += tempint; 863 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 864 sc->sc_offset + ESR); 865 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 866 sc->sc_offset + RSR); 867 } 868 869 /* Packet too long? */ 870 if (rsr & RSR_TOO_LONG) { 871 ifp->if_ierrors++; 872 DPRINTF(XID_INTR, ("xi: packet too long\n")); 873 } 874 875 /* CRC error? */ 876 if (rsr & RSR_CRCERR) { 877 ifp->if_ierrors++; 878 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 879 } 880 881 /* Alignment error? */ 882 if (rsr & RSR_ALIGNERR) { 883 ifp->if_ierrors++; 884 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 885 } 886 887 /* Check for rx overrun. */ 888 if (rx_status & RX_OVERRUN) { 889 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 890 CLR_RX_OVERRUN); 891 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 892 } 893 894 /* Try to start more packets transmitting. */ 895 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 896 xi_start(ifp); 897 898 /* Detected excessive collisions? */ 899 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 900 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 901 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 902 RESTART_TX); 903 ifp->if_oerrors++; 904 } 905 906 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 907 ifp->if_oerrors++; 908 909 end: 910 /* Reenable interrupts. */ 911 PAGE(sc, savedpage); 912 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 913 ENABLE_INT); 914 915 /* have handled the interrupt */ 916 #if NRND > 0 917 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 918 #endif 919 920 return (1); 921 } 922 923 /* 924 * Pull a packet from the card into an mbuf chain. 925 */ 926 static u_int16_t 927 xi_get(sc) 928 struct xi_softc *sc; 929 { 930 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 931 struct mbuf *top, **mp, *m; 932 u_int16_t pktlen, len, recvcount = 0; 933 u_int8_t *data; 934 u_int8_t rsr; 935 936 DPRINTF(XID_CONFIG, ("xi_get()\n")); 937 938 PAGE(sc, 0); 939 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 940 941 pktlen = 942 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 943 RBC_COUNT_MASK; 944 945 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 946 947 if (pktlen == 0) { 948 /* 949 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 950 * when MPE is set. It is not known why. 951 */ 952 return (0); 953 } 954 955 /* XXX should this be incremented now ? */ 956 recvcount += pktlen; 957 958 MGETHDR(m, M_DONTWAIT, MT_DATA); 959 if (m == 0) 960 return (recvcount); 961 m->m_pkthdr.rcvif = ifp; 962 m->m_pkthdr.len = pktlen; 963 m->m_flags |= M_HASFCS; 964 len = MHLEN; 965 top = 0; 966 mp = ⊤ 967 968 while (pktlen > 0) { 969 if (top) { 970 MGET(m, M_DONTWAIT, MT_DATA); 971 if (m == 0) { 972 m_freem(top); 973 return (recvcount); 974 } 975 len = MLEN; 976 } 977 if (pktlen >= MINCLSIZE) { 978 MCLGET(m, M_DONTWAIT); 979 if (!(m->m_flags & M_EXT)) { 980 m_freem(m); 981 m_freem(top); 982 return (recvcount); 983 } 984 len = MCLBYTES; 985 } 986 if (!top) { 987 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 988 sizeof(struct ether_header)) - 989 sizeof(struct ether_header); 990 len -= newdata - m->m_data; 991 m->m_data = newdata; 992 } 993 len = min(pktlen, len); 994 data = mtod(m, u_int8_t *); 995 if (len > 1) { 996 len &= ~1; 997 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 998 sc->sc_offset + EDP, data, len>>1); 999 } else 1000 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 1001 sc->sc_offset + EDP); 1002 m->m_len = len; 1003 pktlen -= len; 1004 *mp = m; 1005 mp = &m->m_next; 1006 } 1007 1008 /* Skip Rx packet. */ 1009 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 1010 DO_SKIP_RX_PKT); 1011 1012 ifp->if_ipackets++; 1013 1014 #if NBPFILTER > 0 1015 if (ifp->if_bpf) 1016 bpf_mtap(ifp->if_bpf, top); 1017 #endif 1018 1019 (*ifp->if_input)(ifp, top); 1020 return (recvcount); 1021 } 1022 1023 /* 1024 * Serial management for the MII. 1025 * The DELAY's below stem from the fact that the maximum frequency 1026 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 1027 * go much faster than that. 1028 */ 1029 1030 /* Let the MII serial management be idle for one period. */ 1031 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 1032 static INLINE void 1033 xi_mdi_idle(sc) 1034 struct xi_softc *sc; 1035 { 1036 bus_space_tag_t bst = sc->sc_bst; 1037 bus_space_handle_t bsh = sc->sc_bsh; 1038 bus_addr_t offset = sc->sc_offset; 1039 1040 /* Drive MDC low... */ 1041 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1042 DELAY(1); 1043 1044 /* and high again. */ 1045 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1046 DELAY(1); 1047 } 1048 1049 /* Pulse out one bit of data. */ 1050 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 1051 static INLINE void 1052 xi_mdi_pulse(sc, data) 1053 struct xi_softc *sc; 1054 int data; 1055 { 1056 bus_space_tag_t bst = sc->sc_bst; 1057 bus_space_handle_t bsh = sc->sc_bsh; 1058 bus_addr_t offset = sc->sc_offset; 1059 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 1060 1061 /* First latch the data bit MDIO with clock bit MDC low...*/ 1062 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 1063 DELAY(1); 1064 1065 /* then raise the clock again, preserving the data bit. */ 1066 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 1067 DELAY(1); 1068 } 1069 1070 /* Probe one bit of data. */ 1071 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 1072 static INLINE int 1073 xi_mdi_probe(sc) 1074 struct xi_softc *sc; 1075 { 1076 bus_space_tag_t bst = sc->sc_bst; 1077 bus_space_handle_t bsh = sc->sc_bsh; 1078 bus_addr_t offset = sc->sc_offset; 1079 u_int8_t x; 1080 1081 /* Pull clock bit MDCK low... */ 1082 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1083 DELAY(1); 1084 1085 /* Read data and drive clock high again. */ 1086 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 1087 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1088 DELAY(1); 1089 1090 return (x); 1091 } 1092 1093 /* Pulse out a sequence of data bits. */ 1094 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 1095 static INLINE void 1096 xi_mdi_pulse_bits(sc, data, len) 1097 struct xi_softc *sc; 1098 u_int32_t data; 1099 int len; 1100 { 1101 u_int32_t mask; 1102 1103 for (mask = 1 << (len - 1); mask; mask >>= 1) 1104 xi_mdi_pulse(sc, data & mask); 1105 } 1106 1107 /* Read a PHY register. */ 1108 static int 1109 xi_mdi_read(self, phy, reg) 1110 struct device *self; 1111 int phy; 1112 int reg; 1113 { 1114 struct xi_softc *sc = (struct xi_softc *)self; 1115 int i; 1116 u_int32_t mask; 1117 u_int32_t data = 0; 1118 1119 PAGE(sc, 2); 1120 for (i = 0; i < 32; i++) /* Synchronize. */ 1121 xi_mdi_pulse(sc, 1); 1122 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1123 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1124 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1125 xi_mdi_idle(sc); /* Turn around. */ 1126 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1127 1128 for (mask = 1 << 15; mask; mask >>= 1) { 1129 if (xi_mdi_probe(sc)) 1130 data |= mask; 1131 } 1132 xi_mdi_idle(sc); 1133 1134 DPRINTF(XID_MII, 1135 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1136 1137 return (data); 1138 } 1139 1140 /* Write a PHY register. */ 1141 static void 1142 xi_mdi_write(self, phy, reg, value) 1143 struct device *self; 1144 int phy; 1145 int reg; 1146 int value; 1147 { 1148 struct xi_softc *sc = (struct xi_softc *)self; 1149 int i; 1150 1151 PAGE(sc, 2); 1152 for (i = 0; i < 32; i++) /* Synchronize. */ 1153 xi_mdi_pulse(sc, 1); 1154 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1155 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1156 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1157 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1158 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1159 xi_mdi_idle(sc); /* Idle away. */ 1160 1161 DPRINTF(XID_MII, 1162 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1163 } 1164 1165 static void 1166 xi_statchg(self) 1167 struct device *self; 1168 { 1169 /* XXX Update ifp->if_baudrate */ 1170 } 1171 1172 /* 1173 * Change media according to request. 1174 */ 1175 static int 1176 xi_mediachange(ifp) 1177 struct ifnet *ifp; 1178 { 1179 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1180 1181 if (ifp->if_flags & IFF_UP) 1182 xi_init(ifp->if_softc); 1183 return (0); 1184 } 1185 1186 /* 1187 * Notify the world which media we're using. 1188 */ 1189 static void 1190 xi_mediastatus(ifp, ifmr) 1191 struct ifnet *ifp; 1192 struct ifmediareq *ifmr; 1193 { 1194 struct xi_softc *sc = ifp->if_softc; 1195 1196 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1197 1198 mii_pollstat(&sc->sc_mii); 1199 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1200 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1201 } 1202 1203 static void 1204 xi_reset(sc) 1205 struct xi_softc *sc; 1206 { 1207 int s; 1208 1209 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1210 1211 s = splnet(); 1212 xi_stop(sc); 1213 xi_full_reset(sc); 1214 xi_init(sc); 1215 splx(s); 1216 } 1217 1218 static void 1219 xi_watchdog(ifp) 1220 struct ifnet *ifp; 1221 { 1222 struct xi_softc *sc = ifp->if_softc; 1223 1224 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1225 ++ifp->if_oerrors; 1226 1227 xi_reset(sc); 1228 } 1229 1230 static void 1231 xi_stop(sc) 1232 register struct xi_softc *sc; 1233 { 1234 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1235 1236 /* Disable interrupts. */ 1237 PAGE(sc, 0); 1238 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1239 1240 PAGE(sc, 1); 1241 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1242 1243 /* Power down, wait. */ 1244 PAGE(sc, 4); 1245 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1246 DELAY(40000); 1247 1248 /* Cancel watchdog timer. */ 1249 sc->sc_ethercom.ec_if.if_timer = 0; 1250 } 1251 1252 static void 1253 xi_init(sc) 1254 struct xi_softc *sc; 1255 { 1256 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)sc; 1257 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1258 int s; 1259 1260 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1261 1262 if ((psc->sc_resource & XI_RES_PCIC) == 0) 1263 xi_pcmcia_enable(psc); 1264 1265 s = splnet(); 1266 1267 xi_set_address(sc); 1268 1269 /* Set current media. */ 1270 mii_mediachg(&sc->sc_mii); 1271 1272 ifp->if_flags |= IFF_RUNNING; 1273 ifp->if_flags &= ~IFF_OACTIVE; 1274 splx(s); 1275 } 1276 1277 /* 1278 * Start outputting on the interface. 1279 * Always called as splnet(). 1280 */ 1281 static void 1282 xi_start(ifp) 1283 struct ifnet *ifp; 1284 { 1285 struct xi_softc *sc = ifp->if_softc; 1286 bus_space_tag_t bst = sc->sc_bst; 1287 bus_space_handle_t bsh = sc->sc_bsh; 1288 bus_addr_t offset = sc->sc_offset; 1289 unsigned int s, len, pad = 0; 1290 struct mbuf *m0, *m; 1291 u_int16_t space; 1292 1293 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1294 1295 /* Don't transmit if interface is busy or not running. */ 1296 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1297 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1298 return; 1299 } 1300 1301 /* Peek at the next packet. */ 1302 IFQ_POLL(&ifp->if_snd, m0); 1303 if (m0 == 0) 1304 return; 1305 1306 /* We need to use m->m_pkthdr.len, so require the header. */ 1307 if (!(m0->m_flags & M_PKTHDR)) 1308 panic("xi_start: no header mbuf"); 1309 1310 len = m0->m_pkthdr.len; 1311 1312 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1313 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1314 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1315 1316 PAGE(sc, 0); 1317 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1318 if (len + pad + 2 > space) { 1319 DPRINTF(XID_FIFO, 1320 ("xi: not enough space in output FIFO (%d > %d)\n", 1321 len + pad + 2, space)); 1322 return; 1323 } 1324 1325 IFQ_DEQUEUE(&ifp->if_snd, m0); 1326 1327 #if NBPFILTER > 0 1328 if (ifp->if_bpf) 1329 bpf_mtap(ifp->if_bpf, m0); 1330 #endif 1331 1332 /* 1333 * Do the output at splhigh() so that an interrupt from another device 1334 * won't cause a FIFO underrun. 1335 */ 1336 s = splhigh(); 1337 1338 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1339 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1340 for (m = m0; m; ) { 1341 if (m->m_len > 1) 1342 bus_space_write_multi_2(bst, bsh, offset + EDP, 1343 mtod(m, u_int8_t *), m->m_len>>1); 1344 if (m->m_len & 1) 1345 bus_space_write_1(bst, bsh, offset + EDP, 1346 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1347 MFREE(m, m0); 1348 m = m0; 1349 } 1350 if (sc->sc_flags & XIFLAGS_MOHAWK) 1351 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1352 else { 1353 for (; pad > 1; pad -= 2) 1354 bus_space_write_2(bst, bsh, offset + EDP, 0); 1355 if (pad == 1) 1356 bus_space_write_1(bst, bsh, offset + EDP, 0); 1357 } 1358 1359 splx(s); 1360 1361 ifp->if_timer = 5; 1362 ++ifp->if_opackets; 1363 } 1364 1365 static int 1366 xi_ether_ioctl(ifp, cmd, data) 1367 struct ifnet *ifp; 1368 u_long cmd; 1369 caddr_t data; 1370 { 1371 struct ifaddr *ifa = (struct ifaddr *)data; 1372 struct xi_softc *sc = ifp->if_softc; 1373 1374 1375 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1376 1377 switch (cmd) { 1378 case SIOCSIFADDR: 1379 ifp->if_flags |= IFF_UP; 1380 1381 switch (ifa->ifa_addr->sa_family) { 1382 #ifdef INET 1383 case AF_INET: 1384 xi_init(sc); 1385 arp_ifinit(ifp, ifa); 1386 break; 1387 #endif /* INET */ 1388 1389 #ifdef NS 1390 case AF_NS: 1391 { 1392 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1393 1394 if (ns_nullhost(*ina)) 1395 ina->x_host = *(union ns_host *) 1396 LLADDR(ifp->if_sadl); 1397 else 1398 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1399 ifp->if_addrlen); 1400 /* Set new address. */ 1401 xi_init(sc); 1402 break; 1403 } 1404 #endif /* NS */ 1405 1406 default: 1407 xi_init(sc); 1408 break; 1409 } 1410 break; 1411 1412 default: 1413 return (EINVAL); 1414 } 1415 1416 return (0); 1417 } 1418 1419 static int 1420 xi_ioctl(ifp, command, data) 1421 struct ifnet *ifp; 1422 u_long command; 1423 caddr_t data; 1424 { 1425 struct xi_pcmcia_softc *psc = ifp->if_softc; 1426 struct xi_softc *sc = &psc->sc_xi; 1427 struct ifreq *ifr = (struct ifreq *)data; 1428 int s, error = 0; 1429 1430 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1431 1432 s = splnet(); 1433 1434 switch (command) { 1435 case SIOCSIFADDR: 1436 error = xi_ether_ioctl(ifp, command, data); 1437 break; 1438 1439 case SIOCSIFFLAGS: 1440 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1441 1442 PAGE(sc, 0x42); 1443 if ((ifp->if_flags & IFF_PROMISC) || 1444 (ifp->if_flags & IFF_ALLMULTI)) 1445 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1446 sc->sc_offset + SWC1, 1447 SWC1_PROMISC | SWC1_MCAST_PROM); 1448 else 1449 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1450 sc->sc_offset + SWC1, 0); 1451 1452 /* 1453 * If interface is marked up and not running, then start it. 1454 * If it is marked down and running, stop it. 1455 * XXX If it's up then re-initialize it. This is so flags 1456 * such as IFF_PROMISC are handled. 1457 */ 1458 if (ifp->if_flags & IFF_UP) { 1459 xi_init(sc); 1460 } else { 1461 if (ifp->if_flags & IFF_RUNNING) { 1462 xi_pcmcia_disable(psc); 1463 xi_stop(sc); 1464 ifp->if_flags &= ~IFF_RUNNING; 1465 } 1466 } 1467 break; 1468 1469 case SIOCADDMULTI: 1470 case SIOCDELMULTI: 1471 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1472 error = (command == SIOCADDMULTI) ? 1473 ether_addmulti(ifr, &sc->sc_ethercom) : 1474 ether_delmulti(ifr, &sc->sc_ethercom); 1475 1476 if (error == ENETRESET) { 1477 /* 1478 * Multicast list has changed; set the hardware 1479 * filter accordingly. 1480 */ 1481 if (!sc->sc_all_mcasts && 1482 !(ifp->if_flags & IFF_PROMISC)) 1483 xi_set_address(sc); 1484 1485 /* 1486 * xi_set_address() can turn on all_mcasts if we run 1487 * out of space, so check it again rather than else {}. 1488 */ 1489 if (sc->sc_all_mcasts) 1490 xi_init(sc); 1491 error = 0; 1492 } 1493 break; 1494 1495 case SIOCSIFMEDIA: 1496 case SIOCGIFMEDIA: 1497 error = 1498 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1499 break; 1500 1501 default: 1502 error = EINVAL; 1503 } 1504 splx(s); 1505 return (error); 1506 } 1507 1508 static void 1509 xi_set_address(sc) 1510 struct xi_softc *sc; 1511 { 1512 bus_space_tag_t bst = sc->sc_bst; 1513 bus_space_handle_t bsh = sc->sc_bsh; 1514 bus_addr_t offset = sc->sc_offset; 1515 struct ethercom *ether = &sc->sc_ethercom; 1516 #if 0 1517 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1518 #endif 1519 #if WORKING_MULTICAST 1520 struct ether_multistep step; 1521 struct ether_multi *enm; 1522 int page, pos, num; 1523 #endif 1524 int i; 1525 1526 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1527 1528 PAGE(sc, 0x50); 1529 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1530 bus_space_write_1(bst, bsh, offset + IA + i, 1531 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1532 } 1533 1534 if (ether->ec_multicnt > 0) { 1535 #ifdef WORKING_MULTICAST 1536 if (ether->ec_multicnt > 9) { 1537 #else 1538 { 1539 #endif 1540 PAGE(sc, 0x42); 1541 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1542 sc->sc_offset + SWC1, 1543 SWC1_PROMISC | SWC1_MCAST_PROM); 1544 return; 1545 } 1546 1547 #ifdef WORKING_MULTICAST 1548 1549 ETHER_FIRST_MULTI(step, ether, enm); 1550 1551 pos = IA + 6; 1552 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1553 num--) { 1554 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1555 sizeof(enm->enm_addrlo)) != 0) { 1556 /* 1557 * The multicast address is really a range; 1558 * it's easier just to accept all multicasts. 1559 * XXX should we be setting IFF_ALLMULTI here? 1560 */ 1561 #if 0 1562 ifp->if_flags |= IFF_ALLMULTI; 1563 #endif 1564 sc->sc_all_mcasts=1; 1565 break; 1566 } 1567 1568 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1569 printf("%x:", enm->enm_addrlo[i]); 1570 bus_space_write_1(bst, bsh, offset + pos, 1571 enm->enm_addrlo[ 1572 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1573 1574 if (++pos > 15) { 1575 pos = IA; 1576 page++; 1577 PAGE(sc, page); 1578 } 1579 } 1580 printf("\n"); 1581 ETHER_NEXT_MULTI(step, enm); 1582 } 1583 #endif 1584 } 1585 } 1586 1587 static void 1588 xi_cycle_power(sc) 1589 struct xi_softc *sc; 1590 { 1591 bus_space_tag_t bst = sc->sc_bst; 1592 bus_space_handle_t bsh = sc->sc_bsh; 1593 bus_addr_t offset = sc->sc_offset; 1594 1595 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1596 1597 PAGE(sc, 4); 1598 DELAY(1); 1599 bus_space_write_1(bst, bsh, offset + GP1, 0); 1600 DELAY(40000); 1601 if (sc->sc_flags & XIFLAGS_MOHAWK) 1602 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1603 else 1604 /* XXX What is bit 2 (aka AIC)? */ 1605 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1606 DELAY(20000); 1607 } 1608 1609 static void 1610 xi_full_reset(sc) 1611 struct xi_softc *sc; 1612 { 1613 bus_space_tag_t bst = sc->sc_bst; 1614 bus_space_handle_t bsh = sc->sc_bsh; 1615 bus_addr_t offset = sc->sc_offset; 1616 1617 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1618 1619 /* Do an as extensive reset as possible on all functions. */ 1620 xi_cycle_power(sc); 1621 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1622 DELAY(20000); 1623 bus_space_write_1(bst, bsh, offset + CR, 0); 1624 DELAY(20000); 1625 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1626 PAGE(sc, 4); 1627 /* 1628 * Drive GP1 low to power up ML6692 and GP2 high to power up 1629 * the 10Mhz chip. XXX What chip is that? The phy? 1630 */ 1631 bus_space_write_1(bst, bsh, offset + GP0, 1632 GP1_OUT | GP2_OUT | GP2_WR); 1633 } 1634 DELAY(500000); 1635 1636 /* Get revision information. XXX Symbolic constants. */ 1637 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1638 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1639 1640 /* Media selection. XXX Maybe manual overriding too? */ 1641 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1642 PAGE(sc, 4); 1643 /* 1644 * XXX I have no idea what this really does, it is from the 1645 * Linux driver. 1646 */ 1647 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1648 } 1649 DELAY(40000); 1650 1651 /* Setup the ethernet interrupt mask. */ 1652 PAGE(sc, 1); 1653 #if 1 1654 bus_space_write_1(bst, bsh, offset + IMR0, 1655 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1656 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1657 #else 1658 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1659 #endif 1660 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1661 /* XXX What is this? Not for Dingo at least. */ 1662 /* Unmask TX underrun detection */ 1663 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1664 } 1665 1666 /* 1667 * Disable source insertion. 1668 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1669 */ 1670 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1671 PAGE(sc, 0x42); 1672 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1673 } 1674 1675 /* Set the local memory dividing line. */ 1676 if (sc->sc_rev != 1) { 1677 PAGE(sc, 2); 1678 /* XXX Symbolic constant preferrable. */ 1679 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1680 } 1681 1682 xi_set_address(sc); 1683 1684 /* 1685 * Apparently the receive byte pointer can be bad after a reset, so 1686 * we hardwire it correctly. 1687 */ 1688 PAGE(sc, 0); 1689 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1690 1691 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1692 PAGE(sc, 0x40); 1693 bus_space_write_1(bst, bsh, offset + RX0MSK, 1694 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1695 bus_space_write_1(bst, bsh, offset + TX0MSK, 1696 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1697 SQE | TX_ABORT | TX_OK); 1698 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1699 /* XXX From Linux, dunno what 0xb0 means. */ 1700 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1701 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1702 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1703 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1704 1705 /* Enable MII function if available. */ 1706 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1707 PAGE(sc, 2); 1708 bus_space_write_1(bst, bsh, offset + MSR, 1709 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1710 DELAY(20000); 1711 } else { 1712 PAGE(sc, 0); 1713 1714 /* XXX Do we need to do this? */ 1715 PAGE(sc, 0x42); 1716 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1717 DELAY(50000); 1718 1719 /* XXX Linux probes the media here. */ 1720 } 1721 1722 /* Configure the LED registers. */ 1723 PAGE(sc, 2); 1724 1725 /* XXX This is not good for 10base2. */ 1726 bus_space_write_1(bst, bsh, offset + LED, 1727 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1728 if (sc->sc_flags & XIFLAGS_DINGO) 1729 bus_space_write_1(bst, bsh, offset + LED3, 1730 LED_100MB_LINK << LED3_SHIFT); 1731 1732 /* Enable receiver and go online. */ 1733 PAGE(sc, 0x40); 1734 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1735 1736 #if 0 1737 /* XXX Linux does this here - is it necessary? */ 1738 PAGE(sc, 1); 1739 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1740 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1741 /* XXX What is this? Not for Dingo at least. */ 1742 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1743 } 1744 #endif 1745 1746 /* Enable interrupts. */ 1747 PAGE(sc, 0); 1748 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1749 1750 /* XXX This is pure magic for me, found in the Linux driver. */ 1751 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1752 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1753 /* Unmask the master interrupt bit. */ 1754 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1755 } 1756 1757 /* 1758 * The Linux driver says this: 1759 * We should switch back to page 0 to avoid a bug in revision 0 1760 * where regs with offset below 8 can't be read after an access 1761 * to the MAC registers. 1762 */ 1763 PAGE(sc, 0); 1764 } 1765