1 /* $NetBSD: if_xi.c,v 1.30 2003/02/27 07:50:57 martin Exp $ */ 2 /* OpenBSD: if_xe.c,v 1.9 1999/09/16 11:28:42 niklas Exp */ 3 4 /* 5 * XXX THIS DRIVER IS BROKEN WRT. MULTICAST LISTS AND PROMISC/ALLMULTI 6 * XXX FLAGS! 7 */ 8 9 /* 10 * Copyright (c) 1999 Niklas Hallqvist, Brandon Creighton, Job de Haas 11 * All rights reserved. 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Niklas Hallqvist, 24 * Brandon Creighton and Job de Haas. 25 * 4. The name of the author may not be used to endorse or promote products 26 * derived from this software without specific prior written permission 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * A driver for Xircom CreditCard PCMCIA Ethernet adapters. 42 */ 43 44 /* 45 * Known Bugs: 46 * 47 * 1) Promiscuous mode doesn't work on at least the CE2. 48 * 2) Slow. ~450KB/s. Memory access would be better. 49 */ 50 51 #include <sys/cdefs.h> 52 __KERNEL_RCSID(0, "$NetBSD: if_xi.c,v 1.30 2003/02/27 07:50:57 martin Exp $"); 53 54 #include "opt_inet.h" 55 #include "bpfilter.h" 56 57 #include <sys/param.h> 58 #include <sys/systm.h> 59 #include <sys/device.h> 60 #include <sys/ioctl.h> 61 #include <sys/mbuf.h> 62 #include <sys/malloc.h> 63 #include <sys/socket.h> 64 65 #include "rnd.h" 66 #if NRND > 0 67 #include <sys/rnd.h> 68 #endif 69 70 #include <net/if.h> 71 #include <net/if_dl.h> 72 #include <net/if_media.h> 73 #include <net/if_types.h> 74 #include <net/if_ether.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/in_systm.h> 79 #include <netinet/in_var.h> 80 #include <netinet/ip.h> 81 #include <netinet/if_inarp.h> 82 #endif 83 84 #ifdef IPX 85 #include <netipx/ipx.h> 86 #include <netipx/ipx_if.h> 87 #endif 88 89 #ifdef NS 90 #include <netns/ns.h> 91 #include <netns/ns_if.h> 92 #endif 93 94 #if NBPFILTER > 0 95 #include <net/bpf.h> 96 #include <net/bpfdesc.h> 97 #endif 98 99 /* 100 * Maximum number of bytes to read per interrupt. Linux recommends 101 * somewhere between 2000-22000. 102 * XXX This is currently a hard maximum. 103 */ 104 #define MAX_BYTES_INTR 12000 105 106 #include <dev/mii/mii.h> 107 #include <dev/mii/miivar.h> 108 109 #include <dev/pcmcia/pcmciareg.h> 110 #include <dev/pcmcia/pcmciavar.h> 111 #include <dev/pcmcia/pcmciadevs.h> 112 113 #include <dev/pcmcia/if_xireg.h> 114 115 #ifdef __GNUC__ 116 #define INLINE __inline 117 #else 118 #define INLINE 119 #endif /* __GNUC__ */ 120 121 #ifdef XIDEBUG 122 #define DPRINTF(cat, x) if (xidebug & (cat)) printf x 123 124 #define XID_CONFIG 0x1 125 #define XID_MII 0x2 126 #define XID_INTR 0x4 127 #define XID_FIFO 0x8 128 129 #ifdef XIDEBUG_VALUE 130 int xidebug = XIDEBUG_VALUE; 131 #else 132 int xidebug = 0; 133 #endif 134 #else 135 #define DPRINTF(cat, x) (void)0 136 #endif 137 138 int xi_pcmcia_match __P((struct device *, struct cfdata *, void *)); 139 void xi_pcmcia_attach __P((struct device *, struct device *, void *)); 140 int xi_pcmcia_detach __P((struct device *, int)); 141 int xi_pcmcia_activate __P((struct device *, enum devact)); 142 143 /* 144 * In case this chipset ever turns up out of pcmcia attachments (very 145 * unlikely) do the driver splitup. 146 */ 147 struct xi_softc { 148 struct device sc_dev; /* Generic device info */ 149 struct ethercom sc_ethercom; /* Ethernet common part */ 150 151 struct mii_data sc_mii; /* MII media information */ 152 153 bus_space_tag_t sc_bst; /* Bus cookie */ 154 bus_space_handle_t sc_bsh; /* Bus I/O handle */ 155 bus_size_t sc_offset; /* Offset of registers */ 156 157 u_int8_t sc_rev; /* Chip revision */ 158 u_int32_t sc_flags; /* Misc. flags */ 159 int sc_all_mcasts; /* Receive all multicasts */ 160 u_int8_t sc_enaddr[ETHER_ADDR_LEN]; 161 #if NRND > 0 162 rndsource_element_t sc_rnd_source; 163 #endif 164 }; 165 166 struct xi_pcmcia_softc { 167 struct xi_softc sc_xi; /* Generic device info */ 168 169 /* PCMCIA-specific goo */ 170 struct pcmcia_function *sc_pf; /* PCMCIA function */ 171 struct pcmcia_io_handle sc_pcioh; /* iospace info */ 172 int sc_io_window; /* io window info */ 173 void *sc_ih; /* Interrupt handler */ 174 void *sc_powerhook; /* power hook descriptor */ 175 int sc_resource; /* resource allocated */ 176 #define XI_RES_PCIC 1 177 #define XI_RES_IO_ALLOC 2 178 #define XI_RES_IO_MAP 4 179 #define XI_RES_MI 8 180 }; 181 182 CFATTACH_DECL(xi_pcmcia, sizeof(struct xi_pcmcia_softc), 183 xi_pcmcia_match, xi_pcmcia_attach, xi_pcmcia_detach, xi_pcmcia_activate); 184 185 static int xi_pcmcia_cis_quirks __P((struct pcmcia_function *)); 186 static void xi_cycle_power __P((struct xi_softc *)); 187 static int xi_ether_ioctl __P((struct ifnet *, u_long cmd, caddr_t)); 188 static void xi_full_reset __P((struct xi_softc *)); 189 static void xi_init __P((struct xi_softc *)); 190 static int xi_intr __P((void *)); 191 static int xi_ioctl __P((struct ifnet *, u_long, caddr_t)); 192 static int xi_mdi_read __P((struct device *, int, int)); 193 static void xi_mdi_write __P((struct device *, int, int, int)); 194 static int xi_mediachange __P((struct ifnet *)); 195 static void xi_mediastatus __P((struct ifnet *, struct ifmediareq *)); 196 static int xi_pcmcia_funce_enaddr __P((struct device *, u_int8_t *)); 197 static int xi_pcmcia_lan_nid_ciscallback __P((struct pcmcia_tuple *, void *)); 198 static int xi_pcmcia_manfid_ciscallback __P((struct pcmcia_tuple *, void *)); 199 static u_int16_t xi_get __P((struct xi_softc *)); 200 static void xi_reset __P((struct xi_softc *)); 201 static void xi_set_address __P((struct xi_softc *)); 202 static void xi_start __P((struct ifnet *)); 203 static void xi_statchg __P((struct device *)); 204 static void xi_stop __P((struct xi_softc *)); 205 static void xi_watchdog __P((struct ifnet *)); 206 const struct xi_pcmcia_product *xi_pcmcia_identify __P((struct device *, 207 struct pcmcia_attach_args *)); 208 static int xi_pcmcia_enable __P((struct xi_pcmcia_softc *)); 209 static void xi_pcmcia_disable __P((struct xi_pcmcia_softc *)); 210 static void xi_pcmcia_power __P((int, void *)); 211 212 /* flags */ 213 #define XIFLAGS_MOHAWK 0x001 /* 100Mb capabilities (has phy) */ 214 #define XIFLAGS_DINGO 0x002 /* realport cards ??? */ 215 #define XIFLAGS_MODEM 0x004 /* modem also present */ 216 217 const struct xi_pcmcia_product { 218 u_int32_t xpp_vendor; /* vendor ID */ 219 u_int32_t xpp_product; /* product ID */ 220 int xpp_expfunc; /* expected function number */ 221 int xpp_flags; /* initial softc flags */ 222 const char *xpp_name; /* device name */ 223 } xi_pcmcia_products[] = { 224 #ifdef NOT_SUPPORTED 225 { PCMCIA_VENDOR_XIRCOM, 0x0141, 226 0, 0, 227 PCMCIA_STR_XIRCOM_CE }, 228 #endif 229 { PCMCIA_VENDOR_XIRCOM, 0x0141, 230 0, 0, 231 PCMCIA_STR_XIRCOM_CE2 }, 232 { PCMCIA_VENDOR_XIRCOM, 0x0142, 233 0, 0, 234 PCMCIA_STR_XIRCOM_CE2 }, 235 { PCMCIA_VENDOR_XIRCOM, 0x0143, 236 0, XIFLAGS_MOHAWK, 237 PCMCIA_STR_XIRCOM_CE3 }, 238 { PCMCIA_VENDOR_COMPAQ2, 0x0143, 239 0, XIFLAGS_MOHAWK, 240 PCMCIA_STR_COMPAQ2_CPQ_10_100 }, 241 { PCMCIA_VENDOR_INTEL, 0x0143, 242 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 243 PCMCIA_STR_INTEL_EEPRO100 }, 244 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_XE2000, 245 0, XIFLAGS_MOHAWK, 246 PCMCIA_STR_XIRCOM_XE2000 }, 247 { PCMCIA_VENDOR_XIRCOM, PCMCIA_PRODUCT_XIRCOM_REM56, 248 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 249 PCMCIA_STR_XIRCOM_REM56 }, 250 #ifdef NOT_SUPPORTED 251 { PCMCIA_VENDOR_XIRCOM, 0x1141, 252 0, XIFLAGS_MODEM, 253 PCMCIA_STR_XIRCOM_CEM }, 254 #endif 255 { PCMCIA_VENDOR_XIRCOM, 0x1142, 256 0, XIFLAGS_MODEM, 257 PCMCIA_STR_XIRCOM_CEM }, 258 { PCMCIA_VENDOR_XIRCOM, 0x1143, 259 0, XIFLAGS_MODEM, 260 PCMCIA_STR_XIRCOM_CEM }, 261 { PCMCIA_VENDOR_XIRCOM, 0x1144, 262 0, XIFLAGS_MODEM, 263 PCMCIA_STR_XIRCOM_CEM33 }, 264 { PCMCIA_VENDOR_XIRCOM, 0x1145, 265 0, XIFLAGS_MOHAWK | XIFLAGS_MODEM, 266 PCMCIA_STR_XIRCOM_CEM56 }, 267 { PCMCIA_VENDOR_XIRCOM, 0x1146, 268 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 269 PCMCIA_STR_XIRCOM_REM56 }, 270 { PCMCIA_VENDOR_XIRCOM, 0x1147, 271 0, XIFLAGS_MOHAWK | XIFLAGS_DINGO | XIFLAGS_MODEM, 272 PCMCIA_STR_XIRCOM_REM56 }, 273 { 0, 0, 274 0, 0, 275 NULL }, 276 }; 277 278 279 const struct xi_pcmcia_product * 280 xi_pcmcia_identify(dev, pa) 281 struct device *dev; 282 struct pcmcia_attach_args *pa; 283 { 284 const struct xi_pcmcia_product *xpp; 285 u_int8_t id; 286 u_int32_t prod; 287 288 /* 289 * The Xircom ethernet cards swap the revision and product fields 290 * inside the CIS, which makes identification just a little 291 * bit different. 292 */ 293 294 pcmcia_scan_cis(dev, xi_pcmcia_manfid_ciscallback, &id); 295 296 prod = (pa->product & ~0xff) | id; 297 298 DPRINTF(XID_CONFIG, ("product=0x%x\n", prod)); 299 300 for (xpp = xi_pcmcia_products; xpp->xpp_name != NULL; xpp++) 301 if (pa->manufacturer == xpp->xpp_vendor && 302 prod == xpp->xpp_product && 303 pa->pf->number == xpp->xpp_expfunc) 304 return (xpp); 305 return (NULL); 306 } 307 308 /* 309 * The quirks are done here instead of the traditional framework because 310 * of the difficulty in identifying the devices. 311 */ 312 static int 313 xi_pcmcia_cis_quirks(pf) 314 struct pcmcia_function *pf; 315 { 316 struct pcmcia_config_entry *cfe; 317 318 /* Tell the pcmcia framework where the CCR is. */ 319 pf->ccr_base = 0x800; 320 pf->ccr_mask = 0x67; 321 322 /* Fake a cfe. */ 323 SIMPLEQ_FIRST(&pf->cfe_head) = cfe = (struct pcmcia_config_entry *) 324 malloc(sizeof(*cfe), M_DEVBUF, M_NOWAIT|M_ZERO); 325 326 if (cfe == NULL) 327 return -1; 328 329 /* 330 * XXX Use preprocessor symbols instead. 331 * Enable ethernet & its interrupts, wiring them to -INT 332 * No I/O base. 333 */ 334 cfe->number = 0x5; 335 cfe->flags = 0; /* XXX Check! */ 336 cfe->iftype = PCMCIA_IFTYPE_IO; 337 cfe->num_iospace = 0; 338 cfe->num_memspace = 0; 339 cfe->irqmask = 0x8eb0; 340 341 return 0; 342 } 343 344 int 345 xi_pcmcia_match(parent, match, aux) 346 struct device *parent; 347 struct cfdata *match; 348 void *aux; 349 { 350 struct pcmcia_attach_args *pa = aux; 351 352 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 353 pa->product == 0x110a) 354 return (2); /* prevent attach to com_pcmcia */ 355 if (pa->pf->function != PCMCIA_FUNCTION_NETWORK) 356 return (0); 357 358 if (pa->manufacturer == PCMCIA_VENDOR_COMPAQ2 && 359 pa->product == PCMCIA_PRODUCT_COMPAQ2_CPQ_10_100) 360 return (1); 361 362 if (pa->manufacturer == PCMCIA_VENDOR_INTEL && 363 pa->product == PCMCIA_PRODUCT_INTEL_EEPRO100) 364 return (1); 365 366 if (pa->manufacturer == PCMCIA_VENDOR_XIRCOM && 367 ((pa->product >> 8) == XIMEDIA_ETHER || 368 (pa->product >> 8) == (XIMEDIA_ETHER | XIMEDIA_MODEM))) 369 return (1); 370 371 return (0); 372 } 373 374 void 375 xi_pcmcia_attach(parent, self, aux) 376 struct device *parent, *self; 377 void *aux; 378 { 379 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 380 struct xi_softc *sc = &psc->sc_xi; 381 struct pcmcia_attach_args *pa = aux; 382 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 383 const struct xi_pcmcia_product *xpp; 384 385 if (xi_pcmcia_cis_quirks(pa->pf) < 0) { 386 printf(": function enable failed\n"); 387 return; 388 } 389 390 /* Enable the card */ 391 psc->sc_pf = pa->pf; 392 pcmcia_function_init(psc->sc_pf, SIMPLEQ_FIRST(&psc->sc_pf->cfe_head)); 393 if (pcmcia_function_enable(psc->sc_pf)) { 394 printf(": function enable failed\n"); 395 goto fail; 396 } 397 psc->sc_resource |= XI_RES_PCIC; 398 399 /* allocate/map ISA I/O space */ 400 if (pcmcia_io_alloc(psc->sc_pf, 0, XI_IOSIZE, XI_IOSIZE, 401 &psc->sc_pcioh) != 0) { 402 printf(": I/O allocation failed\n"); 403 goto fail; 404 } 405 psc->sc_resource |= XI_RES_IO_ALLOC; 406 407 sc->sc_bst = psc->sc_pcioh.iot; 408 sc->sc_bsh = psc->sc_pcioh.ioh; 409 sc->sc_offset = 0; 410 411 if (pcmcia_io_map(psc->sc_pf, PCMCIA_WIDTH_AUTO, 0, XI_IOSIZE, 412 &psc->sc_pcioh, &psc->sc_io_window)) { 413 printf(": can't map I/O space\n"); 414 goto fail; 415 } 416 psc->sc_resource |= XI_RES_IO_MAP; 417 418 xpp = xi_pcmcia_identify(parent,pa); 419 if (xpp == NULL) { 420 printf(": unrecognised model\n"); 421 return; 422 } 423 sc->sc_flags = xpp->xpp_flags; 424 425 printf(": %s\n", xpp->xpp_name); 426 427 /* 428 * Configuration as advised by DINGO documentation. 429 * Dingo has some extra configuration registers in the CCR space. 430 */ 431 if (sc->sc_flags & XIFLAGS_DINGO) { 432 struct pcmcia_mem_handle pcmh; 433 int ccr_window; 434 bus_size_t ccr_offset; 435 436 /* get access to the DINGO CCR space */ 437 if (pcmcia_mem_alloc(psc->sc_pf, PCMCIA_CCR_SIZE_DINGO, 438 &pcmh)) { 439 DPRINTF(XID_CONFIG, ("xi: bad mem alloc\n")); 440 goto fail; 441 } 442 if (pcmcia_mem_map(psc->sc_pf, PCMCIA_MEM_ATTR, 443 psc->sc_pf->ccr_base, PCMCIA_CCR_SIZE_DINGO, 444 &pcmh, &ccr_offset, &ccr_window)) { 445 DPRINTF(XID_CONFIG, ("xi: bad mem map\n")); 446 pcmcia_mem_free(psc->sc_pf, &pcmh); 447 goto fail; 448 } 449 450 /* enable the second function - usually modem */ 451 bus_space_write_1(pcmh.memt, pcmh.memh, 452 ccr_offset + PCMCIA_CCR_DCOR0, PCMCIA_CCR_DCOR0_SFINT); 453 bus_space_write_1(pcmh.memt, pcmh.memh, 454 ccr_offset + PCMCIA_CCR_DCOR1, 455 PCMCIA_CCR_DCOR1_FORCE_LEVIREQ | PCMCIA_CCR_DCOR1_D6); 456 bus_space_write_1(pcmh.memt, pcmh.memh, 457 ccr_offset + PCMCIA_CCR_DCOR2, 0); 458 bus_space_write_1(pcmh.memt, pcmh.memh, 459 ccr_offset + PCMCIA_CCR_DCOR3, 0); 460 bus_space_write_1(pcmh.memt, pcmh.memh, 461 ccr_offset + PCMCIA_CCR_DCOR4, 0); 462 463 /* We don't need them anymore and can free them (I think). */ 464 pcmcia_mem_unmap(psc->sc_pf, ccr_window); 465 pcmcia_mem_free(psc->sc_pf, &pcmh); 466 } 467 468 /* 469 * Get the ethernet address from FUNCE/LAN_NID tuple. 470 */ 471 xi_pcmcia_funce_enaddr(parent, sc->sc_enaddr); 472 if (!sc->sc_enaddr) { 473 printf("%s: unable to get ethernet address\n", 474 sc->sc_dev.dv_xname); 475 goto fail; 476 } 477 478 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 479 ether_sprintf(sc->sc_enaddr)); 480 481 ifp = &sc->sc_ethercom.ec_if; 482 memcpy(ifp->if_xname, sc->sc_dev.dv_xname, IFNAMSIZ); 483 ifp->if_softc = sc; 484 ifp->if_start = xi_start; 485 ifp->if_ioctl = xi_ioctl; 486 ifp->if_watchdog = xi_watchdog; 487 ifp->if_flags = 488 IFF_BROADCAST | IFF_NOTRAILERS | IFF_SIMPLEX | IFF_MULTICAST; 489 IFQ_SET_READY(&ifp->if_snd); 490 491 /* Reset and initialize the card. */ 492 xi_full_reset(sc); 493 494 /* 495 * Initialize our media structures and probe the MII. 496 */ 497 sc->sc_mii.mii_ifp = ifp; 498 sc->sc_mii.mii_readreg = xi_mdi_read; 499 sc->sc_mii.mii_writereg = xi_mdi_write; 500 sc->sc_mii.mii_statchg = xi_statchg; 501 ifmedia_init(&sc->sc_mii.mii_media, 0, xi_mediachange, 502 xi_mediastatus); 503 DPRINTF(XID_MII | XID_CONFIG, 504 ("xi: bmsr %x\n", xi_mdi_read(&sc->sc_dev, 0, 1))); 505 mii_attach(self, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 506 MII_OFFSET_ANY, 0); 507 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) 508 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO, 0, 509 NULL); 510 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 511 512 /* 802.1q capability */ 513 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 514 /* Attach the interface. */ 515 if_attach(ifp); 516 ether_ifattach(ifp, sc->sc_enaddr); 517 psc->sc_resource |= XI_RES_MI; 518 519 #if NRND > 0 520 rnd_attach_source(&sc->sc_rnd_source, sc->sc_dev.dv_xname, 521 RND_TYPE_NET, 0); 522 #endif 523 524 /* 525 * Reset and initialize the card again for DINGO (as found in Linux 526 * driver). Without this Dingo will get a watchdog timeout the first 527 * time. The ugly media tickling seems to be necessary for getting 528 * autonegotiation to work too. 529 */ 530 if (sc->sc_flags & XIFLAGS_DINGO) { 531 xi_full_reset(sc); 532 xi_init(sc); 533 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_AUTO); 534 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER | IFM_NONE); 535 xi_stop(sc); 536 } 537 538 psc->sc_powerhook = powerhook_establish(xi_pcmcia_power, sc); 539 540 pcmcia_function_disable(psc->sc_pf); 541 psc->sc_resource &= ~XI_RES_PCIC; 542 543 return; 544 545 fail: 546 if ((psc->sc_resource & XI_RES_IO_MAP) != 0) { 547 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 548 psc->sc_resource &= ~XI_RES_IO_MAP; 549 } 550 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 551 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 552 psc->sc_resource &= ~XI_RES_IO_ALLOC; 553 } 554 if (psc->sc_resource & XI_RES_PCIC) { 555 pcmcia_function_disable(pa->pf); 556 psc->sc_resource &= ~XI_RES_PCIC; 557 } 558 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 559 } 560 561 int 562 xi_pcmcia_detach(self, flags) 563 struct device *self; 564 int flags; 565 { 566 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 567 struct xi_softc *sc = &psc->sc_xi; 568 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 569 570 DPRINTF(XID_CONFIG, ("xi_pcmcia_detach()\n")); 571 572 if (psc->sc_powerhook != NULL) 573 powerhook_disestablish(psc->sc_powerhook); 574 575 #if NRND > 0 576 rnd_detach_source(&sc->sc_rnd_source); 577 #endif 578 579 if ((psc->sc_resource & XI_RES_MI) != 0) { 580 mii_detach(&sc->sc_mii, MII_PHY_ANY, MII_OFFSET_ANY); 581 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 582 ether_ifdetach(ifp); 583 if_detach(ifp); 584 psc->sc_resource &= ~XI_RES_MI; 585 } 586 if (psc->sc_resource & XI_RES_IO_MAP) { 587 pcmcia_io_unmap(psc->sc_pf, psc->sc_io_window); 588 psc->sc_resource &= ~XI_RES_IO_MAP; 589 } 590 if ((psc->sc_resource & XI_RES_IO_ALLOC) != 0) { 591 pcmcia_io_free(psc->sc_pf, &psc->sc_pcioh); 592 psc->sc_resource &= ~XI_RES_IO_ALLOC; 593 } 594 595 xi_pcmcia_disable(psc); 596 597 free(SIMPLEQ_FIRST(&psc->sc_pf->cfe_head), M_DEVBUF); 598 599 return 0; 600 } 601 602 int 603 xi_pcmcia_activate(self, act) 604 struct device *self; 605 enum devact act; 606 { 607 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)self; 608 struct xi_softc *sc = &psc->sc_xi; 609 int s, rv=0; 610 611 DPRINTF(XID_CONFIG, ("xi_pcmcia_activate()\n")); 612 613 s = splnet(); 614 switch (act) { 615 case DVACT_ACTIVATE: 616 rv = EOPNOTSUPP; 617 break; 618 619 case DVACT_DEACTIVATE: 620 if_deactivate(&sc->sc_ethercom.ec_if); 621 break; 622 } 623 splx(s); 624 return (rv); 625 } 626 627 static int 628 xi_pcmcia_enable(psc) 629 struct xi_pcmcia_softc *psc; 630 { 631 struct xi_softc *sc = &psc->sc_xi; 632 633 DPRINTF(XID_CONFIG,("xi_pcmcia_enable()\n")); 634 635 if (pcmcia_function_enable(psc->sc_pf)) 636 return (1); 637 psc->sc_resource |= XI_RES_PCIC; 638 639 /* establish the interrupt. */ 640 psc->sc_ih = pcmcia_intr_establish(psc->sc_pf, IPL_NET, xi_intr, sc); 641 if (psc->sc_ih == NULL) { 642 printf("%s: couldn't establish interrupt\n", 643 sc->sc_dev.dv_xname); 644 pcmcia_function_disable(psc->sc_pf); 645 psc->sc_resource &= ~XI_RES_PCIC; 646 return (1); 647 } 648 649 xi_full_reset(sc); 650 651 return (0); 652 } 653 654 655 static void 656 xi_pcmcia_disable(psc) 657 struct xi_pcmcia_softc *psc; 658 { 659 DPRINTF(XID_CONFIG,("xi_pcmcia_disable()\n")); 660 661 if (psc->sc_resource & XI_RES_PCIC) { 662 pcmcia_intr_disestablish(psc->sc_pf, psc->sc_ih); 663 pcmcia_function_disable(psc->sc_pf); 664 psc->sc_resource &= ~XI_RES_PCIC; 665 } 666 } 667 668 669 static void 670 xi_pcmcia_power(why, arg) 671 int why; 672 void *arg; 673 { 674 struct xi_pcmcia_softc *psc = arg; 675 struct xi_softc *sc = &psc->sc_xi; 676 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 677 int s; 678 679 DPRINTF(XID_CONFIG,("xi_pcmcia_power()\n")); 680 681 s = splnet(); 682 683 switch (why) { 684 case PWR_SUSPEND: 685 case PWR_STANDBY: 686 if (ifp->if_flags & IFF_RUNNING) { 687 xi_stop(sc); 688 } 689 ifp->if_flags &= ~IFF_RUNNING; 690 ifp->if_timer = 0; 691 break; 692 case PWR_RESUME: 693 if ((ifp->if_flags & IFF_RUNNING) == 0) { 694 xi_init(sc); 695 } 696 ifp->if_flags |= IFF_RUNNING; 697 break; 698 case PWR_SOFTSUSPEND: 699 case PWR_SOFTSTANDBY: 700 case PWR_SOFTRESUME: 701 break; 702 } 703 splx(s); 704 } 705 706 /* 707 * XXX These two functions might be OK to factor out into pcmcia.c since 708 * if_sm_pcmcia.c uses similar ones. 709 */ 710 static int 711 xi_pcmcia_funce_enaddr(parent, myla) 712 struct device *parent; 713 u_int8_t *myla; 714 { 715 /* XXX The Linux driver has more ways to do this in case of failure. */ 716 return (pcmcia_scan_cis(parent, xi_pcmcia_lan_nid_ciscallback, myla)); 717 } 718 719 static int 720 xi_pcmcia_lan_nid_ciscallback(tuple, arg) 721 struct pcmcia_tuple *tuple; 722 void *arg; 723 { 724 u_int8_t *myla = arg; 725 int i; 726 727 DPRINTF(XID_CONFIG, ("xi_pcmcia_lan_nid_ciscallback()\n")); 728 729 if (tuple->code == PCMCIA_CISTPL_FUNCE) { 730 if (tuple->length < 2) 731 return (0); 732 733 switch (pcmcia_tuple_read_1(tuple, 0)) { 734 case PCMCIA_TPLFE_TYPE_LAN_NID: 735 if (pcmcia_tuple_read_1(tuple, 1) != ETHER_ADDR_LEN) 736 return (0); 737 break; 738 739 case 0x02: 740 /* 741 * Not sure about this, I don't have a CE2 742 * that puts the ethernet addr here. 743 */ 744 if (pcmcia_tuple_read_1(tuple, 1) != 13) 745 return (0); 746 break; 747 748 default: 749 return (0); 750 } 751 752 for (i = 0; i < ETHER_ADDR_LEN; i++) 753 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 754 return (1); 755 } 756 757 /* Yet another spot where this might be. */ 758 if (tuple->code == 0x89) { 759 pcmcia_tuple_read_1(tuple, 1); 760 for (i = 0; i < ETHER_ADDR_LEN; i++) 761 myla[i] = pcmcia_tuple_read_1(tuple, i + 2); 762 return (1); 763 } 764 return (0); 765 } 766 767 int 768 xi_pcmcia_manfid_ciscallback(tuple, arg) 769 struct pcmcia_tuple *tuple; 770 void *arg; 771 { 772 u_int8_t *id = arg; 773 774 DPRINTF(XID_CONFIG, ("xi_pcmcia_manfid_callback()\n")); 775 776 if (tuple->code != PCMCIA_CISTPL_MANFID) 777 return (0); 778 779 if (tuple->length < 2) 780 return (0); 781 782 *id = pcmcia_tuple_read_1(tuple, 4); 783 return (1); 784 } 785 786 static int 787 xi_intr(arg) 788 void *arg; 789 { 790 struct xi_softc *sc = arg; 791 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 792 u_int8_t esr, rsr, isr, rx_status, savedpage; 793 u_int16_t tx_status, recvcount = 0, tempint; 794 795 DPRINTF(XID_CONFIG, ("xi_intr()\n")); 796 797 #if 0 798 if (!(ifp->if_flags & IFF_RUNNING)) 799 return (0); 800 #endif 801 802 ifp->if_timer = 0; /* turn watchdog timer off */ 803 804 if (sc->sc_flags & XIFLAGS_MOHAWK) { 805 /* Disable interrupt (Linux does it). */ 806 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 807 0); 808 } 809 810 savedpage = 811 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + PR); 812 813 PAGE(sc, 0); 814 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ESR); 815 isr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + ISR0); 816 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 817 818 /* Check to see if card has been ejected. */ 819 if (isr == 0xff) { 820 #ifdef DIAGNOSTIC 821 printf("%s: interrupt for dead card\n", sc->sc_dev.dv_xname); 822 #endif 823 goto end; 824 } 825 826 PAGE(sc, 40); 827 rx_status = 828 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0); 829 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RXST0, 830 ~rx_status & 0xff); 831 tx_status = 832 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0); 833 tx_status |= 834 bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1) << 8; 835 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST0,0); 836 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + TXST1,0); 837 838 PAGE(sc, 0); 839 while (esr & FULL_PKT_RCV) { 840 if (!(rsr & RSR_RX_OK)) 841 break; 842 843 /* Compare bytes read this interrupt to hard maximum. */ 844 if (recvcount > MAX_BYTES_INTR) { 845 DPRINTF(XID_INTR, 846 ("xi: too many bytes this interrupt\n")); 847 ifp->if_iqdrops++; 848 /* Drop packet. */ 849 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 850 sc->sc_offset + DO0, DO_SKIP_RX_PKT); 851 } 852 tempint = xi_get(sc); /* XXX doesn't check the error! */ 853 recvcount += tempint; 854 ifp->if_ibytes += tempint; 855 esr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 856 sc->sc_offset + ESR); 857 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 858 sc->sc_offset + RSR); 859 } 860 861 /* Packet too long? */ 862 if (rsr & RSR_TOO_LONG) { 863 ifp->if_ierrors++; 864 DPRINTF(XID_INTR, ("xi: packet too long\n")); 865 } 866 867 /* CRC error? */ 868 if (rsr & RSR_CRCERR) { 869 ifp->if_ierrors++; 870 DPRINTF(XID_INTR, ("xi: CRC error detected\n")); 871 } 872 873 /* Alignment error? */ 874 if (rsr & RSR_ALIGNERR) { 875 ifp->if_ierrors++; 876 DPRINTF(XID_INTR, ("xi: alignment error detected\n")); 877 } 878 879 /* Check for rx overrun. */ 880 if (rx_status & RX_OVERRUN) { 881 ifp->if_ierrors++; 882 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 883 CLR_RX_OVERRUN); 884 DPRINTF(XID_INTR, ("xi: overrun cleared\n")); 885 } 886 887 /* Try to start more packets transmitting. */ 888 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 889 xi_start(ifp); 890 891 /* Detected excessive collisions? */ 892 if ((tx_status & EXCESSIVE_COLL) && ifp->if_opackets > 0) { 893 DPRINTF(XID_INTR, ("xi: excessive collisions\n")); 894 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 895 RESTART_TX); 896 ifp->if_oerrors++; 897 } 898 899 if ((tx_status & TX_ABORT) && ifp->if_opackets > 0) 900 ifp->if_oerrors++; 901 902 end: 903 /* Reenable interrupts. */ 904 PAGE(sc, savedpage); 905 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 906 ENABLE_INT); 907 908 /* have handled the interrupt */ 909 #if NRND > 0 910 rnd_add_uint32(&sc->sc_rnd_source, tx_status); 911 #endif 912 913 return (1); 914 } 915 916 /* 917 * Pull a packet from the card into an mbuf chain. 918 */ 919 static u_int16_t 920 xi_get(sc) 921 struct xi_softc *sc; 922 { 923 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 924 struct mbuf *top, **mp, *m; 925 u_int16_t pktlen, len, recvcount = 0; 926 u_int8_t *data; 927 u_int8_t rsr; 928 929 DPRINTF(XID_CONFIG, ("xi_get()\n")); 930 931 PAGE(sc, 0); 932 rsr = bus_space_read_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RSR); 933 934 pktlen = 935 bus_space_read_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + RBC0) & 936 RBC_COUNT_MASK; 937 938 DPRINTF(XID_CONFIG, ("xi_get: pktlen=%d\n", pktlen)); 939 940 if (pktlen == 0) { 941 /* 942 * XXX At least one CE2 sets RBC0 == 0 occasionally, and only 943 * when MPE is set. It is not known why. 944 */ 945 return (0); 946 } 947 948 /* XXX should this be incremented now ? */ 949 recvcount += pktlen; 950 951 MGETHDR(m, M_DONTWAIT, MT_DATA); 952 if (m == 0) 953 return (recvcount); 954 m->m_pkthdr.rcvif = ifp; 955 m->m_pkthdr.len = pktlen; 956 m->m_flags |= M_HASFCS; 957 len = MHLEN; 958 top = 0; 959 mp = ⊤ 960 961 while (pktlen > 0) { 962 if (top) { 963 MGET(m, M_DONTWAIT, MT_DATA); 964 if (m == 0) { 965 m_freem(top); 966 return (recvcount); 967 } 968 len = MLEN; 969 } 970 if (pktlen >= MINCLSIZE) { 971 MCLGET(m, M_DONTWAIT); 972 if (!(m->m_flags & M_EXT)) { 973 m_freem(m); 974 m_freem(top); 975 return (recvcount); 976 } 977 len = MCLBYTES; 978 } 979 if (!top) { 980 caddr_t newdata = (caddr_t)ALIGN(m->m_data + 981 sizeof(struct ether_header)) - 982 sizeof(struct ether_header); 983 len -= newdata - m->m_data; 984 m->m_data = newdata; 985 } 986 len = min(pktlen, len); 987 data = mtod(m, u_int8_t *); 988 if (len > 1) { 989 len &= ~1; 990 bus_space_read_multi_2(sc->sc_bst, sc->sc_bsh, 991 sc->sc_offset + EDP, (u_int16_t *)data, len>>1); 992 } else 993 *data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 994 sc->sc_offset + EDP); 995 m->m_len = len; 996 pktlen -= len; 997 *mp = m; 998 mp = &m->m_next; 999 } 1000 1001 /* Skip Rx packet. */ 1002 bus_space_write_2(sc->sc_bst, sc->sc_bsh, sc->sc_offset + DO0, 1003 DO_SKIP_RX_PKT); 1004 1005 ifp->if_ipackets++; 1006 1007 #if NBPFILTER > 0 1008 if (ifp->if_bpf) 1009 bpf_mtap(ifp->if_bpf, top); 1010 #endif 1011 1012 (*ifp->if_input)(ifp, top); 1013 return (recvcount); 1014 } 1015 1016 /* 1017 * Serial management for the MII. 1018 * The DELAY's below stem from the fact that the maximum frequency 1019 * acceptable on the MDC pin is 2.5 MHz and fast processors can easily 1020 * go much faster than that. 1021 */ 1022 1023 /* Let the MII serial management be idle for one period. */ 1024 static INLINE void xi_mdi_idle __P((struct xi_softc *)); 1025 static INLINE void 1026 xi_mdi_idle(sc) 1027 struct xi_softc *sc; 1028 { 1029 bus_space_tag_t bst = sc->sc_bst; 1030 bus_space_handle_t bsh = sc->sc_bsh; 1031 bus_size_t offset = sc->sc_offset; 1032 1033 /* Drive MDC low... */ 1034 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1035 DELAY(1); 1036 1037 /* and high again. */ 1038 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1039 DELAY(1); 1040 } 1041 1042 /* Pulse out one bit of data. */ 1043 static INLINE void xi_mdi_pulse __P((struct xi_softc *, int)); 1044 static INLINE void 1045 xi_mdi_pulse(sc, data) 1046 struct xi_softc *sc; 1047 int data; 1048 { 1049 bus_space_tag_t bst = sc->sc_bst; 1050 bus_space_handle_t bsh = sc->sc_bsh; 1051 bus_size_t offset = sc->sc_offset; 1052 u_int8_t bit = data ? MDIO_HIGH : MDIO_LOW; 1053 1054 /* First latch the data bit MDIO with clock bit MDC low...*/ 1055 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_LOW); 1056 DELAY(1); 1057 1058 /* then raise the clock again, preserving the data bit. */ 1059 bus_space_write_1(bst, bsh, offset + GP2, bit | MDC_HIGH); 1060 DELAY(1); 1061 } 1062 1063 /* Probe one bit of data. */ 1064 static INLINE int xi_mdi_probe __P((struct xi_softc *sc)); 1065 static INLINE int 1066 xi_mdi_probe(sc) 1067 struct xi_softc *sc; 1068 { 1069 bus_space_tag_t bst = sc->sc_bst; 1070 bus_space_handle_t bsh = sc->sc_bsh; 1071 bus_size_t offset = sc->sc_offset; 1072 u_int8_t x; 1073 1074 /* Pull clock bit MDCK low... */ 1075 bus_space_write_1(bst, bsh, offset + GP2, MDC_LOW); 1076 DELAY(1); 1077 1078 /* Read data and drive clock high again. */ 1079 x = bus_space_read_1(bst, bsh, offset + GP2) & MDIO; 1080 bus_space_write_1(bst, bsh, offset + GP2, MDC_HIGH); 1081 DELAY(1); 1082 1083 return (x); 1084 } 1085 1086 /* Pulse out a sequence of data bits. */ 1087 static INLINE void xi_mdi_pulse_bits __P((struct xi_softc *, u_int32_t, int)); 1088 static INLINE void 1089 xi_mdi_pulse_bits(sc, data, len) 1090 struct xi_softc *sc; 1091 u_int32_t data; 1092 int len; 1093 { 1094 u_int32_t mask; 1095 1096 for (mask = 1 << (len - 1); mask; mask >>= 1) 1097 xi_mdi_pulse(sc, data & mask); 1098 } 1099 1100 /* Read a PHY register. */ 1101 static int 1102 xi_mdi_read(self, phy, reg) 1103 struct device *self; 1104 int phy; 1105 int reg; 1106 { 1107 struct xi_softc *sc = (struct xi_softc *)self; 1108 int i; 1109 u_int32_t mask; 1110 u_int32_t data = 0; 1111 1112 PAGE(sc, 2); 1113 for (i = 0; i < 32; i++) /* Synchronize. */ 1114 xi_mdi_pulse(sc, 1); 1115 xi_mdi_pulse_bits(sc, 0x06, 4); /* Start + Read opcode */ 1116 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1117 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1118 xi_mdi_idle(sc); /* Turn around. */ 1119 xi_mdi_probe(sc); /* Drop initial zero bit. */ 1120 1121 for (mask = 1 << 15; mask; mask >>= 1) { 1122 if (xi_mdi_probe(sc)) 1123 data |= mask; 1124 } 1125 xi_mdi_idle(sc); 1126 1127 DPRINTF(XID_MII, 1128 ("xi_mdi_read: phy %d reg %d -> %x\n", phy, reg, data)); 1129 1130 return (data); 1131 } 1132 1133 /* Write a PHY register. */ 1134 static void 1135 xi_mdi_write(self, phy, reg, value) 1136 struct device *self; 1137 int phy; 1138 int reg; 1139 int value; 1140 { 1141 struct xi_softc *sc = (struct xi_softc *)self; 1142 int i; 1143 1144 PAGE(sc, 2); 1145 for (i = 0; i < 32; i++) /* Synchronize. */ 1146 xi_mdi_pulse(sc, 1); 1147 xi_mdi_pulse_bits(sc, 0x05, 4); /* Start + Write opcode */ 1148 xi_mdi_pulse_bits(sc, phy, 5); /* PHY address */ 1149 xi_mdi_pulse_bits(sc, reg, 5); /* PHY register */ 1150 xi_mdi_pulse_bits(sc, 0x02, 2); /* Turn around. */ 1151 xi_mdi_pulse_bits(sc, value, 16); /* Write the data */ 1152 xi_mdi_idle(sc); /* Idle away. */ 1153 1154 DPRINTF(XID_MII, 1155 ("xi_mdi_write: phy %d reg %d val %x\n", phy, reg, value)); 1156 } 1157 1158 static void 1159 xi_statchg(self) 1160 struct device *self; 1161 { 1162 /* XXX Update ifp->if_baudrate */ 1163 } 1164 1165 /* 1166 * Change media according to request. 1167 */ 1168 static int 1169 xi_mediachange(ifp) 1170 struct ifnet *ifp; 1171 { 1172 DPRINTF(XID_CONFIG, ("xi_mediachange()\n")); 1173 1174 if (ifp->if_flags & IFF_UP) 1175 xi_init(ifp->if_softc); 1176 return (0); 1177 } 1178 1179 /* 1180 * Notify the world which media we're using. 1181 */ 1182 static void 1183 xi_mediastatus(ifp, ifmr) 1184 struct ifnet *ifp; 1185 struct ifmediareq *ifmr; 1186 { 1187 struct xi_softc *sc = ifp->if_softc; 1188 1189 DPRINTF(XID_CONFIG, ("xi_mediastatus()\n")); 1190 1191 mii_pollstat(&sc->sc_mii); 1192 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1193 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1194 } 1195 1196 static void 1197 xi_reset(sc) 1198 struct xi_softc *sc; 1199 { 1200 int s; 1201 1202 DPRINTF(XID_CONFIG, ("xi_reset()\n")); 1203 1204 s = splnet(); 1205 xi_stop(sc); 1206 xi_full_reset(sc); 1207 xi_init(sc); 1208 splx(s); 1209 } 1210 1211 static void 1212 xi_watchdog(ifp) 1213 struct ifnet *ifp; 1214 { 1215 struct xi_softc *sc = ifp->if_softc; 1216 1217 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 1218 ++ifp->if_oerrors; 1219 1220 xi_reset(sc); 1221 } 1222 1223 static void 1224 xi_stop(sc) 1225 register struct xi_softc *sc; 1226 { 1227 DPRINTF(XID_CONFIG, ("xi_stop()\n")); 1228 1229 /* Disable interrupts. */ 1230 PAGE(sc, 0); 1231 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + CR, 0); 1232 1233 PAGE(sc, 1); 1234 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + IMR0, 0); 1235 1236 /* Power down, wait. */ 1237 PAGE(sc, 4); 1238 bus_space_write_1(sc->sc_bst, sc->sc_bsh, sc->sc_offset + GP1, 0); 1239 DELAY(40000); 1240 1241 /* Cancel watchdog timer. */ 1242 sc->sc_ethercom.ec_if.if_timer = 0; 1243 } 1244 1245 static void 1246 xi_init(sc) 1247 struct xi_softc *sc; 1248 { 1249 struct xi_pcmcia_softc *psc = (struct xi_pcmcia_softc *)sc; 1250 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1251 int s; 1252 1253 DPRINTF(XID_CONFIG, ("xi_init()\n")); 1254 1255 if ((psc->sc_resource & XI_RES_PCIC) == 0) 1256 xi_pcmcia_enable(psc); 1257 1258 s = splnet(); 1259 1260 xi_set_address(sc); 1261 1262 /* Set current media. */ 1263 mii_mediachg(&sc->sc_mii); 1264 1265 ifp->if_flags |= IFF_RUNNING; 1266 ifp->if_flags &= ~IFF_OACTIVE; 1267 splx(s); 1268 } 1269 1270 /* 1271 * Start outputting on the interface. 1272 * Always called as splnet(). 1273 */ 1274 static void 1275 xi_start(ifp) 1276 struct ifnet *ifp; 1277 { 1278 struct xi_softc *sc = ifp->if_softc; 1279 bus_space_tag_t bst = sc->sc_bst; 1280 bus_space_handle_t bsh = sc->sc_bsh; 1281 bus_size_t offset = sc->sc_offset; 1282 unsigned int s, len, pad = 0; 1283 struct mbuf *m0, *m; 1284 u_int16_t space; 1285 1286 DPRINTF(XID_CONFIG, ("xi_start()\n")); 1287 1288 /* Don't transmit if interface is busy or not running. */ 1289 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) { 1290 DPRINTF(XID_CONFIG, ("xi: interface busy or not running\n")); 1291 return; 1292 } 1293 1294 /* Peek at the next packet. */ 1295 IFQ_POLL(&ifp->if_snd, m0); 1296 if (m0 == 0) 1297 return; 1298 1299 /* We need to use m->m_pkthdr.len, so require the header. */ 1300 if (!(m0->m_flags & M_PKTHDR)) 1301 panic("xi_start: no header mbuf"); 1302 1303 len = m0->m_pkthdr.len; 1304 1305 /* Pad to ETHER_MIN_LEN - ETHER_CRC_LEN. */ 1306 if (len < ETHER_MIN_LEN - ETHER_CRC_LEN) 1307 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 1308 1309 PAGE(sc, 0); 1310 space = bus_space_read_2(bst, bsh, offset + TSO0) & 0x7fff; 1311 if (len + pad + 2 > space) { 1312 DPRINTF(XID_FIFO, 1313 ("xi: not enough space in output FIFO (%d > %d)\n", 1314 len + pad + 2, space)); 1315 return; 1316 } 1317 1318 IFQ_DEQUEUE(&ifp->if_snd, m0); 1319 1320 #if NBPFILTER > 0 1321 if (ifp->if_bpf) 1322 bpf_mtap(ifp->if_bpf, m0); 1323 #endif 1324 1325 /* 1326 * Do the output at splhigh() so that an interrupt from another device 1327 * won't cause a FIFO underrun. 1328 */ 1329 s = splhigh(); 1330 1331 bus_space_write_2(bst, bsh, offset + TSO2, (u_int16_t)len + pad + 2); 1332 bus_space_write_2(bst, bsh, offset + EDP, (u_int16_t)len + pad); 1333 for (m = m0; m; ) { 1334 if (m->m_len > 1) 1335 bus_space_write_multi_2(bst, bsh, offset + EDP, 1336 mtod(m, u_int16_t *), m->m_len>>1); 1337 if (m->m_len & 1) 1338 bus_space_write_1(bst, bsh, offset + EDP, 1339 *(mtod(m, u_int8_t *) + m->m_len - 1)); 1340 MFREE(m, m0); 1341 m = m0; 1342 } 1343 if (sc->sc_flags & XIFLAGS_MOHAWK) 1344 bus_space_write_1(bst, bsh, offset + CR, TX_PKT | ENABLE_INT); 1345 else { 1346 for (; pad > 1; pad -= 2) 1347 bus_space_write_2(bst, bsh, offset + EDP, 0); 1348 if (pad == 1) 1349 bus_space_write_1(bst, bsh, offset + EDP, 0); 1350 } 1351 1352 splx(s); 1353 1354 ifp->if_timer = 5; 1355 ++ifp->if_opackets; 1356 } 1357 1358 static int 1359 xi_ether_ioctl(ifp, cmd, data) 1360 struct ifnet *ifp; 1361 u_long cmd; 1362 caddr_t data; 1363 { 1364 struct ifaddr *ifa = (struct ifaddr *)data; 1365 struct xi_softc *sc = ifp->if_softc; 1366 1367 1368 DPRINTF(XID_CONFIG, ("xi_ether_ioctl()\n")); 1369 1370 switch (cmd) { 1371 case SIOCSIFADDR: 1372 ifp->if_flags |= IFF_UP; 1373 1374 switch (ifa->ifa_addr->sa_family) { 1375 #ifdef INET 1376 case AF_INET: 1377 xi_init(sc); 1378 arp_ifinit(ifp, ifa); 1379 break; 1380 #endif /* INET */ 1381 1382 #ifdef NS 1383 case AF_NS: 1384 { 1385 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1386 1387 if (ns_nullhost(*ina)) 1388 ina->x_host = *(union ns_host *) 1389 LLADDR(ifp->if_sadl); 1390 else 1391 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1392 ifp->if_addrlen); 1393 /* Set new address. */ 1394 xi_init(sc); 1395 break; 1396 } 1397 #endif /* NS */ 1398 1399 default: 1400 xi_init(sc); 1401 break; 1402 } 1403 break; 1404 1405 default: 1406 return (EINVAL); 1407 } 1408 1409 return (0); 1410 } 1411 1412 static int 1413 xi_ioctl(ifp, command, data) 1414 struct ifnet *ifp; 1415 u_long command; 1416 caddr_t data; 1417 { 1418 struct xi_pcmcia_softc *psc = ifp->if_softc; 1419 struct xi_softc *sc = &psc->sc_xi; 1420 struct ifreq *ifr = (struct ifreq *)data; 1421 int s, error = 0; 1422 1423 DPRINTF(XID_CONFIG, ("xi_ioctl()\n")); 1424 1425 s = splnet(); 1426 1427 switch (command) { 1428 case SIOCSIFADDR: 1429 error = xi_ether_ioctl(ifp, command, data); 1430 break; 1431 1432 case SIOCSIFFLAGS: 1433 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1434 1435 PAGE(sc, 0x42); 1436 if ((ifp->if_flags & IFF_PROMISC) || 1437 (ifp->if_flags & IFF_ALLMULTI)) 1438 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1439 sc->sc_offset + SWC1, 1440 SWC1_PROMISC | SWC1_MCAST_PROM); 1441 else 1442 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1443 sc->sc_offset + SWC1, 0); 1444 1445 /* 1446 * If interface is marked up and not running, then start it. 1447 * If it is marked down and running, stop it. 1448 * XXX If it's up then re-initialize it. This is so flags 1449 * such as IFF_PROMISC are handled. 1450 */ 1451 if (ifp->if_flags & IFF_UP) { 1452 xi_init(sc); 1453 } else { 1454 if (ifp->if_flags & IFF_RUNNING) { 1455 xi_pcmcia_disable(psc); 1456 xi_stop(sc); 1457 ifp->if_flags &= ~IFF_RUNNING; 1458 } 1459 } 1460 break; 1461 1462 case SIOCADDMULTI: 1463 case SIOCDELMULTI: 1464 sc->sc_all_mcasts = (ifp->if_flags & IFF_ALLMULTI) ? 1 : 0; 1465 error = (command == SIOCADDMULTI) ? 1466 ether_addmulti(ifr, &sc->sc_ethercom) : 1467 ether_delmulti(ifr, &sc->sc_ethercom); 1468 1469 if (error == ENETRESET) { 1470 /* 1471 * Multicast list has changed; set the hardware 1472 * filter accordingly. 1473 */ 1474 if (!sc->sc_all_mcasts && 1475 !(ifp->if_flags & IFF_PROMISC)) 1476 xi_set_address(sc); 1477 1478 /* 1479 * xi_set_address() can turn on all_mcasts if we run 1480 * out of space, so check it again rather than else {}. 1481 */ 1482 if (sc->sc_all_mcasts) 1483 xi_init(sc); 1484 error = 0; 1485 } 1486 break; 1487 1488 case SIOCSIFMEDIA: 1489 case SIOCGIFMEDIA: 1490 error = 1491 ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, command); 1492 break; 1493 1494 default: 1495 error = EINVAL; 1496 } 1497 splx(s); 1498 return (error); 1499 } 1500 1501 static void 1502 xi_set_address(sc) 1503 struct xi_softc *sc; 1504 { 1505 bus_space_tag_t bst = sc->sc_bst; 1506 bus_space_handle_t bsh = sc->sc_bsh; 1507 bus_size_t offset = sc->sc_offset; 1508 struct ethercom *ether = &sc->sc_ethercom; 1509 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1510 #if WORKING_MULTICAST 1511 struct ether_multistep step; 1512 struct ether_multi *enm; 1513 int page, pos, num; 1514 #endif 1515 int i; 1516 1517 DPRINTF(XID_CONFIG, ("xi_set_address()\n")); 1518 1519 PAGE(sc, 0x50); 1520 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1521 bus_space_write_1(bst, bsh, offset + IA + i, 1522 sc->sc_enaddr[(sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1523 } 1524 1525 if (ether->ec_multicnt > 0) { 1526 #ifdef WORKING_MULTICAST 1527 if (ether->ec_multicnt > 9) { 1528 #else 1529 { 1530 #endif 1531 PAGE(sc, 0x42); 1532 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 1533 sc->sc_offset + SWC1, 1534 SWC1_PROMISC | SWC1_MCAST_PROM); 1535 ifp->if_flags |= IFF_PROMISC; 1536 return; 1537 } 1538 1539 #ifdef WORKING_MULTICAST 1540 1541 ETHER_FIRST_MULTI(step, ether, enm); 1542 1543 pos = IA + 6; 1544 for (page = 0x50, num = ether->ec_multicnt; num > 0 && enm; 1545 num--) { 1546 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 1547 sizeof(enm->enm_addrlo)) != 0) { 1548 /* 1549 * The multicast address is really a range; 1550 * it's easier just to accept all multicasts. 1551 * XXX should we be setting IFF_ALLMULTI here? 1552 */ 1553 #if 0 1554 ifp->if_flags |= IFF_ALLMULTI; 1555 #endif 1556 sc->sc_all_mcasts=1; 1557 break; 1558 } 1559 1560 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1561 printf("%x:", enm->enm_addrlo[i]); 1562 bus_space_write_1(bst, bsh, offset + pos, 1563 enm->enm_addrlo[ 1564 (sc->sc_flags & XIFLAGS_MOHAWK) ? 5-i : i]); 1565 1566 if (++pos > 15) { 1567 pos = IA; 1568 page++; 1569 PAGE(sc, page); 1570 } 1571 } 1572 printf("\n"); 1573 ETHER_NEXT_MULTI(step, enm); 1574 } 1575 #endif 1576 } 1577 } 1578 1579 static void 1580 xi_cycle_power(sc) 1581 struct xi_softc *sc; 1582 { 1583 bus_space_tag_t bst = sc->sc_bst; 1584 bus_space_handle_t bsh = sc->sc_bsh; 1585 bus_size_t offset = sc->sc_offset; 1586 1587 DPRINTF(XID_CONFIG, ("xi_cycle_power()\n")); 1588 1589 PAGE(sc, 4); 1590 DELAY(1); 1591 bus_space_write_1(bst, bsh, offset + GP1, 0); 1592 DELAY(40000); 1593 if (sc->sc_flags & XIFLAGS_MOHAWK) 1594 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP); 1595 else 1596 /* XXX What is bit 2 (aka AIC)? */ 1597 bus_space_write_1(bst, bsh, offset + GP1, POWER_UP | 4); 1598 DELAY(20000); 1599 } 1600 1601 static void 1602 xi_full_reset(sc) 1603 struct xi_softc *sc; 1604 { 1605 bus_space_tag_t bst = sc->sc_bst; 1606 bus_space_handle_t bsh = sc->sc_bsh; 1607 bus_size_t offset = sc->sc_offset; 1608 1609 DPRINTF(XID_CONFIG, ("xi_full_reset()\n")); 1610 1611 /* Do an as extensive reset as possible on all functions. */ 1612 xi_cycle_power(sc); 1613 bus_space_write_1(bst, bsh, offset + CR, SOFT_RESET); 1614 DELAY(20000); 1615 bus_space_write_1(bst, bsh, offset + CR, 0); 1616 DELAY(20000); 1617 if (sc->sc_flags & XIFLAGS_MOHAWK) { 1618 PAGE(sc, 4); 1619 /* 1620 * Drive GP1 low to power up ML6692 and GP2 high to power up 1621 * the 10MHz chip. XXX What chip is that? The phy? 1622 */ 1623 bus_space_write_1(bst, bsh, offset + GP0, 1624 GP1_OUT | GP2_OUT | GP2_WR); 1625 } 1626 DELAY(500000); 1627 1628 /* Get revision information. XXX Symbolic constants. */ 1629 sc->sc_rev = bus_space_read_1(bst, bsh, offset + BV) & 1630 ((sc->sc_flags & XIFLAGS_MOHAWK) ? 0x70 : 0x30) >> 4; 1631 1632 /* Media selection. XXX Maybe manual overriding too? */ 1633 if (!(sc->sc_flags & XIFLAGS_MOHAWK)) { 1634 PAGE(sc, 4); 1635 /* 1636 * XXX I have no idea what this really does, it is from the 1637 * Linux driver. 1638 */ 1639 bus_space_write_1(bst, bsh, offset + GP0, GP1_OUT); 1640 } 1641 DELAY(40000); 1642 1643 /* Setup the ethernet interrupt mask. */ 1644 PAGE(sc, 1); 1645 #if 1 1646 bus_space_write_1(bst, bsh, offset + IMR0, 1647 ISR_TX_OFLOW | ISR_PKT_TX | ISR_MAC_INT | /* ISR_RX_EARLY | */ 1648 ISR_RX_FULL | ISR_RX_PKT_REJ | ISR_FORCED_INT); 1649 #else 1650 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1651 #endif 1652 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1653 /* XXX What is this? Not for Dingo at least. */ 1654 /* Unmask TX underrun detection */ 1655 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1656 } 1657 1658 /* 1659 * Disable source insertion. 1660 * XXX Dingo does not have this bit, but Linux does it unconditionally. 1661 */ 1662 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1663 PAGE(sc, 0x42); 1664 bus_space_write_1(bst, bsh, offset + SWC0, 0x20); 1665 } 1666 1667 /* Set the local memory dividing line. */ 1668 if (sc->sc_rev != 1) { 1669 PAGE(sc, 2); 1670 /* XXX Symbolic constant preferrable. */ 1671 bus_space_write_2(bst, bsh, offset + RBS0, 0x2000); 1672 } 1673 1674 xi_set_address(sc); 1675 1676 /* 1677 * Apparently the receive byte pointer can be bad after a reset, so 1678 * we hardwire it correctly. 1679 */ 1680 PAGE(sc, 0); 1681 bus_space_write_2(bst, bsh, offset + DO0, DO_CHG_OFFSET); 1682 1683 /* Setup ethernet MAC registers. XXX Symbolic constants. */ 1684 PAGE(sc, 0x40); 1685 bus_space_write_1(bst, bsh, offset + RX0MSK, 1686 PKT_TOO_LONG | CRC_ERR | RX_OVERRUN | RX_ABORT | RX_OK); 1687 bus_space_write_1(bst, bsh, offset + TX0MSK, 1688 CARRIER_LOST | EXCESSIVE_COLL | TX_UNDERRUN | LATE_COLLISION | 1689 SQE | TX_ABORT | TX_OK); 1690 if (!(sc->sc_flags & XIFLAGS_DINGO)) 1691 /* XXX From Linux, dunno what 0xb0 means. */ 1692 bus_space_write_1(bst, bsh, offset + TX1MSK, 0xb0); 1693 bus_space_write_1(bst, bsh, offset + RXST0, 0); 1694 bus_space_write_1(bst, bsh, offset + TXST0, 0); 1695 bus_space_write_1(bst, bsh, offset + TXST1, 0); 1696 1697 /* Enable MII function if available. */ 1698 if (LIST_FIRST(&sc->sc_mii.mii_phys)) { 1699 PAGE(sc, 2); 1700 bus_space_write_1(bst, bsh, offset + MSR, 1701 bus_space_read_1(bst, bsh, offset + MSR) | SELECT_MII); 1702 DELAY(20000); 1703 } else { 1704 PAGE(sc, 0); 1705 1706 /* XXX Do we need to do this? */ 1707 PAGE(sc, 0x42); 1708 bus_space_write_1(bst, bsh, offset + SWC1, SWC1_AUTO_MEDIA); 1709 DELAY(50000); 1710 1711 /* XXX Linux probes the media here. */ 1712 } 1713 1714 /* Configure the LED registers. */ 1715 PAGE(sc, 2); 1716 1717 /* XXX This is not good for 10base2. */ 1718 bus_space_write_1(bst, bsh, offset + LED, 1719 LED_TX_ACT << LED1_SHIFT | LED_10MB_LINK << LED0_SHIFT); 1720 if (sc->sc_flags & XIFLAGS_DINGO) 1721 bus_space_write_1(bst, bsh, offset + LED3, 1722 LED_100MB_LINK << LED3_SHIFT); 1723 1724 /* Enable receiver and go online. */ 1725 PAGE(sc, 0x40); 1726 bus_space_write_1(bst, bsh, offset + CMD0, ENABLE_RX | ONLINE); 1727 1728 #if 0 1729 /* XXX Linux does this here - is it necessary? */ 1730 PAGE(sc, 1); 1731 bus_space_write_1(bst, bsh, offset + IMR0, 0xff); 1732 if (!(sc->sc_flags & XIFLAGS_DINGO)) { 1733 /* XXX What is this? Not for Dingo at least. */ 1734 bus_space_write_1(bst, bsh, offset + IMR1, 1); 1735 } 1736 #endif 1737 1738 /* Enable interrupts. */ 1739 PAGE(sc, 0); 1740 bus_space_write_1(bst, bsh, offset + CR, ENABLE_INT); 1741 1742 /* XXX This is pure magic for me, found in the Linux driver. */ 1743 if ((sc->sc_flags & (XIFLAGS_DINGO | XIFLAGS_MODEM)) == XIFLAGS_MODEM) { 1744 if ((bus_space_read_1(bst, bsh, offset + 0x10) & 0x01) == 0) 1745 /* Unmask the master interrupt bit. */ 1746 bus_space_write_1(bst, bsh, offset + 0x10, 0x11); 1747 } 1748 1749 /* 1750 * The Linux driver says this: 1751 * We should switch back to page 0 to avoid a bug in revision 0 1752 * where regs with offset below 8 can't be read after an access 1753 * to the MAC registers. 1754 */ 1755 PAGE(sc, 0); 1756 } 1757