xref: /netbsd-src/sys/dev/pci/pciide_common.c (revision 5bbd2a12505d72a8177929a37b5cee489d0a1cfd)
1 /*	$NetBSD: pciide_common.c,v 1.57 2012/07/31 15:50:36 bouyer Exp $	*/
2 
3 
4 /*
5  * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26  *
27  */
28 
29 
30 /*
31  * Copyright (c) 1996, 1998 Christopher G. Demetriou.  All rights reserved.
32  *
33  * Redistribution and use in source and binary forms, with or without
34  * modification, are permitted provided that the following conditions
35  * are met:
36  * 1. Redistributions of source code must retain the above copyright
37  *    notice, this list of conditions and the following disclaimer.
38  * 2. Redistributions in binary form must reproduce the above copyright
39  *    notice, this list of conditions and the following disclaimer in the
40  *    documentation and/or other materials provided with the distribution.
41  * 3. All advertising materials mentioning features or use of this software
42  *    must display the following acknowledgement:
43  *      This product includes software developed by Christopher G. Demetriou
44  *	for the NetBSD Project.
45  * 4. The name of the author may not be used to endorse or promote products
46  *    derived from this software without specific prior written permission
47  *
48  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58  */
59 
60 /*
61  * PCI IDE controller driver.
62  *
63  * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
64  * sys/dev/pci/ppb.c, revision 1.16).
65  *
66  * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
67  * "Programming Interface for Bus Master IDE Controller, Revision 1.0
68  * 5/16/94" from the PCI SIG.
69  *
70  */
71 
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.57 2012/07/31 15:50:36 bouyer Exp $");
74 
75 #include <sys/param.h>
76 #include <sys/malloc.h>
77 
78 #include <dev/pci/pcireg.h>
79 #include <dev/pci/pcivar.h>
80 #include <dev/pci/pcidevs.h>
81 #include <dev/pci/pciidereg.h>
82 #include <dev/pci/pciidevar.h>
83 
84 #include <dev/ic/wdcreg.h>
85 
86 #ifdef ATADEBUG
87 int atadebug_pciide_mask = 0;
88 #endif
89 
90 #if NATA_DMA
91 static const char dmaerrfmt[] =
92     "%s:%d: unable to %s table DMA map for drive %d, error=%d\n";
93 #endif
94 
95 /* Default product description for devices not known from this controller */
96 const struct pciide_product_desc default_product_desc = {
97 	0,
98 	0,
99 	"Generic PCI IDE controller",
100 	default_chip_map,
101 };
102 
103 const struct pciide_product_desc *
104 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp)
105 {
106 	for (; pp->chip_map != NULL; pp++)
107 		if (PCI_PRODUCT(id) == pp->ide_product)
108 			break;
109 
110 	if (pp->chip_map == NULL)
111 		return NULL;
112 	return pp;
113 }
114 
115 void
116 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa, const struct pciide_product_desc *pp)
117 {
118 	pci_chipset_tag_t pc = pa->pa_pc;
119 	pcitag_t tag = pa->pa_tag;
120 #if NATA_DMA
121 	pcireg_t csr;
122 #endif
123 	const char *displaydev = NULL;
124 	int dontprint = 0;
125 
126 	sc->sc_pci_id = pa->pa_id;
127 	if (pp == NULL) {
128 		/* should only happen for generic pciide devices */
129 		sc->sc_pp = &default_product_desc;
130 	} else {
131 		sc->sc_pp = pp;
132 		/* if ide_name == NULL, printf is done in chip-specific map */
133 		if (pp->ide_name)
134 			displaydev = pp->ide_name;
135 		else
136 			dontprint = 1;
137 	}
138 
139 	if (dontprint) {
140 		aprint_naive("disk controller\n");
141 		aprint_normal("\n"); /* ??? */
142 	} else
143 		pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1);
144 
145 	sc->sc_pc = pa->pa_pc;
146 	sc->sc_tag = pa->pa_tag;
147 
148 #if NATA_DMA
149 	/* Set up DMA defaults; these might be adjusted by chip_map. */
150 	sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
151 	sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
152 #endif
153 
154 #ifdef ATADEBUG
155 	if (atadebug_pciide_mask & DEBUG_PROBE)
156 		pci_conf_print(sc->sc_pc, sc->sc_tag, NULL);
157 #endif
158 	sc->sc_pp->chip_map(sc, pa);
159 
160 #if NATA_DMA
161 	if (sc->sc_dma_ok) {
162 		csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
163 		csr |= PCI_COMMAND_MASTER_ENABLE;
164 		pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
165 	}
166 #endif
167 	ATADEBUG_PRINT(("pciide: command/status register=%x\n",
168 	    pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE);
169 }
170 
171 int
172 pciide_common_detach(struct pciide_softc *sc, int flags)
173 {
174 	struct pciide_channel *cp;
175 	struct ata_channel *wdc_cp;
176 	struct wdc_regs *wdr;
177 	int channel, drive;
178 	int rv;
179 
180 	rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags);
181 	if (rv)
182 		return rv;
183 
184 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
185 	     channel++) {
186 		cp = &sc->pciide_channels[channel];
187 		wdc_cp = &cp->ata_channel;
188 		wdr = CHAN_TO_WDC_REGS(wdc_cp);
189 
190 		if (wdc_cp->ch_flags & ATACH_DISABLED)
191 			continue;
192 
193 		if (wdr->cmd_ios != 0)
194 			bus_space_unmap(wdr->cmd_iot,
195 			    wdr->cmd_baseioh, wdr->cmd_ios);
196 		if (cp->compat != 0) {
197 			if (wdr->ctl_ios != 0)
198 				bus_space_unmap(wdr->ctl_iot,
199 				    wdr->ctl_ioh, wdr->ctl_ios);
200 		} else {
201 			if (cp->ctl_ios != 0)
202 				bus_space_unmap(wdr->ctl_iot,
203 				    cp->ctl_baseioh, cp->ctl_ios);
204 		}
205 
206 		for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
207 #if NATA_DMA
208 			pciide_dma_table_teardown(sc, channel, drive);
209 #endif
210 		}
211 
212 		free(cp->ata_channel.ch_queue, M_DEVBUF);
213 		cp->ata_channel.atabus = NULL;
214 	}
215 
216 #if NATA_DMA
217 	if (sc->sc_dma_ios != 0)
218 		bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios);
219 	if (sc->sc_ba5_ss != 0)
220 		bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss);
221 #endif
222 
223 	return 0;
224 }
225 
226 int
227 pciide_detach(device_t self, int flags)
228 {
229 	struct pciide_softc *sc = device_private(self);
230 	struct pciide_channel *cp;
231 	int channel;
232 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
233 	bool has_compat_chan;
234 
235 	has_compat_chan = false;
236 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
237 	     channel++) {
238 		cp = &sc->pciide_channels[channel];
239 		if (cp->compat != 0) {
240 			has_compat_chan = true;
241 		}
242 	}
243 
244 	if (has_compat_chan != false)
245 		return EBUSY;
246 #endif
247 
248 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
249 	     channel++) {
250 		cp = &sc->pciide_channels[channel];
251 		if (cp->compat != 0)
252 			if (cp->ih != NULL)
253 			       pciide_unmap_compat_intr(sc->sc_pc, cp, channel);
254 	}
255 
256 	if (sc->sc_pci_ih != NULL)
257 		pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih);
258 
259 	return pciide_common_detach(sc, flags);
260 }
261 
262 /* tell whether the chip is enabled or not */
263 int
264 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa)
265 {
266 	pcireg_t csr;
267 
268 	if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) {
269 		aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
270 		    "I/O access disabled at bridge\n");
271 		return 0;
272 	}
273 	csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
274 	if ((csr & PCI_COMMAND_IO_ENABLE) == 0) {
275 		aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
276 		    "I/O access disabled at device\n");
277 		return 0;
278 	}
279 	return 1;
280 }
281 
282 void
283 pciide_mapregs_compat(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan)
284 {
285 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
286 	struct ata_channel *wdc_cp = &cp->ata_channel;
287 	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
288 	int i;
289 
290 	cp->compat = 1;
291 
292 	wdr->cmd_iot = pa->pa_iot;
293 	if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan),
294 	    PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) {
295 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
296 		    "couldn't map %s channel cmd regs\n", cp->name);
297 		goto bad;
298 	}
299 	wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE;
300 
301 	wdr->ctl_iot = pa->pa_iot;
302 	if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan),
303 	    PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) {
304 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
305 		    "couldn't map %s channel ctl regs\n", cp->name);
306 		bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
307 		goto bad;
308 	}
309 	wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE;
310 
311 	for (i = 0; i < WDC_NREG; i++) {
312 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
313 		    i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
314 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
315 			    "couldn't subregion %s channel cmd regs\n",
316 			    cp->name);
317 			goto bad;
318 		}
319 	}
320 	wdc_init_shadow_regs(wdc_cp);
321 	wdr->data32iot = wdr->cmd_iot;
322 	wdr->data32ioh = wdr->cmd_iohs[0];
323 	return;
324 
325 bad:
326 	cp->ata_channel.ch_flags |= ATACH_DISABLED;
327 	return;
328 }
329 
330 void
331 pciide_mapregs_native(const struct pci_attach_args *pa,
332 	struct pciide_channel *cp, int (*pci_intr)(void *))
333 {
334 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
335 	struct ata_channel *wdc_cp = &cp->ata_channel;
336 	struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
337 	const char *intrstr;
338 	pci_intr_handle_t intrhandle;
339 	int i;
340 
341 	cp->compat = 0;
342 
343 	if (sc->sc_pci_ih == NULL) {
344 		if (pci_intr_map(pa, &intrhandle) != 0) {
345 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
346 			    "couldn't map native-PCI interrupt\n");
347 			goto bad;
348 		}
349 		intrstr = pci_intr_string(pa->pa_pc, intrhandle);
350 		sc->sc_pci_ih = pci_intr_establish(pa->pa_pc,
351 		    intrhandle, IPL_BIO, pci_intr, sc);
352 		if (sc->sc_pci_ih != NULL) {
353 			aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
354 			    "using %s for native-PCI interrupt\n",
355 			    intrstr ? intrstr : "unknown interrupt");
356 		} else {
357 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
358 			    "couldn't establish native-PCI interrupt");
359 			if (intrstr != NULL)
360 				aprint_error(" at %s", intrstr);
361 			aprint_error("\n");
362 			goto bad;
363 		}
364 	}
365 	cp->ih = sc->sc_pci_ih;
366 	if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel),
367 	    PCI_MAPREG_TYPE_IO, 0,
368 	    &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) {
369 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
370 		    "couldn't map %s channel cmd regs\n", cp->name);
371 		goto bad;
372 	}
373 
374 	if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel),
375 	    PCI_MAPREG_TYPE_IO, 0,
376 	    &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) {
377 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
378 		    "couldn't map %s channel ctl regs\n", cp->name);
379 		bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
380 		goto bad;
381 	}
382 	/*
383 	 * In native mode, 4 bytes of I/O space are mapped for the control
384 	 * register, the control register is at offset 2. Pass the generic
385 	 * code a handle for only one byte at the right offset.
386 	 */
387 	if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1,
388 	    &wdr->ctl_ioh) != 0) {
389 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
390 		    "unable to subregion %s channel ctl regs\n", cp->name);
391 		bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
392 		bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios);
393 		goto bad;
394 	}
395 
396 	for (i = 0; i < WDC_NREG; i++) {
397 		if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
398 		    i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
399 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
400 			    "couldn't subregion %s channel cmd regs\n",
401 			    cp->name);
402 			goto bad;
403 		}
404 	}
405 	wdc_init_shadow_regs(wdc_cp);
406 	wdr->data32iot = wdr->cmd_iot;
407 	wdr->data32ioh = wdr->cmd_iohs[0];
408 	return;
409 
410 bad:
411 	cp->ata_channel.ch_flags |= ATACH_DISABLED;
412 	return;
413 }
414 
415 #if NATA_DMA
416 void
417 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
418 {
419 	pcireg_t maptype;
420 	bus_addr_t addr;
421 	struct pciide_channel *pc;
422 	int reg, chan;
423 	bus_size_t size;
424 
425 	/*
426 	 * Map DMA registers
427 	 *
428 	 * Note that sc_dma_ok is the right variable to test to see if
429 	 * DMA can be done.  If the interface doesn't support DMA,
430 	 * sc_dma_ok will never be non-zero.  If the DMA regs couldn't
431 	 * be mapped, it'll be zero.  I.e., sc_dma_ok will only be
432 	 * non-zero if the interface supports DMA and the registers
433 	 * could be mapped.
434 	 *
435 	 * XXX Note that despite the fact that the Bus Master IDE specs
436 	 * XXX say that "The bus master IDE function uses 16 bytes of IO
437 	 * XXX space," some controllers (at least the United
438 	 * XXX Microelectronics UM8886BF) place it in memory space.
439 	 */
440 	maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
441 	    PCIIDE_REG_BUS_MASTER_DMA);
442 
443 	switch (maptype) {
444 	case PCI_MAPREG_TYPE_IO:
445 		sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag,
446 		    PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO,
447 		    &addr, NULL, NULL) == 0);
448 		if (sc->sc_dma_ok == 0) {
449 			aprint_verbose(
450 			    ", but unused (couldn't query registers)");
451 			break;
452 		}
453 		if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE)
454 		    && addr >= 0x10000) {
455 			sc->sc_dma_ok = 0;
456 			aprint_verbose(
457 			    ", but unused (registers at unsafe address "
458 			    "%#lx)", (unsigned long)addr);
459 			break;
460 		}
461 		/* FALLTHROUGH */
462 
463 	case PCI_MAPREG_MEM_TYPE_32BIT:
464 		sc->sc_dma_ok = (pci_mapreg_map(pa,
465 		    PCIIDE_REG_BUS_MASTER_DMA, maptype, 0,
466 		    &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios)
467 		    == 0);
468 		sc->sc_dmat = pa->pa_dmat;
469 		if (sc->sc_dma_ok == 0) {
470 			aprint_verbose(", but unused (couldn't map registers)");
471 		} else {
472 			sc->sc_wdcdev.dma_arg = sc;
473 			sc->sc_wdcdev.dma_init = pciide_dma_init;
474 			sc->sc_wdcdev.dma_start = pciide_dma_start;
475 			sc->sc_wdcdev.dma_finish = pciide_dma_finish;
476 		}
477 
478 		if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
479 		    PCIIDE_OPTIONS_NODMA) {
480 			aprint_verbose(
481 			    ", but unused (forced off by config file)");
482 			sc->sc_dma_ok = 0;
483 		}
484 		break;
485 
486 	default:
487 		sc->sc_dma_ok = 0;
488 		aprint_verbose(
489 		    ", but unsupported register maptype (0x%x)", maptype);
490 	}
491 
492 	if (sc->sc_dma_ok == 0)
493 		return;
494 
495 	/*
496 	 * Set up the default handles for the DMA registers.
497 	 * Just reserve 32 bits for each handle, unless space
498 	 * doesn't permit it.
499 	 */
500 	for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) {
501 		pc = &sc->pciide_channels[chan];
502 		for (reg = 0; reg < IDEDMA_NREGS; reg++) {
503 			size = 4;
504 			if (size > (IDEDMA_SCH_OFFSET - reg))
505 				size = IDEDMA_SCH_OFFSET - reg;
506 			if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
507 			    IDEDMA_SCH_OFFSET * chan + reg, size,
508 			    &pc->dma_iohs[reg]) != 0) {
509 				sc->sc_dma_ok = 0;
510 				aprint_verbose(", but can't subregion offset %d "
511 					      "size %lu", reg, (u_long)size);
512 				return;
513 			}
514 		}
515 	}
516 }
517 #endif	/* NATA_DMA */
518 
519 int
520 pciide_compat_intr(void *arg)
521 {
522 	struct pciide_channel *cp = arg;
523 
524 #ifdef DIAGNOSTIC
525 	/* should only be called for a compat channel */
526 	if (cp->compat == 0)
527 		panic("pciide compat intr called for non-compat chan %p", cp);
528 #endif
529 	return (wdcintr(&cp->ata_channel));
530 }
531 
532 int
533 pciide_pci_intr(void *arg)
534 {
535 	struct pciide_softc *sc = arg;
536 	struct pciide_channel *cp;
537 	struct ata_channel *wdc_cp;
538 	int i, rv, crv;
539 
540 	rv = 0;
541 	for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
542 		cp = &sc->pciide_channels[i];
543 		wdc_cp = &cp->ata_channel;
544 
545 		/* If a compat channel skip. */
546 		if (cp->compat)
547 			continue;
548 		/* if this channel not waiting for intr, skip */
549 		if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0)
550 			continue;
551 
552 		crv = wdcintr(wdc_cp);
553 		if (crv == 0)
554 			;		/* leave rv alone */
555 		else if (crv == 1)
556 			rv = 1;		/* claim the intr */
557 		else if (rv == 0)	/* crv should be -1 in this case */
558 			rv = crv;	/* if we've done no better, take it */
559 	}
560 	return (rv);
561 }
562 
563 #if NATA_DMA
564 void
565 pciide_channel_dma_setup(struct pciide_channel *cp)
566 {
567 	int drive, s;
568 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
569 	struct ata_drive_datas *drvp;
570 
571 	KASSERT(cp->ata_channel.ch_ndrives != 0);
572 
573 	for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
574 		drvp = &cp->ata_channel.ch_drive[drive];
575 		/* If no drive, skip */
576 		if (drvp->drive_type == ATA_DRIVET_NONE)
577 			continue;
578 		/* setup DMA if needed */
579 		if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
580 		    (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) ||
581 		    sc->sc_dma_ok == 0) {
582 			s = splbio();
583 			drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
584 			splx(s);
585 			continue;
586 		}
587 		if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel,
588 					   drive) != 0) {
589 			/* Abort DMA setup */
590 			s = splbio();
591 			drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
592 			splx(s);
593 			continue;
594 		}
595 	}
596 }
597 
598 #define NIDEDMA_TABLES(sc)	\
599 	(MAXPHYS/(min((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1)
600 
601 int
602 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive)
603 {
604 	int error;
605 	const bus_size_t dma_table_size =
606 	    sizeof(struct idedma_table) * NIDEDMA_TABLES(sc);
607 	struct pciide_dma_maps *dma_maps =
608 	    &sc->pciide_channels[channel].dma_maps[drive];
609 
610 	/* If table was already allocated, just return */
611 	if (dma_maps->dma_table)
612 		return 0;
613 
614 	/* Allocate memory for the DMA tables and map it */
615 	if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size,
616 	    IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg,
617 	    1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) {
618 		aprint_error(dmaerrfmt,
619 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
620 		    "allocate", drive, error);
621 		return error;
622 	}
623 	if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg,
624 	    dma_maps->dmamap_table_nseg, dma_table_size,
625 	    (void **)&dma_maps->dma_table,
626 	    BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
627 		aprint_error(dmaerrfmt,
628 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
629 		    "map", drive, error);
630 		return error;
631 	}
632 	ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, "
633 	    "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size,
634 	    (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE);
635 	/* Create and load table DMA map for this disk */
636 	if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size,
637 	    1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT,
638 	    &dma_maps->dmamap_table)) != 0) {
639 		aprint_error(dmaerrfmt,
640 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
641 		    "create", drive, error);
642 		return error;
643 	}
644 	if ((error = bus_dmamap_load(sc->sc_dmat,
645 	    dma_maps->dmamap_table,
646 	    dma_maps->dma_table,
647 	    dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) {
648 		aprint_error(dmaerrfmt,
649 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
650 		    "load", drive, error);
651 		return error;
652 	}
653 	ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n",
654 	    (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr),
655 	    DEBUG_PROBE);
656 	/* Create a xfer DMA map for this drive */
657 	if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
658 	    NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary,
659 	    BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
660 	    &dma_maps->dmamap_xfer)) != 0) {
661 		aprint_error(dmaerrfmt,
662 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
663 		    "create xfer", drive, error);
664 		return error;
665 	}
666 	return 0;
667 }
668 
669 void
670 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive)
671 {
672 	struct pciide_channel *cp;
673 	struct pciide_dma_maps *dma_maps;
674 
675 	cp = &sc->pciide_channels[channel];
676 	dma_maps = &cp->dma_maps[drive];
677 
678 	if (dma_maps->dma_table == NULL)
679 		return;
680 
681 	bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer);
682 	bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table);
683 	bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table);
684 	bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table,
685 	    sizeof(struct idedma_table) * NIDEDMA_TABLES(sc));
686 	bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg,
687 	    dma_maps->dmamap_table_nseg);
688 
689 	dma_maps->dma_table = NULL;
690 
691 	return;
692 }
693 
694 int
695 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive, void *databuf, size_t datalen, int flags)
696 {
697 	int error, seg;
698 	struct pciide_channel *cp = &sc->pciide_channels[channel];
699 	struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
700 
701 	error = bus_dmamap_load(sc->sc_dmat,
702 	    dma_maps->dmamap_xfer,
703 	    databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
704 	    ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
705 	if (error) {
706 		aprint_error(dmaerrfmt,
707 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
708 		    "load xfer", drive, error);
709 		return error;
710 	}
711 
712 	bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
713 	    dma_maps->dmamap_xfer->dm_mapsize,
714 	    (flags & WDC_DMA_READ) ?
715 	    BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
716 
717 	for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) {
718 #ifdef DIAGNOSTIC
719 		/* A segment must not cross a 64k boundary */
720 		{
721 		u_long phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr;
722 		u_long len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len;
723 		if ((phys & ~IDEDMA_BYTE_COUNT_MASK) !=
724 		    ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) {
725 			printf("pciide_dma: segment %d physical addr 0x%lx"
726 			    " len 0x%lx not properly aligned\n",
727 			    seg, phys, len);
728 			panic("pciide_dma: buf align");
729 		}
730 		}
731 #endif
732 		dma_maps->dma_table[seg].base_addr =
733 		    htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_addr);
734 		dma_maps->dma_table[seg].byte_count =
735 		    htole32(dma_maps->dmamap_xfer->dm_segs[seg].ds_len &
736 		    IDEDMA_BYTE_COUNT_MASK);
737 		ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n",
738 		   seg, le32toh(dma_maps->dma_table[seg].byte_count),
739 		   le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA);
740 
741 	}
742 	dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |=
743 	    htole32(IDEDMA_BYTE_COUNT_EOT);
744 
745 	bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0,
746 	    dma_maps->dmamap_table->dm_mapsize,
747 	    BUS_DMASYNC_PREWRITE);
748 
749 #ifdef DIAGNOSTIC
750 	if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) {
751 		printf("pciide_dma_dmamap_setup: addr 0x%lx "
752 		    "not properly aligned\n",
753 		    (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr);
754 		panic("pciide_dma_init: table align");
755 	}
756 #endif
757 	/* remember flags */
758 	dma_maps->dma_flags = flags;
759 
760 	return 0;
761 }
762 
763 int
764 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen, int flags)
765 {
766 	struct pciide_softc *sc = v;
767 	int error;
768 	struct pciide_channel *cp = &sc->pciide_channels[channel];
769 	struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
770 
771 	if ((error = pciide_dma_dmamap_setup(sc, channel, drive,
772 	    databuf, datalen, flags)) != 0)
773 		return error;
774 	/* Maps are ready. Start DMA function */
775 	/* Clear status bits */
776 	bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
777 	    bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
778 	/* Write table addr */
779 	bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0,
780 	    dma_maps->dmamap_table->dm_segs[0].ds_addr);
781 	/* set read/write */
782 	bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
783 	    ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd);
784 	return 0;
785 }
786 
787 void
788 pciide_dma_start(void *v, int channel, int drive)
789 {
790 	struct pciide_softc *sc = v;
791 	struct pciide_channel *cp = &sc->pciide_channels[channel];
792 
793 	ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS);
794 	bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
795 	    bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
796 		| IDEDMA_CMD_START);
797 }
798 
799 int
800 pciide_dma_finish(void *v, int channel, int drive, int force)
801 {
802 	struct pciide_softc *sc = v;
803 	u_int8_t status;
804 	int error = 0;
805 	struct pciide_channel *cp = &sc->pciide_channels[channel];
806 	struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
807 
808 	status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0);
809 	ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status),
810 	    DEBUG_XFERS);
811 
812 	if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0)
813 		return WDC_DMAST_NOIRQ;
814 
815 	/* stop DMA channel */
816 	bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
817 	    bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
818 		& ~IDEDMA_CMD_START);
819 
820 	/* Unload the map of the data buffer */
821 	bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
822 	    dma_maps->dmamap_xfer->dm_mapsize,
823 	    (dma_maps->dma_flags & WDC_DMA_READ) ?
824 	    BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
825 	bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
826 
827 	if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
828 		aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n",
829 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
830 		    drive, status);
831 		error |= WDC_DMAST_ERR;
832 	}
833 
834 	if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) {
835 		aprint_error("%s:%d:%d: bus-master DMA error: missing "
836 		    "interrupt, status=0x%x\n",
837 		    device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
838 		    channel, drive, status);
839 		error |= WDC_DMAST_NOIRQ;
840 	}
841 
842 	if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
843 		/* data underrun, may be a valid condition for ATAPI */
844 		error |= WDC_DMAST_UNDER;
845 	}
846 	return error;
847 }
848 
849 void
850 pciide_irqack(struct ata_channel *chp)
851 {
852 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
853 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
854 
855 	/* clear status bits in IDE DMA registers */
856 	bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
857 	    bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
858 }
859 #endif	/* NATA_DMA */
860 
861 /* some common code used by several chip_map */
862 int
863 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
864 {
865 	struct pciide_channel *cp = &sc->pciide_channels[channel];
866 	sc->wdc_chanarray[channel] = &cp->ata_channel;
867 	cp->name = PCIIDE_CHANNEL_NAME(channel);
868 	cp->ata_channel.ch_channel = channel;
869 	cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
870 	cp->ata_channel.ch_queue =
871 	    malloc(sizeof(struct ata_queue), M_DEVBUF, M_NOWAIT);
872 	if (cp->ata_channel.ch_queue == NULL) {
873 		aprint_error("%s %s channel: "
874 		    "can't allocate memory for command queue",
875 		device_xname(sc->sc_wdcdev.sc_atac.atac_dev), cp->name);
876 		return 0;
877 	}
878 	aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
879 	    "%s channel %s to %s mode\n", cp->name,
880 	    (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
881 	    "configured" : "wired",
882 	    (interface & PCIIDE_INTERFACE_PCI(channel)) ?
883 	    "native-PCI" : "compatibility");
884 	return 1;
885 }
886 
887 /* some common code used by several chip channel_map */
888 void
889 pciide_mapchan(const struct pci_attach_args *pa,
890 	struct pciide_channel *cp,
891 	pcireg_t interface, int (*pci_intr)(void *))
892 {
893 	struct ata_channel *wdc_cp = &cp->ata_channel;
894 
895 	if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel))
896 		pciide_mapregs_native(pa, cp, pci_intr);
897 	else {
898 		pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
899 		if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
900 			pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
901 	}
902 	wdcattach(wdc_cp);
903 }
904 
905 /*
906  * generic code to map the compat intr.
907  */
908 void
909 pciide_map_compat_intr(const struct pci_attach_args *pa, struct pciide_channel *cp, int compatchan)
910 {
911 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
912 
913 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
914 	cp->ih =
915 	   pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev,
916 	   pa, compatchan, pciide_compat_intr, cp);
917 	if (cp->ih == NULL) {
918 #endif
919 		aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
920 		    "no compatibility interrupt for use by %s "
921 		    "channel\n", cp->name);
922 		cp->ata_channel.ch_flags |= ATACH_DISABLED;
923 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
924 	}
925 #endif
926 }
927 
928 void
929 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp, int compatchan)
930 {
931 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
932 	struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
933 
934 	pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev,
935 	    sc->sc_pc, compatchan, cp->ih);
936 #endif
937 }
938 
939 void
940 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
941 {
942 	struct pciide_channel *cp;
943 	pcireg_t interface = PCI_INTERFACE(pa->pa_class);
944 	pcireg_t csr;
945 	int channel;
946 #if NATA_DMA
947 	int drive;
948 	u_int8_t idedma_ctl;
949 #endif
950 	const char *failreason;
951 	struct wdc_regs *wdr;
952 
953 	if (pciide_chipen(sc, pa) == 0)
954 		return;
955 
956 	if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
957 #if NATA_DMA
958 		aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
959 		    "bus-master DMA support present");
960 		if (sc->sc_pp == &default_product_desc &&
961 		    (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
962 		    PCIIDE_OPTIONS_DMA) == 0) {
963 			aprint_verbose(", but unused (no driver support)");
964 			sc->sc_dma_ok = 0;
965 		} else {
966 			pciide_mapreg_dma(sc, pa);
967 			if (sc->sc_dma_ok != 0)
968 				aprint_verbose(", used without full driver "
969 				    "support");
970 		}
971 #else
972 		aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
973 		    "bus-master DMA support present, but unused (no driver "
974 		    "support)");
975 #endif	/* NATA_DMA */
976 	} else {
977 		aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
978 		    "hardware does not support DMA");
979 #if NATA_DMA
980 		sc->sc_dma_ok = 0;
981 #endif
982 	}
983 	aprint_verbose("\n");
984 #if NATA_DMA
985 	if (sc->sc_dma_ok) {
986 		sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
987 		sc->sc_wdcdev.irqack = pciide_irqack;
988 	}
989 #endif
990 	sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
991 #if NATA_DMA
992 	sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
993 #endif
994 
995 	sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
996 	sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
997 	sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
998 	sc->sc_wdcdev.wdc_maxdrives = 2;
999 
1000 	wdc_allocate_regs(&sc->sc_wdcdev);
1001 
1002 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1003 	     channel++) {
1004 		cp = &sc->pciide_channels[channel];
1005 		if (pciide_chansetup(sc, channel, interface) == 0)
1006 			continue;
1007 		wdr = CHAN_TO_WDC_REGS(&cp->ata_channel);
1008 		if (interface & PCIIDE_INTERFACE_PCI(channel))
1009 			pciide_mapregs_native(pa, cp, pciide_pci_intr);
1010 		else
1011 			pciide_mapregs_compat(pa, cp,
1012 			    cp->ata_channel.ch_channel);
1013 		if (cp->ata_channel.ch_flags & ATACH_DISABLED)
1014 			continue;
1015 		/*
1016 		 * Check to see if something appears to be there.
1017 		 */
1018 		failreason = NULL;
1019 		/*
1020 		 * In native mode, always enable the controller. It's
1021 		 * not possible to have an ISA board using the same address
1022 		 * anyway.
1023 		 */
1024 		if (interface & PCIIDE_INTERFACE_PCI(channel)) {
1025 			wdcattach(&cp->ata_channel);
1026 			continue;
1027 		}
1028 		if (!wdcprobe(&cp->ata_channel)) {
1029 			failreason = "not responding; disabled or no drives?";
1030 			goto next;
1031 		}
1032 		/*
1033 		 * Now, make sure it's actually attributable to this PCI IDE
1034 		 * channel by trying to access the channel again while the
1035 		 * PCI IDE controller's I/O space is disabled.  (If the
1036 		 * channel no longer appears to be there, it belongs to
1037 		 * this controller.)  YUCK!
1038 		 */
1039 		csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
1040 		    PCI_COMMAND_STATUS_REG);
1041 		pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
1042 		    csr & ~PCI_COMMAND_IO_ENABLE);
1043 		if (wdcprobe(&cp->ata_channel))
1044 			failreason = "other hardware responding at addresses";
1045 		pci_conf_write(sc->sc_pc, sc->sc_tag,
1046 		    PCI_COMMAND_STATUS_REG, csr);
1047 next:
1048 		if (failreason) {
1049 			aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1050 			    "%s channel ignored (%s)\n", cp->name, failreason);
1051 			cp->ata_channel.ch_flags |= ATACH_DISABLED;
1052 			bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
1053 			    wdr->cmd_ios);
1054 			bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh,
1055 			    wdr->ctl_ios);
1056 		} else {
1057 			pciide_map_compat_intr(pa, cp,
1058 			    cp->ata_channel.ch_channel);
1059 			wdcattach(&cp->ata_channel);
1060 		}
1061 	}
1062 
1063 #if NATA_DMA
1064 	if (sc->sc_dma_ok == 0)
1065 		return;
1066 
1067 	/* Allocate DMA maps */
1068 	for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1069 	     channel++) {
1070 		idedma_ctl = 0;
1071 		cp = &sc->pciide_channels[channel];
1072 		for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
1073 			/*
1074 			 * we have not probed the drives yet, allocate
1075 			 * ressources for all of them.
1076 			 */
1077 			if (pciide_dma_table_setup(sc, channel, drive) != 0) {
1078 				/* Abort DMA setup */
1079 				aprint_error(
1080 				    "%s:%d:%d: can't allocate DMA maps, "
1081 				    "using PIO transfers\n",
1082 				    device_xname(
1083 				      sc->sc_wdcdev.sc_atac.atac_dev),
1084 				    channel, drive);
1085 				sc->sc_dma_ok = 0;
1086 				sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
1087 				sc->sc_wdcdev.irqack = NULL;
1088 				break;
1089 			}
1090 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1091 		}
1092 		if (idedma_ctl != 0) {
1093 			/* Add software bits in status register */
1094 			bus_space_write_1(sc->sc_dma_iot,
1095 			    cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
1096 		}
1097 	}
1098 #endif	/* NATA_DMA */
1099 }
1100 
1101 void
1102 sata_setup_channel(struct ata_channel *chp)
1103 {
1104 #if NATA_DMA
1105 	struct ata_drive_datas *drvp;
1106 	int drive;
1107 #if NATA_UDMA
1108 	int s;
1109 #endif
1110 	u_int32_t idedma_ctl;
1111 	struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
1112 	struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
1113 
1114 	/* setup DMA if needed */
1115 	pciide_channel_dma_setup(cp);
1116 
1117 	idedma_ctl = 0;
1118 
1119 	KASSERT(cp->ata_channel.ch_ndrives != 0);
1120 	for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
1121 		drvp = &chp->ch_drive[drive];
1122 		/* If no drive, skip */
1123 		if (drvp->drive_type == ATA_DRIVET_NONE)
1124 			continue;
1125 #if NATA_UDMA
1126 		if (drvp->drive_flags & ATA_DRIVE_UDMA) {
1127 			/* use Ultra/DMA */
1128 			s = splbio();
1129 			drvp->drive_flags &= ~ATA_DRIVE_DMA;
1130 			splx(s);
1131 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1132 		} else
1133 #endif	/* NATA_UDMA */
1134 		if (drvp->drive_flags & ATA_DRIVE_DMA) {
1135 			idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1136 		}
1137 	}
1138 
1139 	/*
1140 	 * Nothing to do to setup modes; it is meaningless in S-ATA
1141 	 * (but many S-ATA drives still want to get the SET_FEATURE
1142 	 * command).
1143 	 */
1144 	if (idedma_ctl != 0) {
1145 		/* Add software bits in status register */
1146 		bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
1147 		    idedma_ctl);
1148 	}
1149 #endif	/* NATA_DMA */
1150 }
1151