1 /* $NetBSD: pciide_common.c,v 1.71 2024/03/31 18:59:52 thorpej Exp $ */
2
3
4 /*
5 * Copyright (c) 1999, 2000, 2001, 2003 Manuel Bouyer.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 */
28
29
30 /*
31 * Copyright (c) 1996, 1998 Christopher G. Demetriou. All rights reserved.
32 *
33 * Redistribution and use in source and binary forms, with or without
34 * modification, are permitted provided that the following conditions
35 * are met:
36 * 1. Redistributions of source code must retain the above copyright
37 * notice, this list of conditions and the following disclaimer.
38 * 2. Redistributions in binary form must reproduce the above copyright
39 * notice, this list of conditions and the following disclaimer in the
40 * documentation and/or other materials provided with the distribution.
41 * 3. All advertising materials mentioning features or use of this software
42 * must display the following acknowledgement:
43 * This product includes software developed by Christopher G. Demetriou
44 * for the NetBSD Project.
45 * 4. The name of the author may not be used to endorse or promote products
46 * derived from this software without specific prior written permission
47 *
48 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
52 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
53 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
54 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
55 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
56 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
57 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
58 */
59
60 /*
61 * PCI IDE controller driver.
62 *
63 * Author: Christopher G. Demetriou, March 2, 1998 (derived from NetBSD
64 * sys/dev/pci/ppb.c, revision 1.16).
65 *
66 * See "PCI IDE Controller Specification, Revision 1.0 3/4/94" and
67 * "Programming Interface for Bus Master IDE Controller, Revision 1.0
68 * 5/16/94" from the PCI SIG.
69 *
70 */
71
72 #include <sys/cdefs.h>
73 __KERNEL_RCSID(0, "$NetBSD: pciide_common.c,v 1.71 2024/03/31 18:59:52 thorpej Exp $");
74
75 #include <sys/param.h>
76
77 #include <dev/pci/pcireg.h>
78 #include <dev/pci/pcivar.h>
79 #include <dev/pci/pcidevs.h>
80 #include <dev/pci/pciidereg.h>
81 #include <dev/pci/pciidevar.h>
82
83 #include <dev/ic/wdcreg.h>
84
85 #ifdef ATADEBUG
86 int atadebug_pciide_mask = 0;
87 #endif
88
89 #if NATA_DMA
90 static const char dmaerrfmt[] =
91 "%s:%d: unable to %s table DMA map for drive %d, error=%d\n";
92 #endif
93
94 /* Default product description for devices not known from this controller */
95 const struct pciide_product_desc default_product_desc = {
96 0,
97 0,
98 "Generic PCI IDE controller",
99 default_chip_map,
100 };
101
102 const struct pciide_product_desc *
pciide_lookup_product(pcireg_t id,const struct pciide_product_desc * pp)103 pciide_lookup_product(pcireg_t id, const struct pciide_product_desc *pp)
104 {
105 for (; pp->chip_map != NULL; pp++)
106 if (PCI_PRODUCT(id) == pp->ide_product)
107 break;
108
109 if (pp->chip_map == NULL)
110 return NULL;
111 return pp;
112 }
113
114 void
pciide_common_attach(struct pciide_softc * sc,const struct pci_attach_args * pa,const struct pciide_product_desc * pp)115 pciide_common_attach(struct pciide_softc *sc, const struct pci_attach_args *pa,
116 const struct pciide_product_desc *pp)
117 {
118 pci_chipset_tag_t pc = pa->pa_pc;
119 pcitag_t tag = pa->pa_tag;
120 #if NATA_DMA
121 pcireg_t csr;
122 #endif
123 const char *displaydev = NULL;
124 int dontprint = 0;
125
126 sc->sc_pci_id = pa->pa_id;
127 if (pp == NULL) {
128 /* should only happen for generic pciide devices */
129 sc->sc_pp = &default_product_desc;
130 } else {
131 sc->sc_pp = pp;
132 /* if ide_name == NULL, printf is done in chip-specific map */
133 if (pp->ide_name)
134 displaydev = pp->ide_name;
135 else
136 dontprint = 1;
137 }
138
139 if (dontprint) {
140 aprint_naive("disk controller\n");
141 aprint_normal("\n"); /* ??? */
142 } else
143 pci_aprint_devinfo_fancy(pa, "disk controller", displaydev, 1);
144
145 sc->sc_pc = pa->pa_pc;
146 sc->sc_tag = pa->pa_tag;
147
148 #if NATA_DMA
149 /* Set up DMA defaults; these might be adjusted by chip_map. */
150 sc->sc_dma_maxsegsz = IDEDMA_BYTE_COUNT_MAX;
151 sc->sc_dma_boundary = IDEDMA_BYTE_COUNT_ALIGN;
152 #endif
153
154 #ifdef ATADEBUG
155 if (atadebug_pciide_mask & DEBUG_PROBE)
156 pci_conf_print(sc->sc_pc, sc->sc_tag, NULL);
157 #endif
158 sc->sc_pp->chip_map(sc, pa);
159
160 #if NATA_DMA
161 if (sc->sc_dma_ok) {
162 csr = pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG);
163 csr |= PCI_COMMAND_MASTER_ENABLE;
164 pci_conf_write(pc, tag, PCI_COMMAND_STATUS_REG, csr);
165 }
166 #endif
167 ATADEBUG_PRINT(("pciide: command/status register=%x\n",
168 pci_conf_read(pc, tag, PCI_COMMAND_STATUS_REG)), DEBUG_PROBE);
169 }
170
171 int
pciide_common_detach(struct pciide_softc * sc,int flags)172 pciide_common_detach(struct pciide_softc *sc, int flags)
173 {
174 struct pciide_channel *cp;
175 struct ata_channel *wdc_cp;
176 struct wdc_regs *wdr;
177 int channel, drive;
178 int rv;
179
180 rv = wdcdetach(sc->sc_wdcdev.sc_atac.atac_dev, flags);
181 if (rv)
182 return rv;
183
184 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
185 channel++) {
186 cp = &sc->pciide_channels[channel];
187 wdc_cp = &cp->ata_channel;
188 wdr = CHAN_TO_WDC_REGS(wdc_cp);
189
190 if (wdc_cp->ch_flags & ATACH_DISABLED)
191 continue;
192
193 if (wdr->cmd_ios != 0)
194 bus_space_unmap(wdr->cmd_iot,
195 wdr->cmd_baseioh, wdr->cmd_ios);
196 if (cp->compat != 0) {
197 if (wdr->ctl_ios != 0)
198 bus_space_unmap(wdr->ctl_iot,
199 wdr->ctl_ioh, wdr->ctl_ios);
200 } else {
201 if (cp->ctl_ios != 0)
202 bus_space_unmap(wdr->ctl_iot,
203 cp->ctl_baseioh, cp->ctl_ios);
204 }
205
206 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
207 #if NATA_DMA
208 pciide_dma_table_teardown(sc, channel, drive);
209 #endif
210 }
211 }
212
213 #if NATA_DMA
214 if (sc->sc_dma_ios != 0)
215 bus_space_unmap(sc->sc_dma_iot, sc->sc_dma_ioh, sc->sc_dma_ios);
216 if (sc->sc_ba5_ss != 0)
217 bus_space_unmap(sc->sc_ba5_st, sc->sc_ba5_sh, sc->sc_ba5_ss);
218 #endif
219
220 return 0;
221 }
222
223 int
pciide_detach(device_t self,int flags)224 pciide_detach(device_t self, int flags)
225 {
226 struct pciide_softc *sc = device_private(self);
227 struct pciide_channel *cp;
228 int channel;
229 #ifndef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
230 bool has_compat_chan;
231
232 has_compat_chan = false;
233 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
234 channel++) {
235 cp = &sc->pciide_channels[channel];
236 if (cp->compat != 0) {
237 has_compat_chan = true;
238 }
239 }
240
241 if (has_compat_chan != false)
242 return EBUSY;
243 #endif
244
245 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
246 channel++) {
247 cp = &sc->pciide_channels[channel];
248 if (cp->compat != 0)
249 if (cp->ih != NULL) {
250 pciide_unmap_compat_intr(sc->sc_pc, cp, channel);
251 cp->ih = NULL;
252 }
253 }
254
255 if (sc->sc_pci_ih != NULL) {
256 pci_intr_disestablish(sc->sc_pc, sc->sc_pci_ih);
257 sc->sc_pci_ih = NULL;
258 }
259
260 return pciide_common_detach(sc, flags);
261 }
262
263 /* tell whether the chip is enabled or not */
264 int
pciide_chipen(struct pciide_softc * sc,const struct pci_attach_args * pa)265 pciide_chipen(struct pciide_softc *sc, const struct pci_attach_args *pa)
266 {
267 pcireg_t csr;
268
269 if ((pa->pa_flags & PCI_FLAGS_IO_OKAY) == 0) {
270 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
271 "I/O access disabled at bridge\n");
272 return 0;
273 }
274 csr = pci_conf_read(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG);
275 if ((csr & PCI_COMMAND_IO_ENABLE) == 0) {
276 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
277 "I/O access disabled at device\n");
278 return 0;
279 }
280 return 1;
281 }
282
283 void
pciide_mapregs_compat(const struct pci_attach_args * pa,struct pciide_channel * cp,int compatchan)284 pciide_mapregs_compat(const struct pci_attach_args *pa,
285 struct pciide_channel *cp, int compatchan)
286 {
287 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
288 struct ata_channel *wdc_cp = &cp->ata_channel;
289 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
290 int i;
291
292 cp->compat = 1;
293
294 wdr->cmd_iot = pa->pa_iot;
295 if (bus_space_map(wdr->cmd_iot, PCIIDE_COMPAT_CMD_BASE(compatchan),
296 PCIIDE_COMPAT_CMD_SIZE, 0, &wdr->cmd_baseioh) != 0) {
297 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
298 "couldn't map %s channel cmd regs\n", cp->name);
299 goto bad;
300 }
301 wdr->cmd_ios = PCIIDE_COMPAT_CMD_SIZE;
302
303 wdr->ctl_iot = pa->pa_iot;
304 if (bus_space_map(wdr->ctl_iot, PCIIDE_COMPAT_CTL_BASE(compatchan),
305 PCIIDE_COMPAT_CTL_SIZE, 0, &wdr->ctl_ioh) != 0) {
306 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
307 "couldn't map %s channel ctl regs\n", cp->name);
308 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
309 goto bad;
310 }
311 wdr->ctl_ios = PCIIDE_COMPAT_CTL_SIZE;
312
313 for (i = 0; i < WDC_NREG; i++) {
314 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
315 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
316 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
317 "couldn't subregion %s channel cmd regs\n",
318 cp->name);
319 goto bad;
320 }
321 }
322 wdc_init_shadow_regs(wdr);
323 wdr->data32iot = wdr->cmd_iot;
324 wdr->data32ioh = wdr->cmd_iohs[0];
325 return;
326
327 bad:
328 cp->ata_channel.ch_flags |= ATACH_DISABLED;
329 return;
330 }
331
332 void
pciide_mapregs_native(const struct pci_attach_args * pa,struct pciide_channel * cp,int (* pci_intr)(void *))333 pciide_mapregs_native(const struct pci_attach_args *pa,
334 struct pciide_channel *cp, int (*pci_intr)(void *))
335 {
336 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
337 struct ata_channel *wdc_cp = &cp->ata_channel;
338 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(wdc_cp);
339 const char *intrstr;
340 pci_intr_handle_t intrhandle;
341 int i;
342 char intrbuf[PCI_INTRSTR_LEN];
343
344 cp->compat = 0;
345
346 if (sc->sc_pci_ih == NULL) {
347 if (pci_intr_map(pa, &intrhandle) != 0) {
348 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
349 "couldn't map native-PCI interrupt\n");
350 goto bad;
351 }
352 intrstr = pci_intr_string(pa->pa_pc, intrhandle, intrbuf, sizeof(intrbuf));
353 sc->sc_pci_ih = pci_intr_establish_xname(pa->pa_pc,
354 intrhandle, IPL_BIO, pci_intr, sc,
355 device_xname(sc->sc_wdcdev.sc_atac.atac_dev));
356 if (sc->sc_pci_ih != NULL) {
357 aprint_normal_dev(sc->sc_wdcdev.sc_atac.atac_dev,
358 "using %s for native-PCI interrupt\n",
359 intrstr ? intrstr : "unknown interrupt");
360 } else {
361 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
362 "couldn't establish native-PCI interrupt");
363 if (intrstr != NULL)
364 aprint_error(" at %s", intrstr);
365 aprint_error("\n");
366 goto bad;
367 }
368 }
369 cp->ih = sc->sc_pci_ih;
370 if (pci_mapreg_map(pa, PCIIDE_REG_CMD_BASE(wdc_cp->ch_channel),
371 PCI_MAPREG_TYPE_IO, 0,
372 &wdr->cmd_iot, &wdr->cmd_baseioh, NULL, &wdr->cmd_ios) != 0) {
373 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
374 "couldn't map %s channel cmd regs\n", cp->name);
375 goto bad;
376 }
377
378 if (pci_mapreg_map(pa, PCIIDE_REG_CTL_BASE(wdc_cp->ch_channel),
379 PCI_MAPREG_TYPE_IO, 0,
380 &wdr->ctl_iot, &cp->ctl_baseioh, NULL, &cp->ctl_ios) != 0) {
381 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
382 "couldn't map %s channel ctl regs\n", cp->name);
383 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
384 goto bad;
385 }
386 /*
387 * In native mode, 4 bytes of I/O space are mapped for the control
388 * register, the control register is at offset 2. Pass the generic
389 * code a handle for only one byte at the right offset.
390 */
391 if (bus_space_subregion(wdr->ctl_iot, cp->ctl_baseioh, 2, 1,
392 &wdr->ctl_ioh) != 0) {
393 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
394 "unable to subregion %s channel ctl regs\n", cp->name);
395 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh, wdr->cmd_ios);
396 bus_space_unmap(wdr->cmd_iot, cp->ctl_baseioh, cp->ctl_ios);
397 goto bad;
398 }
399
400 for (i = 0; i < WDC_NREG; i++) {
401 if (bus_space_subregion(wdr->cmd_iot, wdr->cmd_baseioh, i,
402 i == 0 ? 4 : 1, &wdr->cmd_iohs[i]) != 0) {
403 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
404 "couldn't subregion %s channel cmd regs\n",
405 cp->name);
406 goto bad;
407 }
408 }
409 wdc_init_shadow_regs(wdr);
410 wdr->data32iot = wdr->cmd_iot;
411 wdr->data32ioh = wdr->cmd_iohs[0];
412 return;
413
414 bad:
415 cp->ata_channel.ch_flags |= ATACH_DISABLED;
416 return;
417 }
418
419 #if NATA_DMA
420 void
pciide_mapreg_dma(struct pciide_softc * sc,const struct pci_attach_args * pa)421 pciide_mapreg_dma(struct pciide_softc *sc, const struct pci_attach_args *pa)
422 {
423 pcireg_t maptype;
424 bus_addr_t addr;
425 struct pciide_channel *pc;
426 int reg, chan;
427 bus_size_t size;
428
429 /*
430 * Map DMA registers
431 *
432 * Note that sc_dma_ok is the right variable to test to see if
433 * DMA can be done. If the interface doesn't support DMA,
434 * sc_dma_ok will never be non-zero. If the DMA regs couldn't
435 * be mapped, it'll be zero. I.e., sc_dma_ok will only be
436 * non-zero if the interface supports DMA and the registers
437 * could be mapped.
438 *
439 * XXX Note that despite the fact that the Bus Master IDE specs
440 * XXX say that "The bus master IDE function uses 16 bytes of IO
441 * XXX space," some controllers (at least the United
442 * XXX Microelectronics UM8886BF) place it in memory space.
443 */
444 maptype = pci_mapreg_type(pa->pa_pc, pa->pa_tag,
445 PCIIDE_REG_BUS_MASTER_DMA);
446
447 switch (maptype) {
448 case PCI_MAPREG_TYPE_IO:
449 sc->sc_dma_ok = (pci_mapreg_info(pa->pa_pc, pa->pa_tag,
450 PCIIDE_REG_BUS_MASTER_DMA, PCI_MAPREG_TYPE_IO,
451 &addr, NULL, NULL) == 0);
452 if (sc->sc_dma_ok == 0) {
453 aprint_verbose(
454 ", but unused (couldn't query registers)");
455 break;
456 }
457 if ((sc->sc_pp->ide_flags & IDE_16BIT_IOSPACE)
458 && addr >= 0x10000) {
459 sc->sc_dma_ok = 0;
460 aprint_verbose(
461 ", but unused (registers at unsafe address "
462 "%#lx)", (unsigned long)addr);
463 break;
464 }
465 /* FALLTHROUGH */
466
467 case PCI_MAPREG_MEM_TYPE_32BIT:
468 sc->sc_dma_ok = (pci_mapreg_map(pa,
469 PCIIDE_REG_BUS_MASTER_DMA, maptype, 0,
470 &sc->sc_dma_iot, &sc->sc_dma_ioh, NULL, &sc->sc_dma_ios)
471 == 0);
472 sc->sc_dmat = pa->pa_dmat;
473 if (sc->sc_dma_ok == 0) {
474 aprint_verbose(", but unused (couldn't map registers)");
475 } else {
476 sc->sc_wdcdev.dma_arg = sc;
477 sc->sc_wdcdev.dma_init = pciide_dma_init;
478 sc->sc_wdcdev.dma_start = pciide_dma_start;
479 sc->sc_wdcdev.dma_finish = pciide_dma_finish;
480 }
481
482 if (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
483 PCIIDE_OPTIONS_NODMA) {
484 aprint_verbose(
485 ", but unused (forced off by config file)");
486 sc->sc_dma_ok = 0;
487 } else {
488 bool disable;
489
490 if (prop_dictionary_get_bool(
491 device_properties(sc->sc_wdcdev.sc_atac.atac_dev),
492 "pciide-disable-dma", &disable) && disable) {
493 aprint_verbose(
494 ", but unused (disabled by platform)");
495 sc->sc_dma_ok = 0;
496 }
497 }
498 break;
499
500 default:
501 sc->sc_dma_ok = 0;
502 aprint_verbose(
503 ", but unsupported register maptype (0x%x)", maptype);
504 }
505
506 if (sc->sc_dma_ok == 0)
507 return;
508
509 /*
510 * Set up the default handles for the DMA registers.
511 * Just reserve 32 bits for each handle, unless space
512 * doesn't permit it.
513 */
514 for (chan = 0; chan < PCIIDE_NUM_CHANNELS; chan++) {
515 pc = &sc->pciide_channels[chan];
516 for (reg = 0; reg < IDEDMA_NREGS; reg++) {
517 size = 4;
518 if (size > (IDEDMA_SCH_OFFSET - reg))
519 size = IDEDMA_SCH_OFFSET - reg;
520 if (bus_space_subregion(sc->sc_dma_iot, sc->sc_dma_ioh,
521 IDEDMA_SCH_OFFSET * chan + reg, size,
522 &pc->dma_iohs[reg]) != 0) {
523 sc->sc_dma_ok = 0;
524 aprint_verbose(", but can't subregion offset %d "
525 "size %lu", reg, (u_long)size);
526 return;
527 }
528 }
529 }
530 }
531 #endif /* NATA_DMA */
532
533 int
pciide_compat_intr(void * arg)534 pciide_compat_intr(void *arg)
535 {
536 struct pciide_channel *cp = arg;
537
538 #ifdef DIAGNOSTIC
539 /* should only be called for a compat channel */
540 if (cp->compat == 0)
541 panic("pciide compat intr called for non-compat chan %p", cp);
542 #endif
543 return (wdcintr(&cp->ata_channel));
544 }
545
546 int
pciide_pci_intr(void * arg)547 pciide_pci_intr(void *arg)
548 {
549 struct pciide_softc *sc = arg;
550 struct pciide_channel *cp;
551 struct ata_channel *wdc_cp;
552 int i, rv, crv;
553
554 rv = 0;
555 for (i = 0; i < sc->sc_wdcdev.sc_atac.atac_nchannels; i++) {
556 cp = &sc->pciide_channels[i];
557 wdc_cp = &cp->ata_channel;
558
559 /* If a compat channel skip. */
560 if (cp->compat)
561 continue;
562
563 /* if this channel not waiting for intr, skip */
564 if ((wdc_cp->ch_flags & ATACH_IRQ_WAIT) == 0)
565 continue;
566
567 crv = wdcintr(wdc_cp);
568 if (crv == 0)
569 ; /* leave rv alone */
570 else if (crv == 1)
571 rv = 1; /* claim the intr */
572 else if (rv == 0) /* crv should be -1 in this case */
573 rv = crv; /* if we've done no better, take it */
574 }
575 return (rv);
576 }
577
578 #if NATA_DMA
579 void
pciide_channel_dma_setup(struct pciide_channel * cp)580 pciide_channel_dma_setup(struct pciide_channel *cp)
581 {
582 int drive, s;
583 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
584 struct ata_drive_datas *drvp;
585
586 KASSERT(cp->ata_channel.ch_ndrives != 0);
587
588 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
589 drvp = &cp->ata_channel.ch_drive[drive];
590 /* If no drive, skip */
591 if (drvp->drive_type == ATA_DRIVET_NONE)
592 continue;
593 /* setup DMA if needed */
594 if (((drvp->drive_flags & ATA_DRIVE_DMA) == 0 &&
595 (drvp->drive_flags & ATA_DRIVE_UDMA) == 0) ||
596 sc->sc_dma_ok == 0) {
597 s = splbio();
598 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
599 splx(s);
600 continue;
601 }
602 if (pciide_dma_table_setup(sc, cp->ata_channel.ch_channel,
603 drive) != 0) {
604 /* Abort DMA setup */
605 s = splbio();
606 drvp->drive_flags &= ~(ATA_DRIVE_DMA | ATA_DRIVE_UDMA);
607 splx(s);
608 continue;
609 }
610 }
611 }
612
613 #define NIDEDMA_TABLES(sc) \
614 (MAXPHYS/(uimin((sc)->sc_dma_maxsegsz, PAGE_SIZE)) + 1)
615
616 int
pciide_dma_table_setup(struct pciide_softc * sc,int channel,int drive)617 pciide_dma_table_setup(struct pciide_softc *sc, int channel, int drive)
618 {
619 int error;
620 const bus_size_t dma_table_size =
621 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc);
622 struct pciide_dma_maps *dma_maps =
623 &sc->pciide_channels[channel].dma_maps[drive];
624
625 /* If table was already allocated, just return */
626 if (dma_maps->dma_table)
627 return 0;
628
629 /* Allocate memory for the DMA tables and map it */
630 if ((error = bus_dmamem_alloc(sc->sc_dmat, dma_table_size,
631 IDEDMA_TBL_ALIGN, IDEDMA_TBL_ALIGN, &dma_maps->dmamap_table_seg,
632 1, &dma_maps->dmamap_table_nseg, BUS_DMA_NOWAIT)) != 0) {
633 aprint_error(dmaerrfmt,
634 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
635 "allocate", drive, error);
636 return error;
637 }
638 if ((error = bus_dmamem_map(sc->sc_dmat, &dma_maps->dmamap_table_seg,
639 dma_maps->dmamap_table_nseg, dma_table_size,
640 (void **)&dma_maps->dma_table,
641 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) {
642 aprint_error(dmaerrfmt,
643 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
644 "map", drive, error);
645 return error;
646 }
647 ATADEBUG_PRINT(("pciide_dma_table_setup: table at %p len %lu, "
648 "phy 0x%lx\n", dma_maps->dma_table, (u_long)dma_table_size,
649 (unsigned long)dma_maps->dmamap_table_seg.ds_addr), DEBUG_PROBE);
650 /* Create and load table DMA map for this disk */
651 if ((error = bus_dmamap_create(sc->sc_dmat, dma_table_size,
652 1, dma_table_size, IDEDMA_TBL_ALIGN, BUS_DMA_NOWAIT,
653 &dma_maps->dmamap_table)) != 0) {
654 aprint_error(dmaerrfmt,
655 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
656 "create", drive, error);
657 return error;
658 }
659 if ((error = bus_dmamap_load(sc->sc_dmat,
660 dma_maps->dmamap_table,
661 dma_maps->dma_table,
662 dma_table_size, NULL, BUS_DMA_NOWAIT)) != 0) {
663 aprint_error(dmaerrfmt,
664 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
665 "load", drive, error);
666 return error;
667 }
668 ATADEBUG_PRINT(("pciide_dma_table_setup: phy addr of table 0x%lx\n",
669 (unsigned long)dma_maps->dmamap_table->dm_segs[0].ds_addr),
670 DEBUG_PROBE);
671 /* Create a xfer DMA map for this drive */
672 if ((error = bus_dmamap_create(sc->sc_dmat, MAXPHYS,
673 NIDEDMA_TABLES(sc), sc->sc_dma_maxsegsz, sc->sc_dma_boundary,
674 BUS_DMA_NOWAIT | BUS_DMA_ALLOCNOW,
675 &dma_maps->dmamap_xfer)) != 0) {
676 aprint_error(dmaerrfmt,
677 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
678 "create xfer", drive, error);
679 return error;
680 }
681 return 0;
682 }
683
684 void
pciide_dma_table_teardown(struct pciide_softc * sc,int channel,int drive)685 pciide_dma_table_teardown(struct pciide_softc *sc, int channel, int drive)
686 {
687 struct pciide_channel *cp;
688 struct pciide_dma_maps *dma_maps;
689
690 cp = &sc->pciide_channels[channel];
691 dma_maps = &cp->dma_maps[drive];
692
693 if (dma_maps->dma_table == NULL)
694 return;
695
696 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_xfer);
697 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_table);
698 bus_dmamap_destroy(sc->sc_dmat, dma_maps->dmamap_table);
699 bus_dmamem_unmap(sc->sc_dmat, dma_maps->dma_table,
700 sizeof(struct idedma_table) * NIDEDMA_TABLES(sc));
701 bus_dmamem_free(sc->sc_dmat, &dma_maps->dmamap_table_seg,
702 dma_maps->dmamap_table_nseg);
703
704 dma_maps->dma_table = NULL;
705
706 return;
707 }
708
709 int
pciide_dma_dmamap_setup(struct pciide_softc * sc,int channel,int drive,void * databuf,size_t datalen,int flags)710 pciide_dma_dmamap_setup(struct pciide_softc *sc, int channel, int drive,
711 void *databuf, size_t datalen, int flags)
712 {
713 int error, seg;
714 struct pciide_channel *cp = &sc->pciide_channels[channel];
715 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
716
717 error = bus_dmamap_load(sc->sc_dmat,
718 dma_maps->dmamap_xfer,
719 databuf, datalen, NULL, BUS_DMA_NOWAIT | BUS_DMA_STREAMING |
720 ((flags & WDC_DMA_READ) ? BUS_DMA_READ : BUS_DMA_WRITE));
721 if (error) {
722 aprint_error(dmaerrfmt,
723 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
724 "load xfer", drive, error);
725 return error;
726 }
727
728 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
729 dma_maps->dmamap_xfer->dm_mapsize,
730 (flags & WDC_DMA_READ) ?
731 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE);
732
733 for (seg = 0; seg < dma_maps->dmamap_xfer->dm_nsegs; seg++) {
734 bus_addr_t phys = dma_maps->dmamap_xfer->dm_segs[seg].ds_addr;
735 bus_size_t len = dma_maps->dmamap_xfer->dm_segs[seg].ds_len;
736
737 #ifdef DIAGNOSTIC
738 /* A segment must not cross a 64k boundary */
739 {
740 if ((phys & ~IDEDMA_BYTE_COUNT_MASK) !=
741 ((phys + len - 1) & ~IDEDMA_BYTE_COUNT_MASK)) {
742 printf("pciide_dma: seg %d addr 0x%" PRIx64
743 " len 0x%" PRIx64 " not properly aligned\n",
744 seg, (uint64_t)phys, (uint64_t)len);
745 panic("pciide_dma: buf align");
746 }
747 }
748 #endif
749 /*
750 * Some controllers get really upset if the length
751 * of any DMA segment is odd. This isn't something
752 * that's going to happen in normal steady-state
753 * operation (reading VM pages, etc.), but physio users
754 * don't have as many guard rails.
755 *
756 * Consider an 8K read request that starts at an odd
757 * offset within a page. At first blush, all of the
758 * checks pass because it's a sector-rounded size, but
759 * unless the buffer spans 2 physically contiguous pages,
760 * it's going to result in 2 odd-length DMA segments.
761 *
762 * Odd start addresses are also frowned upon, so we
763 * catch those here, too.
764 *
765 * Returning EINVAL here will cause the upper layers to
766 * fall back onto PIO.
767 */
768 if ((phys & 1) != 0 || (len & 1) != 0) {
769 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
770 "Invalid DMA segment: "
771 "seg %d addr 0x%" PRIx64 " len 0x%" PRIx64 "\n",
772 seg, (uint64_t)phys, (uint64_t)len);
773 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
774 return EINVAL;
775 }
776 dma_maps->dma_table[seg].base_addr = htole32(phys);
777 dma_maps->dma_table[seg].byte_count =
778 htole32(len & IDEDMA_BYTE_COUNT_MASK);
779 ATADEBUG_PRINT(("\t seg %d len %d addr 0x%x\n",
780 seg, le32toh(dma_maps->dma_table[seg].byte_count),
781 le32toh(dma_maps->dma_table[seg].base_addr)), DEBUG_DMA);
782
783 }
784 dma_maps->dma_table[dma_maps->dmamap_xfer->dm_nsegs -1].byte_count |=
785 htole32(IDEDMA_BYTE_COUNT_EOT);
786
787 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_table, 0,
788 dma_maps->dmamap_table->dm_mapsize,
789 BUS_DMASYNC_PREWRITE);
790
791 #ifdef DIAGNOSTIC
792 if (dma_maps->dmamap_table->dm_segs[0].ds_addr & ~IDEDMA_TBL_MASK) {
793 printf("pciide_dma_dmamap_setup: addr 0x%lx "
794 "not properly aligned\n",
795 (u_long)dma_maps->dmamap_table->dm_segs[0].ds_addr);
796 panic("pciide_dma_init: table align");
797 }
798 #endif
799 /* remember flags */
800 dma_maps->dma_flags = flags;
801
802 return 0;
803 }
804
805 int
pciide_dma_init(void * v,int channel,int drive,void * databuf,size_t datalen,int flags)806 pciide_dma_init(void *v, int channel, int drive, void *databuf, size_t datalen,
807 int flags)
808 {
809 struct pciide_softc *sc = v;
810 int error;
811 struct pciide_channel *cp = &sc->pciide_channels[channel];
812 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
813
814 if ((error = pciide_dma_dmamap_setup(sc, channel, drive,
815 databuf, datalen, flags)) != 0)
816 return error;
817 /* Maps are ready. Start DMA function */
818 /* Clear status bits */
819 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
820 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
821 /* Write table addr */
822 bus_space_write_4(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_TBL], 0,
823 dma_maps->dmamap_table->dm_segs[0].ds_addr);
824 /* set read/write */
825 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
826 ((flags & WDC_DMA_READ) ? IDEDMA_CMD_WRITE : 0) | cp->idedma_cmd);
827 return 0;
828 }
829
830 void
pciide_dma_start(void * v,int channel,int drive)831 pciide_dma_start(void *v, int channel, int drive)
832 {
833 struct pciide_softc *sc = v;
834 struct pciide_channel *cp = &sc->pciide_channels[channel];
835
836 ATADEBUG_PRINT(("pciide_dma_start\n"),DEBUG_XFERS);
837 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
838 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
839 | IDEDMA_CMD_START);
840 }
841
842 int
pciide_dma_finish(void * v,int channel,int drive,int force)843 pciide_dma_finish(void *v, int channel, int drive, int force)
844 {
845 struct pciide_softc *sc = v;
846 u_int8_t status;
847 int error = 0;
848 struct pciide_channel *cp = &sc->pciide_channels[channel];
849 struct pciide_dma_maps *dma_maps = &cp->dma_maps[drive];
850
851 status = bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0);
852 ATADEBUG_PRINT(("pciide_dma_finish: status 0x%x\n", status),
853 DEBUG_XFERS);
854
855 if (force == WDC_DMAEND_END && (status & IDEDMA_CTL_INTR) == 0)
856 return WDC_DMAST_NOIRQ;
857
858 /* stop DMA channel */
859 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0,
860 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CMD], 0)
861 & ~IDEDMA_CMD_START);
862
863 /* Unload the map of the data buffer */
864 bus_dmamap_sync(sc->sc_dmat, dma_maps->dmamap_xfer, 0,
865 dma_maps->dmamap_xfer->dm_mapsize,
866 (dma_maps->dma_flags & WDC_DMA_READ) ?
867 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
868 bus_dmamap_unload(sc->sc_dmat, dma_maps->dmamap_xfer);
869
870 if ((status & IDEDMA_CTL_ERR) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
871 aprint_error("%s:%d:%d: bus-master DMA error: status=0x%x\n",
872 device_xname(sc->sc_wdcdev.sc_atac.atac_dev), channel,
873 drive, status);
874 error |= WDC_DMAST_ERR;
875 }
876
877 if ((status & IDEDMA_CTL_INTR) == 0 && force != WDC_DMAEND_ABRT_QUIET) {
878 aprint_error("%s:%d:%d: bus-master DMA error: missing "
879 "interrupt, status=0x%x\n",
880 device_xname(sc->sc_wdcdev.sc_atac.atac_dev),
881 channel, drive, status);
882 error |= WDC_DMAST_NOIRQ;
883 }
884
885 if ((status & IDEDMA_CTL_ACT) != 0 && force != WDC_DMAEND_ABRT_QUIET) {
886 /* data underrun, may be a valid condition for ATAPI */
887 error |= WDC_DMAST_UNDER;
888 }
889 return error;
890 }
891
892 void
pciide_irqack(struct ata_channel * chp)893 pciide_irqack(struct ata_channel *chp)
894 {
895 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
896 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
897
898 /* clear status bits in IDE DMA registers */
899 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
900 bus_space_read_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0));
901 }
902 #endif /* NATA_DMA */
903
904 /* some common code used by several chip_map */
905 int
pciide_chansetup(struct pciide_softc * sc,int channel,pcireg_t interface)906 pciide_chansetup(struct pciide_softc *sc, int channel, pcireg_t interface)
907 {
908 struct pciide_channel *cp = &sc->pciide_channels[channel];
909 sc->wdc_chanarray[channel] = &cp->ata_channel;
910 cp->name = PCIIDE_CHANNEL_NAME(channel);
911 cp->ata_channel.ch_channel = channel;
912 cp->ata_channel.ch_atac = &sc->sc_wdcdev.sc_atac;
913
914 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
915 "%s channel %s to %s mode\n", cp->name,
916 (interface & PCIIDE_INTERFACE_SETTABLE(channel)) ?
917 "configured" : "wired",
918 (interface & PCIIDE_INTERFACE_PCI(channel)) ?
919 "native-PCI" : "compatibility");
920 return 1;
921 }
922
923 /* some common code used by several chip channel_map */
924 void
pciide_mapchan(const struct pci_attach_args * pa,struct pciide_channel * cp,pcireg_t interface,int (* pci_intr)(void *))925 pciide_mapchan(const struct pci_attach_args *pa, struct pciide_channel *cp,
926 pcireg_t interface, int (*pci_intr)(void *))
927 {
928 struct ata_channel *wdc_cp = &cp->ata_channel;
929
930 if (interface & PCIIDE_INTERFACE_PCI(wdc_cp->ch_channel))
931 pciide_mapregs_native(pa, cp, pci_intr);
932 else {
933 pciide_mapregs_compat(pa, cp, wdc_cp->ch_channel);
934 if ((cp->ata_channel.ch_flags & ATACH_DISABLED) == 0)
935 pciide_map_compat_intr(pa, cp, wdc_cp->ch_channel);
936 }
937 wdcattach(wdc_cp);
938 }
939
940 /*
941 * generic code to map the compat intr.
942 */
943 void
pciide_map_compat_intr(const struct pci_attach_args * pa,struct pciide_channel * cp,int compatchan)944 pciide_map_compat_intr(const struct pci_attach_args *pa,
945 struct pciide_channel *cp, int compatchan)
946 {
947 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
948
949 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
950 cp->ih =
951 pciide_machdep_compat_intr_establish(sc->sc_wdcdev.sc_atac.atac_dev,
952 pa, compatchan, pciide_compat_intr, cp);
953 if (cp->ih == NULL) {
954 #endif
955 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
956 "no compatibility interrupt for use by %s "
957 "channel\n", cp->name);
958 cp->ata_channel.ch_flags |= ATACH_DISABLED;
959 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_ESTABLISH
960 }
961 #endif
962 }
963
964 void
pciide_unmap_compat_intr(pci_chipset_tag_t pc,struct pciide_channel * cp,int compatchan)965 pciide_unmap_compat_intr(pci_chipset_tag_t pc, struct pciide_channel *cp,
966 int compatchan)
967 {
968 #ifdef __HAVE_PCIIDE_MACHDEP_COMPAT_INTR_DISESTABLISH
969 struct pciide_softc *sc = CHAN_TO_PCIIDE(&cp->ata_channel);
970
971 pciide_machdep_compat_intr_disestablish(sc->sc_wdcdev.sc_atac.atac_dev,
972 sc->sc_pc, compatchan, cp->ih);
973 #endif
974 }
975
976 void
default_chip_map(struct pciide_softc * sc,const struct pci_attach_args * pa)977 default_chip_map(struct pciide_softc *sc, const struct pci_attach_args *pa)
978 {
979 struct pciide_channel *cp;
980 pcireg_t interface = PCI_INTERFACE(pa->pa_class);
981 pcireg_t csr;
982 int channel;
983 #if NATA_DMA
984 int drive;
985 u_int8_t idedma_ctl;
986 #endif
987 const char *failreason;
988 struct wdc_regs *wdr;
989
990 if (pciide_chipen(sc, pa) == 0)
991 return;
992
993 if (interface & PCIIDE_INTERFACE_BUS_MASTER_DMA) {
994 #if NATA_DMA
995 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
996 "bus-master DMA support present");
997 if (sc->sc_pp == &default_product_desc &&
998 (device_cfdata(sc->sc_wdcdev.sc_atac.atac_dev)->cf_flags &
999 PCIIDE_OPTIONS_DMA) == 0) {
1000 aprint_verbose(", but unused (no driver support)");
1001 sc->sc_dma_ok = 0;
1002 } else {
1003 pciide_mapreg_dma(sc, pa);
1004 if (sc->sc_dma_ok != 0)
1005 aprint_verbose(", used without full driver "
1006 "support");
1007 }
1008 #else
1009 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1010 "bus-master DMA support present, but unused (no driver "
1011 "support)");
1012 #endif /* NATA_DMA */
1013 } else {
1014 aprint_verbose_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1015 "hardware does not support DMA");
1016 #if NATA_DMA
1017 sc->sc_dma_ok = 0;
1018 #endif
1019 }
1020 aprint_verbose("\n");
1021 #if NATA_DMA
1022 if (sc->sc_dma_ok) {
1023 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DMA;
1024 sc->sc_wdcdev.irqack = pciide_irqack;
1025 }
1026 #endif
1027 sc->sc_wdcdev.sc_atac.atac_pio_cap = 0;
1028 #if NATA_DMA
1029 sc->sc_wdcdev.sc_atac.atac_dma_cap = 0;
1030 #endif
1031
1032 sc->sc_wdcdev.sc_atac.atac_channels = sc->wdc_chanarray;
1033 sc->sc_wdcdev.sc_atac.atac_nchannels = PCIIDE_NUM_CHANNELS;
1034 sc->sc_wdcdev.sc_atac.atac_cap |= ATAC_CAP_DATA16;
1035 sc->sc_wdcdev.wdc_maxdrives = 2;
1036
1037 wdc_allocate_regs(&sc->sc_wdcdev);
1038
1039 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1040 channel++) {
1041 cp = &sc->pciide_channels[channel];
1042 if (pciide_chansetup(sc, channel, interface) == 0)
1043 continue;
1044 wdr = CHAN_TO_WDC_REGS(&cp->ata_channel);
1045 if (interface & PCIIDE_INTERFACE_PCI(channel))
1046 pciide_mapregs_native(pa, cp, pciide_pci_intr);
1047 else
1048 pciide_mapregs_compat(pa, cp,
1049 cp->ata_channel.ch_channel);
1050 if (cp->ata_channel.ch_flags & ATACH_DISABLED)
1051 continue;
1052 /*
1053 * Check to see if something appears to be there.
1054 */
1055 failreason = NULL;
1056 /*
1057 * In native mode, always enable the controller. It's
1058 * not possible to have an ISA board using the same address
1059 * anyway.
1060 */
1061 if (interface & PCIIDE_INTERFACE_PCI(channel)) {
1062 wdcattach(&cp->ata_channel);
1063 continue;
1064 }
1065 if (!wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel))) {
1066 failreason = "not responding; disabled or no drives?";
1067 goto next;
1068 }
1069 /*
1070 * Now, make sure it's actually attributable to this PCI IDE
1071 * channel by trying to access the channel again while the
1072 * PCI IDE controller's I/O space is disabled. (If the
1073 * channel no longer appears to be there, it belongs to
1074 * this controller.) YUCK!
1075 */
1076 csr = pci_conf_read(sc->sc_pc, sc->sc_tag,
1077 PCI_COMMAND_STATUS_REG);
1078 pci_conf_write(sc->sc_pc, sc->sc_tag, PCI_COMMAND_STATUS_REG,
1079 csr & ~PCI_COMMAND_IO_ENABLE);
1080 if (wdcprobe(CHAN_TO_WDC_REGS(&cp->ata_channel)))
1081 failreason = "other hardware responding at addresses";
1082 pci_conf_write(sc->sc_pc, sc->sc_tag,
1083 PCI_COMMAND_STATUS_REG, csr);
1084 next:
1085 if (failreason) {
1086 aprint_error_dev(sc->sc_wdcdev.sc_atac.atac_dev,
1087 "%s channel ignored (%s)\n", cp->name, failreason);
1088 cp->ata_channel.ch_flags |= ATACH_DISABLED;
1089 bus_space_unmap(wdr->cmd_iot, wdr->cmd_baseioh,
1090 wdr->cmd_ios);
1091 bus_space_unmap(wdr->ctl_iot, wdr->ctl_ioh,
1092 wdr->ctl_ios);
1093 } else {
1094 pciide_map_compat_intr(pa, cp,
1095 cp->ata_channel.ch_channel);
1096 wdcattach(&cp->ata_channel);
1097 }
1098 }
1099
1100 #if NATA_DMA
1101 if (sc->sc_dma_ok == 0)
1102 return;
1103
1104 /* Allocate DMA maps */
1105 for (channel = 0; channel < sc->sc_wdcdev.sc_atac.atac_nchannels;
1106 channel++) {
1107 idedma_ctl = 0;
1108 cp = &sc->pciide_channels[channel];
1109 for (drive = 0; drive < sc->sc_wdcdev.wdc_maxdrives; drive++) {
1110 /*
1111 * we have not probed the drives yet, allocate
1112 * resources for all of them.
1113 */
1114 if (pciide_dma_table_setup(sc, channel, drive) != 0) {
1115 /* Abort DMA setup */
1116 aprint_error(
1117 "%s:%d:%d: can't allocate DMA maps, "
1118 "using PIO transfers\n",
1119 device_xname(
1120 sc->sc_wdcdev.sc_atac.atac_dev),
1121 channel, drive);
1122 sc->sc_dma_ok = 0;
1123 sc->sc_wdcdev.sc_atac.atac_cap &= ~ATAC_CAP_DMA;
1124 sc->sc_wdcdev.irqack = NULL;
1125 break;
1126 }
1127 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1128 }
1129 if (idedma_ctl != 0) {
1130 /* Add software bits in status register */
1131 bus_space_write_1(sc->sc_dma_iot,
1132 cp->dma_iohs[IDEDMA_CTL], 0, idedma_ctl);
1133 }
1134 }
1135 #endif /* NATA_DMA */
1136 }
1137
1138 void
sata_setup_channel(struct ata_channel * chp)1139 sata_setup_channel(struct ata_channel *chp)
1140 {
1141 #if NATA_DMA
1142 struct ata_drive_datas *drvp;
1143 int drive;
1144 #if NATA_UDMA
1145 int s;
1146 #endif
1147 u_int32_t idedma_ctl;
1148 struct pciide_channel *cp = CHAN_TO_PCHAN(chp);
1149 struct pciide_softc *sc = CHAN_TO_PCIIDE(chp);
1150
1151 /* setup DMA if needed */
1152 pciide_channel_dma_setup(cp);
1153
1154 idedma_ctl = 0;
1155
1156 KASSERT(cp->ata_channel.ch_ndrives != 0);
1157 for (drive = 0; drive < cp->ata_channel.ch_ndrives; drive++) {
1158 drvp = &chp->ch_drive[drive];
1159 /* If no drive, skip */
1160 if (drvp->drive_type == ATA_DRIVET_NONE)
1161 continue;
1162 #if NATA_UDMA
1163 if (drvp->drive_flags & ATA_DRIVE_UDMA) {
1164 /* use Ultra/DMA */
1165 s = splbio();
1166 drvp->drive_flags &= ~ATA_DRIVE_DMA;
1167 splx(s);
1168 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1169 } else
1170 #endif /* NATA_UDMA */
1171 if (drvp->drive_flags & ATA_DRIVE_DMA) {
1172 idedma_ctl |= IDEDMA_CTL_DRV_DMA(drive);
1173 }
1174 }
1175
1176 /*
1177 * Nothing to do to setup modes; it is meaningless in S-ATA
1178 * (but many S-ATA drives still want to get the SET_FEATURE
1179 * command).
1180 */
1181 if (idedma_ctl != 0) {
1182 /* Add software bits in status register */
1183 bus_space_write_1(sc->sc_dma_iot, cp->dma_iohs[IDEDMA_CTL], 0,
1184 idedma_ctl);
1185 }
1186 #endif /* NATA_DMA */
1187 }
1188