1 /* $NetBSD: nvmm_ioctl.h,v 1.12 2020/09/08 16:58:38 maxv Exp $ */ 2 3 /* 4 * Copyright (c) 2018-2020 Maxime Villard, m00nbsd.net 5 * All rights reserved. 6 * 7 * This code is part of the NVMM hypervisor. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 24 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef _NVMM_IOCTL_H_ 32 #define _NVMM_IOCTL_H_ 33 34 #include <sys/ioccom.h> 35 #include <dev/nvmm/nvmm.h> 36 37 struct nvmm_ioc_capability { 38 struct nvmm_capability cap; 39 }; 40 41 struct nvmm_ioc_machine_create { 42 nvmm_machid_t machid; 43 }; 44 45 struct nvmm_ioc_machine_destroy { 46 nvmm_machid_t machid; 47 }; 48 49 struct nvmm_ioc_machine_configure { 50 nvmm_machid_t machid; 51 uint64_t op; 52 void *conf; 53 }; 54 55 struct nvmm_ioc_vcpu_create { 56 nvmm_machid_t machid; 57 nvmm_cpuid_t cpuid; 58 }; 59 60 struct nvmm_ioc_vcpu_destroy { 61 nvmm_machid_t machid; 62 nvmm_cpuid_t cpuid; 63 }; 64 65 struct nvmm_ioc_vcpu_configure { 66 nvmm_machid_t machid; 67 nvmm_cpuid_t cpuid; 68 uint64_t op; 69 void *conf; 70 }; 71 72 struct nvmm_ioc_vcpu_setstate { 73 nvmm_machid_t machid; 74 nvmm_cpuid_t cpuid; 75 }; 76 77 struct nvmm_ioc_vcpu_getstate { 78 nvmm_machid_t machid; 79 nvmm_cpuid_t cpuid; 80 }; 81 82 struct nvmm_ioc_vcpu_inject { 83 nvmm_machid_t machid; 84 nvmm_cpuid_t cpuid; 85 }; 86 87 struct nvmm_ioc_vcpu_run { 88 /* input */ 89 nvmm_machid_t machid; 90 nvmm_cpuid_t cpuid; 91 /* output */ 92 struct nvmm_vcpu_exit exit; 93 }; 94 95 struct nvmm_ioc_hva_map { 96 nvmm_machid_t machid; 97 uintptr_t hva; 98 size_t size; 99 int flags; 100 }; 101 102 struct nvmm_ioc_hva_unmap { 103 nvmm_machid_t machid; 104 uintptr_t hva; 105 size_t size; 106 int flags; 107 }; 108 109 struct nvmm_ioc_gpa_map { 110 nvmm_machid_t machid; 111 uintptr_t hva; 112 gpaddr_t gpa; 113 size_t size; 114 int prot; 115 }; 116 117 struct nvmm_ioc_gpa_unmap { 118 nvmm_machid_t machid; 119 gpaddr_t gpa; 120 size_t size; 121 }; 122 123 struct nvmm_ctl_mach_info { 124 /* input */ 125 nvmm_machid_t machid; 126 /* output */ 127 uint32_t nvcpus; 128 uint64_t nram; 129 pid_t pid; 130 time_t time; 131 }; 132 133 struct nvmm_ioc_ctl { 134 int op; 135 #define NVMM_CTL_MACH_INFO 0 136 137 void *data; 138 size_t size; 139 }; 140 141 #define NVMM_IOC_CAPABILITY _IOR ('N', 0, struct nvmm_ioc_capability) 142 #define NVMM_IOC_MACHINE_CREATE _IOWR('N', 1, struct nvmm_ioc_machine_create) 143 #define NVMM_IOC_MACHINE_DESTROY _IOW ('N', 2, struct nvmm_ioc_machine_destroy) 144 #define NVMM_IOC_MACHINE_CONFIGURE _IOW ('N', 3, struct nvmm_ioc_machine_configure) 145 #define NVMM_IOC_VCPU_CREATE _IOW ('N', 4, struct nvmm_ioc_vcpu_create) 146 #define NVMM_IOC_VCPU_DESTROY _IOW ('N', 5, struct nvmm_ioc_vcpu_destroy) 147 #define NVMM_IOC_VCPU_CONFIGURE _IOW ('N', 6, struct nvmm_ioc_vcpu_configure) 148 #define NVMM_IOC_VCPU_SETSTATE _IOW ('N', 7, struct nvmm_ioc_vcpu_setstate) 149 #define NVMM_IOC_VCPU_GETSTATE _IOW ('N', 8, struct nvmm_ioc_vcpu_getstate) 150 #define NVMM_IOC_VCPU_INJECT _IOW ('N', 9, struct nvmm_ioc_vcpu_inject) 151 #define NVMM_IOC_VCPU_RUN _IOWR('N', 10, struct nvmm_ioc_vcpu_run) 152 #define NVMM_IOC_GPA_MAP _IOW ('N', 11, struct nvmm_ioc_gpa_map) 153 #define NVMM_IOC_GPA_UNMAP _IOW ('N', 12, struct nvmm_ioc_gpa_unmap) 154 #define NVMM_IOC_HVA_MAP _IOW ('N', 13, struct nvmm_ioc_hva_map) 155 #define NVMM_IOC_HVA_UNMAP _IOW ('N', 14, struct nvmm_ioc_hva_unmap) 156 #define NVMM_IOC_CTL _IOW ('N', 20, struct nvmm_ioc_ctl) 157 158 #endif /* _NVMM_IOCTL_H_ */ 159