1 /* $NetBSD: clmpcc.c,v 1.31 2006/10/01 20:31:50 elad Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 /* 40 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller. 41 */ 42 43 #include <sys/cdefs.h> 44 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.31 2006/10/01 20:31:50 elad Exp $"); 45 46 #include "opt_ddb.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/ioctl.h> 51 #include <sys/select.h> 52 #include <sys/tty.h> 53 #include <sys/proc.h> 54 #include <sys/user.h> 55 #include <sys/conf.h> 56 #include <sys/file.h> 57 #include <sys/uio.h> 58 #include <sys/kernel.h> 59 #include <sys/syslog.h> 60 #include <sys/device.h> 61 #include <sys/malloc.h> 62 #include <sys/kauth.h> 63 64 #include <machine/bus.h> 65 #include <machine/intr.h> 66 #include <machine/param.h> 67 68 #include <dev/ic/clmpccreg.h> 69 #include <dev/ic/clmpccvar.h> 70 #include <dev/cons.h> 71 72 73 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH) 74 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive." 75 #endif 76 77 78 static int clmpcc_init(struct clmpcc_softc *sc); 79 static void clmpcc_shutdown(struct clmpcc_chan *); 80 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *); 81 static int clmpcc_param(struct tty *, struct termios *); 82 static void clmpcc_set_params(struct clmpcc_chan *); 83 static void clmpcc_start(struct tty *); 84 static int clmpcc_modem_control(struct clmpcc_chan *, int, int); 85 86 #define CLMPCCUNIT(x) (minor(x) & 0x7fffc) 87 #define CLMPCCCHAN(x) (minor(x) & 0x00003) 88 #define CLMPCCDIALOUT(x) (minor(x) & 0x80000) 89 90 /* 91 * These should be in a header file somewhere... 92 */ 93 #define ISCLR(v, f) (((v) & (f)) == 0) 94 95 extern struct cfdriver clmpcc_cd; 96 97 dev_type_open(clmpccopen); 98 dev_type_close(clmpccclose); 99 dev_type_read(clmpccread); 100 dev_type_write(clmpccwrite); 101 dev_type_ioctl(clmpccioctl); 102 dev_type_stop(clmpccstop); 103 dev_type_tty(clmpcctty); 104 dev_type_poll(clmpccpoll); 105 106 const struct cdevsw clmpcc_cdevsw = { 107 clmpccopen, clmpccclose, clmpccread, clmpccwrite, clmpccioctl, 108 clmpccstop, clmpcctty, clmpccpoll, nommap, ttykqfilter, D_TTY 109 }; 110 111 /* 112 * Make this an option variable one can patch. 113 */ 114 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE; 115 116 117 /* 118 * Things needed when the device is used as a console 119 */ 120 static struct clmpcc_softc *cons_sc = NULL; 121 static int cons_chan; 122 static int cons_rate; 123 124 static int clmpcc_common_getc(struct clmpcc_softc *, int); 125 static void clmpcc_common_putc(struct clmpcc_softc *, int, int); 126 int clmpcccngetc(dev_t); 127 void clmpcccnputc(dev_t, int); 128 129 130 /* 131 * Convenience functions, inlined for speed 132 */ 133 #define integrate static inline 134 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int); 135 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int); 136 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int); 137 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int); 138 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *, 139 u_int); 140 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int); 141 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int); 142 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *); 143 144 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR) 145 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v) 146 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v) 147 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR) 148 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v) 149 150 151 integrate u_int8_t 152 clmpcc_rdreg(sc, offset) 153 struct clmpcc_softc *sc; 154 u_int offset; 155 { 156 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 157 offset ^= sc->sc_byteswap; 158 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 159 offset ^= CLMPCC_BYTESWAP_HIGH; 160 #endif 161 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 162 } 163 164 integrate void 165 clmpcc_wrreg(sc, offset, val) 166 struct clmpcc_softc *sc; 167 u_int offset; 168 u_int val; 169 { 170 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 171 offset ^= sc->sc_byteswap; 172 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 173 offset ^= CLMPCC_BYTESWAP_HIGH; 174 #endif 175 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 176 } 177 178 integrate u_int8_t 179 clmpcc_rdreg_odd(sc, offset) 180 struct clmpcc_softc *sc; 181 u_int offset; 182 { 183 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 184 offset ^= (sc->sc_byteswap & 2); 185 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 186 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 187 #endif 188 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset); 189 } 190 191 integrate void 192 clmpcc_wrreg_odd(sc, offset, val) 193 struct clmpcc_softc *sc; 194 u_int offset; 195 u_int val; 196 { 197 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 198 offset ^= (sc->sc_byteswap & 2); 199 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 200 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 201 #endif 202 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val); 203 } 204 205 integrate void 206 clmpcc_wrtx_multi(sc, buff, count) 207 struct clmpcc_softc *sc; 208 u_int8_t *buff; 209 u_int count; 210 { 211 u_int offset = CLMPCC_REG_TDR; 212 213 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH) 214 offset ^= (sc->sc_byteswap & 2); 215 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH) 216 offset ^= (CLMPCC_BYTESWAP_HIGH & 2); 217 #endif 218 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count); 219 } 220 221 integrate u_int8_t 222 clmpcc_select_channel(sc, new_chan) 223 struct clmpcc_softc *sc; 224 u_int new_chan; 225 { 226 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR); 227 228 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan); 229 230 return old_chan; 231 } 232 233 integrate void 234 clmpcc_channel_cmd(sc, chan, cmd) 235 struct clmpcc_softc *sc; 236 int chan; 237 int cmd; 238 { 239 int i; 240 241 for (i = 5000; i; i--) { 242 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 ) 243 break; 244 delay(1); 245 } 246 247 if ( i == 0 ) 248 printf("%s: channel %d command timeout (idle)\n", 249 sc->sc_dev.dv_xname, chan); 250 251 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd); 252 } 253 254 integrate void 255 clmpcc_enable_transmitter(ch) 256 struct clmpcc_chan *ch; 257 { 258 u_int old; 259 int s; 260 261 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 262 263 s = splserial(); 264 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 265 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY); 266 SET(ch->ch_tty->t_state, TS_BUSY); 267 splx(s); 268 269 clmpcc_select_channel(ch->ch_sc, old); 270 } 271 272 static int 273 clmpcc_speed(sc, speed, cor, bpr) 274 struct clmpcc_softc *sc; 275 speed_t speed; 276 int *cor, *bpr; 277 { 278 int c, co, br; 279 280 for (co = 0, c = 8; c <= 2048; co++, c *= 4) { 281 br = ((sc->sc_clk / c) / speed) - 1; 282 if ( br < 0x100 ) { 283 *cor = co; 284 *bpr = br; 285 return 0; 286 } 287 } 288 289 return -1; 290 } 291 292 void 293 clmpcc_attach(sc) 294 struct clmpcc_softc *sc; 295 { 296 struct clmpcc_chan *ch; 297 struct tty *tp; 298 int chan; 299 300 if ( cons_sc != NULL && 301 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh ) 302 cons_sc = sc; 303 304 /* Initialise the chip */ 305 clmpcc_init(sc); 306 307 printf(": Cirrus Logic CD240%c Serial Controller\n", 308 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1'); 309 310 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 311 sc->sc_soft_running = 0; 312 #else 313 sc->sc_softintr_cookie = 314 softintr_establish(IPL_SOFTSERIAL, clmpcc_softintr, sc); 315 #ifdef DEBUG 316 if (sc->sc_softintr_cookie == NULL) 317 panic("clmpcc_attach: softintr_establish"); 318 #endif 319 #endif 320 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans)); 321 322 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 323 ch = &sc->sc_chans[chan]; 324 325 ch->ch_sc = sc; 326 ch->ch_car = chan; 327 328 tp = ttymalloc(); 329 tp->t_oproc = clmpcc_start; 330 tp->t_param = clmpcc_param; 331 332 ch->ch_tty = tp; 333 334 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_NOWAIT); 335 if ( ch->ch_ibuf == NULL ) { 336 printf("%s(%d): unable to allocate ring buffer\n", 337 sc->sc_dev.dv_xname, chan); 338 return; 339 } 340 341 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]); 342 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 343 344 tty_attach(tp); 345 } 346 347 printf("%s: %d channels available", sc->sc_dev.dv_xname, 348 CLMPCC_NUM_CHANS); 349 if ( cons_sc == sc ) { 350 printf(", console on channel %d.\n", cons_chan); 351 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE); 352 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR); 353 } else 354 printf(".\n"); 355 } 356 357 static int 358 clmpcc_init(sc) 359 struct clmpcc_softc *sc; 360 { 361 u_int tcor, tbpr; 362 u_int rcor, rbpr; 363 u_int msvr_rts, msvr_dtr; 364 u_int ccr; 365 int is_console; 366 int i; 367 368 /* 369 * All we're really concerned about here is putting the chip 370 * into a quiescent state so that it won't do anything until 371 * clmpccopen() is called. (Except the console channel.) 372 */ 373 374 /* 375 * If the chip is acting as console, set all channels to the supplied 376 * console baud rate. Otherwise, plump for 9600. 377 */ 378 if ( cons_sc && 379 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) { 380 clmpcc_speed(sc, cons_rate, &tcor, &tbpr); 381 clmpcc_speed(sc, cons_rate, &rcor, &rbpr); 382 is_console = 1; 383 } else { 384 clmpcc_speed(sc, 9600, &tcor, &tbpr); 385 clmpcc_speed(sc, 9600, &rcor, &rbpr); 386 is_console = 0; 387 } 388 389 /* Allow any pending output to be sent */ 390 delay(10000); 391 392 /* Send the Reset All command to channel 0 (resets all channels!) */ 393 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL); 394 395 delay(1000); 396 397 /* 398 * The chip will set it's firmware revision register to a non-zero 399 * value to indicate completion of reset. 400 */ 401 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--) 402 delay(1); 403 404 if ( i == 0 ) { 405 /* 406 * Watch out... If this chip is console, the message 407 * probably won't be sent since we just reset it! 408 */ 409 printf("%s: Failed to reset chip\n", sc->sc_dev.dv_xname); 410 return -1; 411 } 412 413 for (i = 0; i < CLMPCC_NUM_CHANS; i++) { 414 clmpcc_select_channel(sc, i); 415 416 /* All interrupts are disabled to begin with */ 417 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0); 418 419 /* Make sure the channel interrupts on the correct vectors */ 420 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base); 421 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr); 422 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr); 423 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr); 424 425 /* Receive timer prescaler set to 1ms */ 426 clmpcc_wrreg(sc, CLMPCC_REG_TPR, 427 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1)); 428 429 /* We support Async mode only */ 430 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC); 431 432 /* Set the required baud rate */ 433 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor)); 434 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr); 435 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor)); 436 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr); 437 438 /* Always default to 8N1 (XXX what about console?) */ 439 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS | 440 CLMPCC_COR1_NO_PARITY | 441 CLMPCC_COR1_IGNORE_PAR); 442 443 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0); 444 445 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1); 446 447 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd | 448 CLMPCC_COR4_CDzd | 449 CLMPCC_COR4_CTSzd); 450 451 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod | 452 CLMPCC_COR5_CDod | 453 CLMPCC_COR5_CTSod | 454 CLMPCC_COR5_FLOW_NORM); 455 456 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0); 457 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0); 458 459 /* Set the receive FIFO timeout */ 460 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT); 461 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0); 462 463 /* At this point, we set up the console differently */ 464 if ( is_console && i == cons_chan ) { 465 msvr_rts = CLMPCC_MSVR_RTS; 466 msvr_dtr = CLMPCC_MSVR_DTR; 467 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN; 468 } else { 469 msvr_rts = 0; 470 msvr_dtr = 0; 471 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS; 472 } 473 474 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts); 475 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr); 476 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr); 477 delay(100); 478 } 479 480 return 0; 481 } 482 483 static void 484 clmpcc_shutdown(ch) 485 struct clmpcc_chan *ch; 486 { 487 int oldch; 488 489 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 490 491 /* Turn off interrupts. */ 492 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0); 493 494 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 495 /* Disable the transmitter and receiver */ 496 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS | 497 CLMPCC_CCR_T0_TX_DIS); 498 499 /* Drop RTS and DTR */ 500 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 501 } 502 503 clmpcc_select_channel(ch->ch_sc, oldch); 504 } 505 506 int 507 clmpccopen(dev, flag, mode, l) 508 dev_t dev; 509 int flag, mode; 510 struct lwp *l; 511 { 512 struct clmpcc_softc *sc; 513 struct clmpcc_chan *ch; 514 struct tty *tp; 515 int oldch; 516 int error; 517 518 sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 519 if (sc == NULL) 520 return (ENXIO); 521 522 ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 523 524 tp = ch->ch_tty; 525 526 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp)) 527 return EBUSY; 528 529 /* 530 * Do the following iff this is a first open. 531 */ 532 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 533 534 ttychars(tp); 535 536 tp->t_dev = dev; 537 tp->t_iflag = TTYDEF_IFLAG; 538 tp->t_oflag = TTYDEF_OFLAG; 539 tp->t_lflag = TTYDEF_LFLAG; 540 tp->t_cflag = TTYDEF_CFLAG; 541 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED; 542 543 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) ) 544 SET(tp->t_cflag, CLOCAL); 545 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) ) 546 SET(tp->t_cflag, CRTSCTS); 547 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) ) 548 SET(tp->t_cflag, MDMBUF); 549 550 /* 551 * Override some settings if the channel is being 552 * used as the console. 553 */ 554 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 555 tp->t_ospeed = tp->t_ispeed = cons_rate; 556 SET(tp->t_cflag, CLOCAL); 557 CLR(tp->t_cflag, CRTSCTS); 558 CLR(tp->t_cflag, HUPCL); 559 } 560 561 ch->ch_control = 0; 562 563 clmpcc_param(tp, &tp->t_termios); 564 ttsetwater(tp); 565 566 /* Clear the input ring */ 567 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf; 568 569 /* Select the channel */ 570 oldch = clmpcc_select_channel(sc, ch->ch_car); 571 572 /* Reset it */ 573 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR | 574 CLMPCC_CCR_T0_RX_EN | 575 CLMPCC_CCR_T0_TX_EN); 576 577 /* Enable receiver and modem change interrupts. */ 578 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM | 579 CLMPCC_IER_RET | 580 CLMPCC_IER_RX_FIFO); 581 582 /* Raise RTS and DTR */ 583 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS); 584 585 clmpcc_select_channel(sc, oldch); 586 } 587 588 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK)); 589 if (error) 590 goto bad; 591 592 error = (*tp->t_linesw->l_open)(dev, tp); 593 if (error) 594 goto bad; 595 596 return 0; 597 598 bad: 599 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 600 /* 601 * We failed to open the device, and nobody else had it opened. 602 * Clean up the state as appropriate. 603 */ 604 clmpcc_shutdown(ch); 605 } 606 607 return error; 608 } 609 610 int 611 clmpccclose(dev, flag, mode, l) 612 dev_t dev; 613 int flag, mode; 614 struct lwp *l; 615 { 616 struct clmpcc_softc *sc = 617 device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 618 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 619 struct tty *tp = ch->ch_tty; 620 int s; 621 622 if ( ISCLR(tp->t_state, TS_ISOPEN) ) 623 return 0; 624 625 (*tp->t_linesw->l_close)(tp, flag); 626 627 s = spltty(); 628 629 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) { 630 /* 631 * Although we got a last close, the device may still be in 632 * use; e.g. if this was the dialout node, and there are still 633 * processes waiting for carrier on the non-dialout node. 634 */ 635 clmpcc_shutdown(ch); 636 } 637 638 ttyclose(tp); 639 640 splx(s); 641 642 return 0; 643 } 644 645 int 646 clmpccread(dev, uio, flag) 647 dev_t dev; 648 struct uio *uio; 649 int flag; 650 { 651 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 652 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 653 654 return ((*tp->t_linesw->l_read)(tp, uio, flag)); 655 } 656 657 int 658 clmpccwrite(dev, uio, flag) 659 dev_t dev; 660 struct uio *uio; 661 int flag; 662 { 663 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 664 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 665 666 return ((*tp->t_linesw->l_write)(tp, uio, flag)); 667 } 668 669 int 670 clmpccpoll(dev, events, l) 671 dev_t dev; 672 int events; 673 struct lwp *l; 674 { 675 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 676 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty; 677 678 return ((*tp->t_linesw->l_poll)(tp, events, l)); 679 } 680 681 struct tty * 682 clmpcctty(dev) 683 dev_t dev; 684 { 685 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 686 687 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty); 688 } 689 690 int 691 clmpccioctl(dev, cmd, data, flag, l) 692 dev_t dev; 693 u_long cmd; 694 caddr_t data; 695 int flag; 696 struct lwp *l; 697 { 698 struct clmpcc_softc *sc = device_lookup(&clmpcc_cd, CLMPCCUNIT(dev)); 699 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)]; 700 struct tty *tp = ch->ch_tty; 701 int error; 702 703 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l); 704 if (error != EPASSTHROUGH) 705 return error; 706 707 error = ttioctl(tp, cmd, data, flag, l); 708 if (error != EPASSTHROUGH) 709 return error; 710 711 error = 0; 712 713 switch (cmd) { 714 case TIOCSBRK: 715 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK); 716 clmpcc_enable_transmitter(ch); 717 break; 718 719 case TIOCCBRK: 720 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK); 721 clmpcc_enable_transmitter(ch); 722 break; 723 724 case TIOCSDTR: 725 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS); 726 break; 727 728 case TIOCCDTR: 729 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC); 730 break; 731 732 case TIOCMSET: 733 clmpcc_modem_control(ch, *((int *)data), DMSET); 734 break; 735 736 case TIOCMBIS: 737 clmpcc_modem_control(ch, *((int *)data), DMBIS); 738 break; 739 740 case TIOCMBIC: 741 clmpcc_modem_control(ch, *((int *)data), DMBIC); 742 break; 743 744 case TIOCMGET: 745 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET); 746 break; 747 748 case TIOCGFLAGS: 749 *((int *)data) = ch->ch_openflags; 750 break; 751 752 case TIOCSFLAGS: 753 error = kauth_authorize_device_tty(l->l_cred, 754 KAUTH_DEVICE_TTY_PRIVSET, tp); 755 if ( error ) 756 break; 757 ch->ch_openflags = *((int *)data) & 758 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL | 759 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF); 760 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) 761 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR); 762 break; 763 764 default: 765 error = EPASSTHROUGH; 766 break; 767 } 768 769 return error; 770 } 771 772 int 773 clmpcc_modem_control(ch, bits, howto) 774 struct clmpcc_chan *ch; 775 int bits; 776 int howto; 777 { 778 struct clmpcc_softc *sc = ch->ch_sc; 779 struct tty *tp = ch->ch_tty; 780 int oldch; 781 int msvr; 782 int rbits = 0; 783 784 oldch = clmpcc_select_channel(sc, ch->ch_car); 785 786 switch ( howto ) { 787 case DMGET: 788 msvr = clmpcc_rd_msvr(sc); 789 790 if ( sc->sc_swaprtsdtr ) { 791 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0; 792 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0; 793 } else { 794 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0; 795 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0; 796 } 797 798 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0; 799 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0; 800 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0; 801 break; 802 803 case DMSET: 804 if ( sc->sc_swaprtsdtr ) { 805 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 806 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 807 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0); 808 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 809 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0); 810 } else { 811 if ( ISCLR(tp->t_cflag, CRTSCTS) ) 812 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 813 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0); 814 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 815 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0); 816 } 817 break; 818 819 case DMBIS: 820 if ( sc->sc_swaprtsdtr ) { 821 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 822 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 823 if ( ISSET(bits, TIOCM_DTR) ) 824 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 825 } else { 826 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) ) 827 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS); 828 if ( ISSET(bits, TIOCM_DTR) ) 829 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR); 830 } 831 break; 832 833 case DMBIC: 834 if ( sc->sc_swaprtsdtr ) { 835 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 836 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 837 if ( ISCLR(bits, TIOCM_DTR) ) 838 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 839 } else { 840 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) ) 841 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0); 842 if ( ISCLR(bits, TIOCM_DTR) ) 843 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0); 844 } 845 break; 846 } 847 848 clmpcc_select_channel(sc, oldch); 849 850 return rbits; 851 } 852 853 static int 854 clmpcc_param(tp, t) 855 struct tty *tp; 856 struct termios *t; 857 { 858 struct clmpcc_softc *sc = 859 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 860 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 861 u_char cor; 862 u_char oldch; 863 int oclk, obpr; 864 int iclk, ibpr; 865 int s; 866 867 /* Check requested parameters. */ 868 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 ) 869 return EINVAL; 870 871 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 ) 872 return EINVAL; 873 874 /* 875 * For the console, always force CLOCAL and !HUPCL, so that the port 876 * is always active. 877 */ 878 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) || 879 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) { 880 SET(t->c_cflag, CLOCAL); 881 CLR(t->c_cflag, HUPCL); 882 } 883 884 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 885 886 /* If ospeed it zero, hangup the line */ 887 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS); 888 889 if ( t->c_ospeed ) { 890 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk); 891 ch->ch_tbpr = obpr; 892 } else { 893 ch->ch_tcor = 0; 894 ch->ch_tbpr = 0; 895 } 896 897 if ( t->c_ispeed ) { 898 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk); 899 ch->ch_rbpr = ibpr; 900 } else { 901 ch->ch_rcor = 0; 902 ch->ch_rbpr = 0; 903 } 904 905 /* Work out value to use for COR1 */ 906 cor = 0; 907 if ( ISSET(t->c_cflag, PARENB) ) { 908 cor |= CLMPCC_COR1_NORM_PARITY; 909 if ( ISSET(t->c_cflag, PARODD) ) 910 cor |= CLMPCC_COR1_ODD_PARITY; 911 } 912 913 if ( ISCLR(t->c_cflag, INPCK) ) 914 cor |= CLMPCC_COR1_IGNORE_PAR; 915 916 switch ( t->c_cflag & CSIZE ) { 917 case CS5: 918 cor |= CLMPCC_COR1_CHAR_5BITS; 919 break; 920 921 case CS6: 922 cor |= CLMPCC_COR1_CHAR_6BITS; 923 break; 924 925 case CS7: 926 cor |= CLMPCC_COR1_CHAR_7BITS; 927 break; 928 929 case CS8: 930 cor |= CLMPCC_COR1_CHAR_8BITS; 931 break; 932 } 933 934 ch->ch_cor1 = cor; 935 936 /* 937 * The only interesting bit in COR2 is 'CTS Automatic Enable' 938 * when hardware flow control is in effect. 939 */ 940 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0; 941 942 /* COR3 needs to be set to the number of stop bits... */ 943 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 : 944 CLMPCC_COR3_STOP_1; 945 946 /* 947 * COR4 contains the FIFO threshold setting. 948 * We adjust the threshold depending on the input speed... 949 */ 950 if ( t->c_ispeed <= 1200 ) 951 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW; 952 else if ( t->c_ispeed <= 19200 ) 953 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED; 954 else 955 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH; 956 957 /* 958 * If chip is used with CTS and DTR swapped, we can enable 959 * automatic hardware flow control. 960 */ 961 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) ) 962 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM; 963 else 964 ch->ch_cor5 = 0; 965 966 s = splserial(); 967 oldch = clmpcc_select_channel(sc, ch->ch_car); 968 969 /* 970 * COR2 needs to be set immediately otherwise we might never get 971 * a Tx EMPTY interrupt to change the other parameters. 972 */ 973 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 ) 974 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 975 976 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) ) 977 clmpcc_set_params(ch); 978 else 979 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 980 981 clmpcc_select_channel(sc, oldch); 982 983 splx(s); 984 985 return 0; 986 } 987 988 static void 989 clmpcc_set_params(ch) 990 struct clmpcc_chan *ch; 991 { 992 struct clmpcc_softc *sc = ch->ch_sc; 993 u_char r1; 994 u_char r2; 995 996 if ( ch->ch_tcor || ch->ch_tbpr ) { 997 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR); 998 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR); 999 /* Only write Tx rate if it really has changed */ 1000 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) { 1001 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor); 1002 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr); 1003 } 1004 } 1005 1006 if ( ch->ch_rcor || ch->ch_rbpr ) { 1007 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR); 1008 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR); 1009 /* Only write Rx rate if it really has changed */ 1010 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) { 1011 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor); 1012 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr); 1013 } 1014 } 1015 1016 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) { 1017 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1); 1018 /* Any change to COR1 requires an INIT command */ 1019 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1020 } 1021 1022 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 ) 1023 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3); 1024 1025 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1026 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) { 1027 /* 1028 * Note: If the FIFO has changed, we always set it to 1029 * zero here and disable the Receive Timeout interrupt. 1030 * It's up to the Rx Interrupt handler to pick the 1031 * appropriate moment to write the new FIFO length. 1032 */ 1033 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK); 1034 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1035 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET); 1036 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1037 } 1038 1039 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5); 1040 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) { 1041 r1 &= ~CLMPCC_COR5_FLOW_MASK; 1042 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5); 1043 } 1044 } 1045 1046 static void 1047 clmpcc_start(tp) 1048 struct tty *tp; 1049 { 1050 struct clmpcc_softc *sc = 1051 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1052 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1053 u_int oldch; 1054 int s; 1055 1056 s = spltty(); 1057 1058 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) { 1059 if ( tp->t_outq.c_cc <= tp->t_lowat ) { 1060 if ( ISSET(tp->t_state, TS_ASLEEP) ) { 1061 CLR(tp->t_state, TS_ASLEEP); 1062 wakeup(&tp->t_outq); 1063 } 1064 selwakeup(&tp->t_wsel); 1065 } 1066 1067 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1068 CLMPCC_FLG_END_BREAK) || 1069 tp->t_outq.c_cc > 0 ) { 1070 1071 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK | 1072 CLMPCC_FLG_END_BREAK) ) { 1073 ch->ch_obuf_addr = tp->t_outq.c_cf; 1074 ch->ch_obuf_size = ndqb(&tp->t_outq, 0); 1075 } 1076 1077 /* Enable TX empty interrupts */ 1078 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car); 1079 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 1080 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | 1081 CLMPCC_IER_TX_EMPTY); 1082 clmpcc_select_channel(ch->ch_sc, oldch); 1083 SET(tp->t_state, TS_BUSY); 1084 } 1085 } 1086 1087 splx(s); 1088 } 1089 1090 /* 1091 * Stop output on a line. 1092 */ 1093 void 1094 clmpccstop(tp, flag) 1095 struct tty *tp; 1096 int flag; 1097 { 1098 struct clmpcc_softc *sc = 1099 device_lookup(&clmpcc_cd, CLMPCCUNIT(tp->t_dev)); 1100 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)]; 1101 int s; 1102 1103 s = splserial(); 1104 1105 if ( ISSET(tp->t_state, TS_BUSY) ) { 1106 if ( ISCLR(tp->t_state, TS_TTSTOP) ) 1107 SET(tp->t_state, TS_FLUSH); 1108 ch->ch_obuf_size = 0; 1109 } 1110 splx(s); 1111 } 1112 1113 /* 1114 * RX interrupt routine 1115 */ 1116 int 1117 clmpcc_rxintr(arg) 1118 void *arg; 1119 { 1120 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1121 struct clmpcc_chan *ch; 1122 u_int8_t *put, *end, rxd; 1123 u_char errstat; 1124 u_char fc, tc; 1125 u_char risr; 1126 u_char rir; 1127 #ifdef DDB 1128 int saw_break = 0; 1129 #endif 1130 1131 /* Receive interrupt active? */ 1132 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1133 1134 /* 1135 * If we're using auto-vectored interrupts, we have to 1136 * verify if the chip is generating the interrupt. 1137 */ 1138 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 ) 1139 return 0; 1140 1141 /* Get pointer to interrupting channel's data structure */ 1142 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK]; 1143 1144 /* Get the interrupt status register */ 1145 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl); 1146 if ( risr & CLMPCC_RISR_TIMEOUT ) { 1147 u_char reg; 1148 /* 1149 * Set the FIFO threshold to zero, and disable 1150 * further receive timeout interrupts. 1151 */ 1152 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1153 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK); 1154 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1155 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET); 1156 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1157 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1158 return 1; 1159 } 1160 1161 /* How many bytes are waiting in the FIFO? */ 1162 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK; 1163 1164 #ifdef DDB 1165 /* 1166 * Allow BREAK on the console to drop to the debugger. 1167 */ 1168 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) && 1169 risr & CLMPCC_RISR_BREAK ) { 1170 saw_break = 1; 1171 } 1172 #endif 1173 1174 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) { 1175 /* Just get rid of the data */ 1176 while ( fc-- ) 1177 (void) clmpcc_rd_rxdata(sc); 1178 goto rx_done; 1179 } 1180 1181 put = ch->ch_ibuf_wr; 1182 end = ch->ch_ibuf_end; 1183 1184 /* 1185 * Note: The chip is completely hosed WRT these error 1186 * conditions; there seems to be no way to associate 1187 * the error with the correct character in the FIFO. 1188 * We compromise by tagging the first character we read 1189 * with the error. Not perfect, but there's no other way. 1190 */ 1191 errstat = 0; 1192 if ( risr & CLMPCC_RISR_PARITY ) 1193 errstat |= TTY_PE; 1194 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) ) 1195 errstat |= TTY_FE; 1196 1197 /* 1198 * As long as there are characters in the FIFO, and we 1199 * have space for them... 1200 */ 1201 while ( fc > 0 ) { 1202 1203 *put++ = rxd = clmpcc_rd_rxdata(sc); 1204 *put++ = errstat; 1205 1206 if ( put >= end ) 1207 put = ch->ch_ibuf; 1208 1209 if ( put == ch->ch_ibuf_rd ) { 1210 put -= 2; 1211 if ( put < ch->ch_ibuf ) 1212 put = end - 2; 1213 } 1214 1215 errstat = 0; 1216 fc--; 1217 } 1218 1219 ch->ch_ibuf_wr = put; 1220 1221 #if 0 1222 if ( sc->sc_swaprtsdtr == 0 && 1223 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) { 1224 /* 1225 * If RTS/DTR are not physically swapped, we have to 1226 * do hardware flow control manually 1227 */ 1228 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0); 1229 } 1230 #endif 1231 1232 rx_done: 1233 if ( fc != tc ) { 1234 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) { 1235 u_char reg; 1236 /* 1237 * Set the FIFO threshold to the preset value, 1238 * and enable receive timeout interrupts. 1239 */ 1240 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4); 1241 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4; 1242 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg); 1243 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1244 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET); 1245 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR); 1246 } 1247 1248 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1249 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1250 if ( sc->sc_soft_running == 0 ) { 1251 sc->sc_soft_running = 1; 1252 (sc->sc_softhook)(sc); 1253 } 1254 #else 1255 softintr_schedule(sc->sc_softintr_cookie); 1256 #endif 1257 } else 1258 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS); 1259 1260 #ifdef DDB 1261 /* 1262 * Only =after= we write REOIR is it safe to drop to the debugger. 1263 */ 1264 if ( saw_break ) 1265 Debugger(); 1266 #endif 1267 1268 return 1; 1269 } 1270 1271 /* 1272 * Tx interrupt routine 1273 */ 1274 int 1275 clmpcc_txintr(arg) 1276 void *arg; 1277 { 1278 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1279 struct clmpcc_chan *ch; 1280 struct tty *tp; 1281 u_char ftc, oftc; 1282 u_char tir, teoir; 1283 int etcmode = 0; 1284 1285 /* Tx interrupt active? */ 1286 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR); 1287 1288 /* 1289 * If we're using auto-vectored interrupts, we have to 1290 * verify if the chip is generating the interrupt. 1291 */ 1292 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 ) 1293 return 0; 1294 1295 /* Get pointer to interrupting channel's data structure */ 1296 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK]; 1297 tp = ch->ch_tty; 1298 1299 /* Dummy read of the interrupt status register */ 1300 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR); 1301 1302 /* Make sure embedded transmit commands are disabled */ 1303 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2); 1304 1305 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC); 1306 1307 /* Handle a delayed parameter change */ 1308 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) { 1309 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS); 1310 clmpcc_set_params(ch); 1311 } 1312 1313 if ( ch->ch_obuf_size > 0 ) { 1314 u_int n = min(ch->ch_obuf_size, ftc); 1315 1316 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n); 1317 1318 ftc -= n; 1319 ch->ch_obuf_size -= n; 1320 ch->ch_obuf_addr += n; 1321 1322 } else { 1323 /* 1324 * Check if we should start/stop a break 1325 */ 1326 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) { 1327 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK); 1328 /* Enable embedded transmit commands */ 1329 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1330 ch->ch_cor2 | CLMPCC_COR2_ETC); 1331 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1332 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK); 1333 ftc -= 2; 1334 etcmode = 1; 1335 } 1336 1337 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) { 1338 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK); 1339 /* Enable embedded transmit commands */ 1340 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 1341 ch->ch_cor2 | CLMPCC_COR2_ETC); 1342 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC); 1343 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK); 1344 ftc -= 2; 1345 etcmode = 1; 1346 } 1347 } 1348 1349 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1350 1351 if ( ftc != oftc ) { 1352 /* 1353 * Enable/disable the Tx FIFO threshold interrupt 1354 * according to how much data is in the FIFO. 1355 * However, always disable the FIFO threshold if 1356 * we've left the channel in 'Embedded Transmit 1357 * Command' mode. 1358 */ 1359 if ( etcmode || ftc >= ch->ch_cor4 ) 1360 tir &= ~CLMPCC_IER_TX_FIFO; 1361 else 1362 tir |= CLMPCC_IER_TX_FIFO; 1363 teoir = 0; 1364 } else { 1365 /* 1366 * No data was sent. 1367 * Disable transmit interrupt. 1368 */ 1369 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO); 1370 teoir = CLMPCC_TEOIR_NO_TRANS; 1371 1372 /* 1373 * Request Tx processing in the soft interrupt handler 1374 */ 1375 ch->ch_tx_done = 1; 1376 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1377 if ( sc->sc_soft_running == 0 ) { 1378 sc->sc_soft_running = 1; 1379 (sc->sc_softhook)(sc); 1380 } 1381 #else 1382 softintr_schedule(sc->sc_softintr_cookie); 1383 #endif 1384 } 1385 1386 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir); 1387 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir); 1388 1389 return 1; 1390 } 1391 1392 /* 1393 * Modem change interrupt routine 1394 */ 1395 int 1396 clmpcc_mdintr(arg) 1397 void *arg; 1398 { 1399 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1400 u_char mir; 1401 1402 /* Modem status interrupt active? */ 1403 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR); 1404 1405 /* 1406 * If we're using auto-vectored interrupts, we have to 1407 * verify if the chip is generating the interrupt. 1408 */ 1409 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 ) 1410 return 0; 1411 1412 /* Dummy read of the interrupt status register */ 1413 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR); 1414 1415 /* Retrieve current status of modem lines. */ 1416 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |= 1417 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1418 1419 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0); 1420 1421 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1422 if ( sc->sc_soft_running == 0 ) { 1423 sc->sc_soft_running = 1; 1424 (sc->sc_softhook)(sc); 1425 } 1426 #else 1427 softintr_schedule(sc->sc_softintr_cookie); 1428 #endif 1429 1430 return 1; 1431 } 1432 1433 void 1434 clmpcc_softintr(arg) 1435 void *arg; 1436 { 1437 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg; 1438 struct clmpcc_chan *ch; 1439 struct tty *tp; 1440 int (*rint)(int, struct tty *); 1441 u_char *get; 1442 u_char reg; 1443 u_int c; 1444 int chan; 1445 1446 #ifndef __HAVE_GENERIC_SOFT_INTERRUPTS 1447 sc->sc_soft_running = 0; 1448 #endif 1449 1450 /* Handle Modem state changes too... */ 1451 1452 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) { 1453 ch = &sc->sc_chans[chan]; 1454 tp = ch->ch_tty; 1455 1456 get = ch->ch_ibuf_rd; 1457 rint = tp->t_linesw->l_rint; 1458 1459 /* Squirt buffered incoming data into the tty layer */ 1460 while ( get != ch->ch_ibuf_wr ) { 1461 c = get[0]; 1462 c |= ((u_int)get[1]) << 8; 1463 if ( (rint)(c, tp) == -1 ) { 1464 ch->ch_ibuf_rd = ch->ch_ibuf_wr; 1465 break; 1466 } 1467 1468 get += 2; 1469 if ( get == ch->ch_ibuf_end ) 1470 get = ch->ch_ibuf; 1471 1472 ch->ch_ibuf_rd = get; 1473 } 1474 1475 /* 1476 * Is the transmitter idle and in need of attention? 1477 */ 1478 if ( ch->ch_tx_done ) { 1479 ch->ch_tx_done = 0; 1480 1481 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) { 1482 clmpcc_channel_cmd(sc, ch->ch_car, 1483 CLMPCC_CCR_T0_INIT | 1484 CLMPCC_CCR_T0_RX_EN | 1485 CLMPCC_CCR_T0_TX_EN); 1486 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT); 1487 1488 /* 1489 * Allow time for the channel to initialise. 1490 * (Empirically derived duration; there must 1491 * be another way to determine the command 1492 * has completed without busy-waiting...) 1493 */ 1494 delay(800); 1495 1496 /* 1497 * Update the tty layer's idea of the carrier 1498 * bit, in case we changed CLOCAL or MDMBUF. 1499 * We don't hang up here; we only do that by 1500 * explicit request. 1501 */ 1502 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD; 1503 (*tp->t_linesw->l_modem)(tp, reg != 0); 1504 } 1505 1506 CLR(tp->t_state, TS_BUSY); 1507 if ( ISSET(tp->t_state, TS_FLUSH) ) 1508 CLR(tp->t_state, TS_FLUSH); 1509 else 1510 ndflush(&tp->t_outq, 1511 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf)); 1512 1513 (*tp->t_linesw->l_start)(tp); 1514 } 1515 } 1516 } 1517 1518 1519 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1520 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1521 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/ 1522 /* 1523 * Following are all routines needed for a cd240x channel to act as console 1524 */ 1525 int 1526 clmpcc_cnattach(sc, chan, rate) 1527 struct clmpcc_softc *sc; 1528 int chan; 1529 int rate; 1530 { 1531 cons_sc = sc; 1532 cons_chan = chan; 1533 cons_rate = rate; 1534 1535 return (clmpcc_init(sc)); 1536 } 1537 1538 /* 1539 * The following functions are polled getc and putc routines, for console use. 1540 */ 1541 static int 1542 clmpcc_common_getc(sc, chan) 1543 struct clmpcc_softc *sc; 1544 int chan; 1545 { 1546 u_char old_chan; 1547 u_char old_ier; 1548 u_char ch, rir, risr; 1549 int s; 1550 1551 s = splhigh(); 1552 1553 /* Save the currently active channel */ 1554 old_chan = clmpcc_select_channel(sc, chan); 1555 1556 /* 1557 * We have to put the channel into RX interrupt mode before 1558 * trying to read the Rx data register. So save the previous 1559 * interrupt mode. 1560 */ 1561 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER); 1562 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO); 1563 1564 /* Loop until we get a character */ 1565 for (;;) { 1566 /* 1567 * The REN bit will be set in the Receive Interrupt Register 1568 * when the CD240x has a character to process. Remember, 1569 * the RACT bit won't be set until we generate an interrupt 1570 * acknowledge cycle via the MD front-end. 1571 */ 1572 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1573 if ( (rir & CLMPCC_RIR_REN) == 0 ) 1574 continue; 1575 1576 /* Acknowledge the request */ 1577 if ( sc->sc_iackhook ) 1578 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX); 1579 1580 /* 1581 * Determine if the interrupt is for the required channel 1582 * and if valid data is available. 1583 */ 1584 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR); 1585 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR); 1586 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan || 1587 risr != 0 ) { 1588 /* Rx error, or BREAK */ 1589 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 1590 CLMPCC_REOIR_NO_TRANS); 1591 } else { 1592 /* Dummy read of the FIFO count register */ 1593 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC); 1594 1595 /* Fetch the received character */ 1596 ch = clmpcc_rd_rxdata(sc); 1597 1598 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0); 1599 break; 1600 } 1601 } 1602 1603 /* Restore the original IER and CAR register contents */ 1604 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier); 1605 clmpcc_select_channel(sc, old_chan); 1606 1607 splx(s); 1608 return ch; 1609 } 1610 1611 1612 static void 1613 clmpcc_common_putc(sc, chan, c) 1614 struct clmpcc_softc *sc; 1615 int chan; 1616 int c; 1617 { 1618 u_char old_chan; 1619 int s = splhigh(); 1620 1621 /* Save the currently active channel */ 1622 old_chan = clmpcc_select_channel(sc, chan); 1623 1624 /* 1625 * Since we can only access the Tx Data register from within 1626 * the interrupt handler, the easiest way to get console data 1627 * onto the wire is using one of the Special Transmit Character 1628 * registers. 1629 */ 1630 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c); 1631 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) | 1632 CLMPCC_STCR_SND_SPC); 1633 1634 /* Wait until the "Send Special Character" command is accepted */ 1635 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 ) 1636 ; 1637 1638 /* Restore the previous channel selected */ 1639 clmpcc_select_channel(sc, old_chan); 1640 1641 splx(s); 1642 } 1643 1644 int 1645 clmpcccngetc(dev) 1646 dev_t dev; 1647 { 1648 return clmpcc_common_getc(cons_sc, cons_chan); 1649 } 1650 1651 /* 1652 * Console kernel output character routine. 1653 */ 1654 void 1655 clmpcccnputc(dev, c) 1656 dev_t dev; 1657 int c; 1658 { 1659 if ( c == '\n' ) 1660 clmpcc_common_putc(cons_sc, cons_chan, '\r'); 1661 1662 clmpcc_common_putc(cons_sc, cons_chan, c); 1663 } 1664