1 /* $NetBSD: clmpcc.c,v 1.54 2019/11/10 21:16:35 chs Exp $ */
2
3 /*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Steve C. Woodford.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 /*
33 * Cirrus Logic CD2400/CD2401 Four Channel Multi-Protocol Comms. Controller.
34 */
35
36 #include <sys/cdefs.h>
37 __KERNEL_RCSID(0, "$NetBSD: clmpcc.c,v 1.54 2019/11/10 21:16:35 chs Exp $");
38
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/systm.h>
43 #include <sys/ioctl.h>
44 #include <sys/select.h>
45 #include <sys/tty.h>
46 #include <sys/proc.h>
47 #include <sys/conf.h>
48 #include <sys/file.h>
49 #include <sys/uio.h>
50 #include <sys/kernel.h>
51 #include <sys/syslog.h>
52 #include <sys/device.h>
53 #include <sys/malloc.h>
54 #include <sys/kauth.h>
55 #include <sys/intr.h>
56
57 #include <sys/bus.h>
58 #include <machine/param.h>
59
60 #include <dev/ic/clmpccreg.h>
61 #include <dev/ic/clmpccvar.h>
62 #include <dev/cons.h>
63
64 #include "ioconf.h"
65
66 #if defined(CLMPCC_ONLY_BYTESWAP_LOW) && defined(CLMPCC_ONLY_BYTESWAP_HIGH)
67 #error "CLMPCC_ONLY_BYTESWAP_LOW and CLMPCC_ONLY_BYTESWAP_HIGH are mutually exclusive."
68 #endif
69
70
71 static int clmpcc_init(struct clmpcc_softc *sc);
72 static void clmpcc_shutdown(struct clmpcc_chan *);
73 static int clmpcc_speed(struct clmpcc_softc *, speed_t, int *, int *);
74 static int clmpcc_param(struct tty *, struct termios *);
75 static void clmpcc_set_params(struct clmpcc_chan *);
76 static void clmpcc_start(struct tty *);
77 static int clmpcc_modem_control(struct clmpcc_chan *, int, int);
78
79 #define CLMPCCUNIT(x) (TTUNIT(x) & ~0x3) // XXX >> 2?
80 #define CLMPCCCHAN(x) (TTUNIT(x) & 0x3)
81 #define CLMPCCDIALOUT(x) TTDIALOUT(x)
82
83 /*
84 * These should be in a header file somewhere...
85 */
86 #define ISCLR(v, f) (((v) & (f)) == 0)
87
88 dev_type_open(clmpccopen);
89 dev_type_close(clmpccclose);
90 dev_type_read(clmpccread);
91 dev_type_write(clmpccwrite);
92 dev_type_ioctl(clmpccioctl);
93 dev_type_stop(clmpccstop);
94 dev_type_tty(clmpcctty);
95 dev_type_poll(clmpccpoll);
96
97 const struct cdevsw clmpcc_cdevsw = {
98 .d_open = clmpccopen,
99 .d_close = clmpccclose,
100 .d_read = clmpccread,
101 .d_write = clmpccwrite,
102 .d_ioctl = clmpccioctl,
103 .d_stop = clmpccstop,
104 .d_tty = clmpcctty,
105 .d_poll = clmpccpoll,
106 .d_mmap = nommap,
107 .d_kqfilter = ttykqfilter,
108 .d_discard = nodiscard,
109 .d_flag = D_TTY
110 };
111
112 /*
113 * Make this an option variable one can patch.
114 */
115 u_int clmpcc_ibuf_size = CLMPCC_RING_SIZE;
116
117
118 /*
119 * Things needed when the device is used as a console
120 */
121 static struct clmpcc_softc *cons_sc = NULL;
122 static int cons_chan;
123 static int cons_rate;
124
125 static int clmpcc_common_getc(struct clmpcc_softc *, int);
126 static void clmpcc_common_putc(struct clmpcc_softc *, int, int);
127 int clmpcccngetc(dev_t);
128 void clmpcccnputc(dev_t, int);
129
130
131 /*
132 * Convenience functions, inlined for speed
133 */
134 #define integrate static inline
135 integrate u_int8_t clmpcc_rdreg(struct clmpcc_softc *, u_int);
136 integrate void clmpcc_wrreg(struct clmpcc_softc *, u_int, u_int);
137 integrate u_int8_t clmpcc_rdreg_odd(struct clmpcc_softc *, u_int);
138 integrate void clmpcc_wrreg_odd(struct clmpcc_softc *, u_int, u_int);
139 integrate void clmpcc_wrtx_multi(struct clmpcc_softc *, u_int8_t *,
140 u_int);
141 integrate u_int8_t clmpcc_select_channel(struct clmpcc_softc *, u_int);
142 integrate void clmpcc_channel_cmd(struct clmpcc_softc *,int,int);
143 integrate void clmpcc_enable_transmitter(struct clmpcc_chan *);
144
145 #define clmpcc_rd_msvr(s) clmpcc_rdreg_odd(s,CLMPCC_REG_MSVR)
146 #define clmpcc_wr_msvr(s,r,v) clmpcc_wrreg_odd(s,r,v)
147 #define clmpcc_wr_pilr(s,r,v) clmpcc_wrreg_odd(s,r,v)
148 #define clmpcc_rd_rxdata(s) clmpcc_rdreg_odd(s,CLMPCC_REG_RDR)
149 #define clmpcc_wr_txdata(s,v) clmpcc_wrreg_odd(s,CLMPCC_REG_TDR,v)
150
151
152 integrate u_int8_t
clmpcc_rdreg(struct clmpcc_softc * sc,u_int offset)153 clmpcc_rdreg(struct clmpcc_softc *sc, u_int offset)
154 {
155 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
156 offset ^= sc->sc_byteswap;
157 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
158 offset ^= CLMPCC_BYTESWAP_HIGH;
159 #endif
160 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
161 }
162
163 integrate void
clmpcc_wrreg(struct clmpcc_softc * sc,u_int offset,u_int val)164 clmpcc_wrreg(struct clmpcc_softc *sc, u_int offset, u_int val)
165 {
166 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
167 offset ^= sc->sc_byteswap;
168 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
169 offset ^= CLMPCC_BYTESWAP_HIGH;
170 #endif
171 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
172 }
173
174 integrate u_int8_t
clmpcc_rdreg_odd(struct clmpcc_softc * sc,u_int offset)175 clmpcc_rdreg_odd(struct clmpcc_softc *sc, u_int offset)
176 {
177 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
178 offset ^= (sc->sc_byteswap & 2);
179 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
180 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
181 #endif
182 return bus_space_read_1(sc->sc_iot, sc->sc_ioh, offset);
183 }
184
185 integrate void
clmpcc_wrreg_odd(struct clmpcc_softc * sc,u_int offset,u_int val)186 clmpcc_wrreg_odd(struct clmpcc_softc *sc, u_int offset, u_int val)
187 {
188 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
189 offset ^= (sc->sc_byteswap & 2);
190 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
191 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
192 #endif
193 bus_space_write_1(sc->sc_iot, sc->sc_ioh, offset, val);
194 }
195
196 integrate void
clmpcc_wrtx_multi(struct clmpcc_softc * sc,u_int8_t * buff,u_int count)197 clmpcc_wrtx_multi(struct clmpcc_softc *sc, u_int8_t *buff, u_int count)
198 {
199 u_int offset = CLMPCC_REG_TDR;
200
201 #if !defined(CLMPCC_ONLY_BYTESWAP_LOW) && !defined(CLMPCC_ONLY_BYTESWAP_HIGH)
202 offset ^= (sc->sc_byteswap & 2);
203 #elif defined(CLMPCC_ONLY_BYTESWAP_HIGH)
204 offset ^= (CLMPCC_BYTESWAP_HIGH & 2);
205 #endif
206 bus_space_write_multi_1(sc->sc_iot, sc->sc_ioh, offset, buff, count);
207 }
208
209 integrate u_int8_t
clmpcc_select_channel(struct clmpcc_softc * sc,u_int new_chan)210 clmpcc_select_channel(struct clmpcc_softc *sc, u_int new_chan)
211 {
212 u_int old_chan = clmpcc_rdreg_odd(sc, CLMPCC_REG_CAR);
213
214 clmpcc_wrreg_odd(sc, CLMPCC_REG_CAR, new_chan);
215
216 return old_chan;
217 }
218
219 integrate void
clmpcc_channel_cmd(struct clmpcc_softc * sc,int chan,int cmd)220 clmpcc_channel_cmd(struct clmpcc_softc *sc, int chan, int cmd)
221 {
222 int i;
223
224 for (i = 5000; i; i--) {
225 if ( clmpcc_rdreg(sc, CLMPCC_REG_CCR) == 0 )
226 break;
227 delay(1);
228 }
229
230 if ( i == 0 )
231 printf("%s: channel %d command timeout (idle)\n",
232 device_xname(sc->sc_dev), chan);
233
234 clmpcc_wrreg(sc, CLMPCC_REG_CCR, cmd);
235 }
236
237 integrate void
clmpcc_enable_transmitter(struct clmpcc_chan * ch)238 clmpcc_enable_transmitter(struct clmpcc_chan *ch)
239 {
240 u_int old;
241 int s;
242
243 old = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
244
245 s = splserial();
246 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
247 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) | CLMPCC_IER_TX_EMPTY);
248 SET(ch->ch_tty->t_state, TS_BUSY);
249 splx(s);
250
251 clmpcc_select_channel(ch->ch_sc, old);
252 }
253
254 static int
clmpcc_speed(struct clmpcc_softc * sc,speed_t speed,int * cor,int * bpr)255 clmpcc_speed(struct clmpcc_softc *sc, speed_t speed, int *cor, int *bpr)
256 {
257 int c, co, br;
258
259 for (co = 0, c = 8; c <= 2048; co++, c *= 4) {
260 br = ((sc->sc_clk / c) / speed) - 1;
261 if ( br < 0x100 ) {
262 *cor = co;
263 *bpr = br;
264 return 0;
265 }
266 }
267
268 return -1;
269 }
270
271 void
clmpcc_attach(struct clmpcc_softc * sc)272 clmpcc_attach(struct clmpcc_softc *sc)
273 {
274 struct clmpcc_chan *ch;
275 struct tty *tp;
276 int chan;
277
278 if ( cons_sc != NULL &&
279 sc->sc_iot == cons_sc->sc_iot && sc->sc_ioh == cons_sc->sc_ioh )
280 cons_sc = sc;
281
282 /* Initialise the chip */
283 clmpcc_init(sc);
284
285 printf(": Cirrus Logic CD240%c Serial Controller\n",
286 (clmpcc_rd_msvr(sc) & CLMPCC_MSVR_PORT_ID) ? '0' : '1');
287
288 sc->sc_softintr_cookie =
289 softint_establish(SOFTINT_SERIAL, clmpcc_softintr, sc);
290 if (sc->sc_softintr_cookie == NULL)
291 panic("clmpcc_attach: softintr_establish");
292 memset(&(sc->sc_chans[0]), 0, sizeof(sc->sc_chans));
293
294 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
295 ch = &sc->sc_chans[chan];
296
297 ch->ch_sc = sc;
298 ch->ch_car = chan;
299
300 tp = tty_alloc();
301 tp->t_oproc = clmpcc_start;
302 tp->t_param = clmpcc_param;
303
304 ch->ch_tty = tp;
305
306 ch->ch_ibuf = malloc(clmpcc_ibuf_size * 2, M_DEVBUF, M_WAITOK);
307 ch->ch_ibuf_end = &(ch->ch_ibuf[clmpcc_ibuf_size * 2]);
308 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
309
310 tty_attach(tp);
311 }
312
313 aprint_error_dev(sc->sc_dev, "%d channels available",
314 CLMPCC_NUM_CHANS);
315 if ( cons_sc == sc ) {
316 printf(", console on channel %d.\n", cons_chan);
317 SET(sc->sc_chans[cons_chan].ch_flags, CLMPCC_FLG_IS_CONSOLE);
318 SET(sc->sc_chans[cons_chan].ch_openflags, TIOCFLAG_SOFTCAR);
319 } else
320 printf(".\n");
321 }
322
323 static int
clmpcc_init(struct clmpcc_softc * sc)324 clmpcc_init(struct clmpcc_softc *sc)
325 {
326 u_int tcor = 0, tbpr = 0;
327 u_int rcor = 0, rbpr = 0;
328 u_int msvr_rts, msvr_dtr;
329 u_int ccr;
330 int is_console;
331 int i;
332
333 /*
334 * All we're really concerned about here is putting the chip
335 * into a quiescent state so that it won't do anything until
336 * clmpccopen() is called. (Except the console channel.)
337 */
338
339 /*
340 * If the chip is acting as console, set all channels to the supplied
341 * console baud rate. Otherwise, plump for 9600.
342 */
343 if ( cons_sc &&
344 sc->sc_ioh == cons_sc->sc_ioh && sc->sc_iot == cons_sc->sc_iot ) {
345 clmpcc_speed(sc, cons_rate, &tcor, &tbpr);
346 clmpcc_speed(sc, cons_rate, &rcor, &rbpr);
347 is_console = 1;
348 } else {
349 clmpcc_speed(sc, 9600, &tcor, &tbpr);
350 clmpcc_speed(sc, 9600, &rcor, &rbpr);
351 is_console = 0;
352 }
353
354 /* Allow any pending output to be sent */
355 delay(10000);
356
357 /* Send the Reset All command to channel 0 (resets all channels!) */
358 clmpcc_channel_cmd(sc, 0, CLMPCC_CCR_T0_RESET_ALL);
359
360 delay(1000);
361
362 /*
363 * The chip will set its firmware revision register to a non-zero
364 * value to indicate completion of reset.
365 */
366 for (i = 10000; clmpcc_rdreg(sc, CLMPCC_REG_GFRCR) == 0 && i; i--)
367 delay(1);
368
369 if ( i == 0 ) {
370 /*
371 * Watch out... If this chip is console, the message
372 * probably won't be sent since we just reset it!
373 */
374 aprint_error_dev(sc->sc_dev, "Failed to reset chip\n");
375 return -1;
376 }
377
378 for (i = 0; i < CLMPCC_NUM_CHANS; i++) {
379 clmpcc_select_channel(sc, i);
380
381 /* All interrupts are disabled to begin with */
382 clmpcc_wrreg(sc, CLMPCC_REG_IER, 0);
383
384 /* Make sure the channel interrupts on the correct vectors */
385 clmpcc_wrreg(sc, CLMPCC_REG_LIVR, sc->sc_vector_base);
386 clmpcc_wr_pilr(sc, CLMPCC_REG_RPILR, sc->sc_rpilr);
387 clmpcc_wr_pilr(sc, CLMPCC_REG_TPILR, sc->sc_tpilr);
388 clmpcc_wr_pilr(sc, CLMPCC_REG_MPILR, sc->sc_mpilr);
389
390 /* Receive timer prescaler set to 1ms */
391 clmpcc_wrreg(sc, CLMPCC_REG_TPR,
392 CLMPCC_MSEC_TO_TPR(sc->sc_clk, 1));
393
394 /* We support Async mode only */
395 clmpcc_wrreg(sc, CLMPCC_REG_CMR, CLMPCC_CMR_ASYNC);
396
397 /* Set the required baud rate */
398 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, CLMPCC_TCOR_CLK(tcor));
399 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, tbpr);
400 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, CLMPCC_RCOR_CLK(rcor));
401 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, rbpr);
402
403 /* Always default to 8N1 (XXX what about console?) */
404 clmpcc_wrreg(sc, CLMPCC_REG_COR1, CLMPCC_COR1_CHAR_8BITS |
405 CLMPCC_COR1_NO_PARITY |
406 CLMPCC_COR1_IGNORE_PAR);
407
408 clmpcc_wrreg(sc, CLMPCC_REG_COR2, 0);
409
410 clmpcc_wrreg(sc, CLMPCC_REG_COR3, CLMPCC_COR3_STOP_1);
411
412 clmpcc_wrreg(sc, CLMPCC_REG_COR4, CLMPCC_COR4_DSRzd |
413 CLMPCC_COR4_CDzd |
414 CLMPCC_COR4_CTSzd);
415
416 clmpcc_wrreg(sc, CLMPCC_REG_COR5, CLMPCC_COR5_DSRod |
417 CLMPCC_COR5_CDod |
418 CLMPCC_COR5_CTSod |
419 CLMPCC_COR5_FLOW_NORM);
420
421 clmpcc_wrreg(sc, CLMPCC_REG_COR6, 0);
422 clmpcc_wrreg(sc, CLMPCC_REG_COR7, 0);
423
424 /* Set the receive FIFO timeout */
425 clmpcc_wrreg(sc, CLMPCC_REG_RTPRl, CLMPCC_RTPR_DEFAULT);
426 clmpcc_wrreg(sc, CLMPCC_REG_RTPRh, 0);
427
428 /* At this point, we set up the console differently */
429 if ( is_console && i == cons_chan ) {
430 msvr_rts = CLMPCC_MSVR_RTS;
431 msvr_dtr = CLMPCC_MSVR_DTR;
432 ccr = CLMPCC_CCR_T0_RX_EN | CLMPCC_CCR_T0_TX_EN;
433 } else {
434 msvr_rts = 0;
435 msvr_dtr = 0;
436 ccr = CLMPCC_CCR_T0_RX_DIS | CLMPCC_CCR_T0_TX_DIS;
437 }
438
439 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_RTS, msvr_rts);
440 clmpcc_wrreg(sc, CLMPCC_REG_MSVR_DTR, msvr_dtr);
441 clmpcc_channel_cmd(sc, i, CLMPCC_CCR_T0_INIT | ccr);
442 delay(100);
443 }
444
445 return 0;
446 }
447
448 static void
clmpcc_shutdown(struct clmpcc_chan * ch)449 clmpcc_shutdown(struct clmpcc_chan *ch)
450 {
451 int oldch;
452
453 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
454
455 /* Turn off interrupts. */
456 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER, 0);
457
458 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
459 /* Disable the transmitter and receiver */
460 clmpcc_channel_cmd(ch->ch_sc, ch->ch_car, CLMPCC_CCR_T0_RX_DIS |
461 CLMPCC_CCR_T0_TX_DIS);
462
463 /* Drop RTS and DTR */
464 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
465 }
466
467 clmpcc_select_channel(ch->ch_sc, oldch);
468 }
469
470 int
clmpccopen(dev_t dev,int flag,int mode,struct lwp * l)471 clmpccopen(dev_t dev, int flag, int mode, struct lwp *l)
472 {
473 struct clmpcc_softc *sc;
474 struct clmpcc_chan *ch;
475 struct tty *tp;
476 int oldch;
477 int error;
478
479 sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
480 if (sc == NULL)
481 return (ENXIO);
482
483 ch = &sc->sc_chans[CLMPCCCHAN(dev)];
484
485 tp = ch->ch_tty;
486
487 if (kauth_authorize_device_tty(l->l_cred, KAUTH_DEVICE_TTY_OPEN, tp))
488 return EBUSY;
489
490 /*
491 * Do the following iff this is a first open.
492 */
493 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
494
495 ttychars(tp);
496
497 tp->t_dev = dev;
498 tp->t_iflag = TTYDEF_IFLAG;
499 tp->t_oflag = TTYDEF_OFLAG;
500 tp->t_lflag = TTYDEF_LFLAG;
501 tp->t_cflag = TTYDEF_CFLAG;
502 tp->t_ospeed = tp->t_ispeed = TTYDEF_SPEED;
503
504 if ( ISSET(ch->ch_openflags, TIOCFLAG_CLOCAL) )
505 SET(tp->t_cflag, CLOCAL);
506 if ( ISSET(ch->ch_openflags, TIOCFLAG_CRTSCTS) )
507 SET(tp->t_cflag, CRTSCTS);
508 if ( ISSET(ch->ch_openflags, TIOCFLAG_MDMBUF) )
509 SET(tp->t_cflag, MDMBUF);
510
511 /*
512 * Override some settings if the channel is being
513 * used as the console.
514 */
515 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
516 tp->t_ospeed = tp->t_ispeed = cons_rate;
517 SET(tp->t_cflag, CLOCAL);
518 CLR(tp->t_cflag, CRTSCTS);
519 CLR(tp->t_cflag, HUPCL);
520 }
521
522 ch->ch_control = 0;
523
524 clmpcc_param(tp, &tp->t_termios);
525 ttsetwater(tp);
526
527 /* Clear the input ring */
528 ch->ch_ibuf_rd = ch->ch_ibuf_wr = ch->ch_ibuf;
529
530 /* Select the channel */
531 oldch = clmpcc_select_channel(sc, ch->ch_car);
532
533 /* Reset it */
534 clmpcc_channel_cmd(sc, ch->ch_car, CLMPCC_CCR_T0_CLEAR |
535 CLMPCC_CCR_T0_RX_EN |
536 CLMPCC_CCR_T0_TX_EN);
537
538 /* Enable receiver and modem change interrupts. */
539 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_MODEM |
540 CLMPCC_IER_RET |
541 CLMPCC_IER_RX_FIFO);
542
543 /* Raise RTS and DTR */
544 clmpcc_modem_control(ch, TIOCM_RTS | TIOCM_DTR, DMBIS);
545
546 clmpcc_select_channel(sc, oldch);
547 }
548
549 error = ttyopen(tp, CLMPCCDIALOUT(dev), ISSET(flag, O_NONBLOCK));
550 if (error)
551 goto bad;
552
553 error = (*tp->t_linesw->l_open)(dev, tp);
554 if (error)
555 goto bad;
556
557 return 0;
558
559 bad:
560 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
561 /*
562 * We failed to open the device, and nobody else had it opened.
563 * Clean up the state as appropriate.
564 */
565 clmpcc_shutdown(ch);
566 }
567
568 return error;
569 }
570
571 int
clmpccclose(dev_t dev,int flag,int mode,struct lwp * l)572 clmpccclose(dev_t dev, int flag, int mode, struct lwp *l)
573 {
574 struct clmpcc_softc *sc =
575 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
576 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
577 struct tty *tp = ch->ch_tty;
578 int s;
579
580 if ( ISCLR(tp->t_state, TS_ISOPEN) )
581 return 0;
582
583 (*tp->t_linesw->l_close)(tp, flag);
584
585 s = spltty();
586
587 if ( ISCLR(tp->t_state, TS_ISOPEN) && tp->t_wopen == 0 ) {
588 /*
589 * Although we got a last close, the device may still be in
590 * use; e.g. if this was the dialout node, and there are still
591 * processes waiting for carrier on the non-dialout node.
592 */
593 clmpcc_shutdown(ch);
594 }
595
596 ttyclose(tp);
597
598 splx(s);
599
600 return 0;
601 }
602
603 int
clmpccread(dev_t dev,struct uio * uio,int flag)604 clmpccread(dev_t dev, struct uio *uio, int flag)
605 {
606 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
607 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
608
609 return ((*tp->t_linesw->l_read)(tp, uio, flag));
610 }
611
612 int
clmpccwrite(dev_t dev,struct uio * uio,int flag)613 clmpccwrite(dev_t dev, struct uio *uio, int flag)
614 {
615 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
616 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
617
618 return ((*tp->t_linesw->l_write)(tp, uio, flag));
619 }
620
621 int
clmpccpoll(dev_t dev,int events,struct lwp * l)622 clmpccpoll(dev_t dev, int events, struct lwp *l)
623 {
624 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
625 struct tty *tp = sc->sc_chans[CLMPCCCHAN(dev)].ch_tty;
626
627 return ((*tp->t_linesw->l_poll)(tp, events, l));
628 }
629
630 struct tty *
clmpcctty(dev_t dev)631 clmpcctty(dev_t dev)
632 {
633 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
634
635 return (sc->sc_chans[CLMPCCCHAN(dev)].ch_tty);
636 }
637
638 int
clmpccioctl(dev_t dev,u_long cmd,void * data,int flag,struct lwp * l)639 clmpccioctl(dev_t dev, u_long cmd, void *data, int flag, struct lwp *l)
640 {
641 struct clmpcc_softc *sc = device_lookup_private(&clmpcc_cd, CLMPCCUNIT(dev));
642 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(dev)];
643 struct tty *tp = ch->ch_tty;
644 int error;
645
646 error = (*tp->t_linesw->l_ioctl)(tp, cmd, data, flag, l);
647 if (error != EPASSTHROUGH)
648 return error;
649
650 error = ttioctl(tp, cmd, data, flag, l);
651 if (error != EPASSTHROUGH)
652 return error;
653
654 error = 0;
655
656 switch (cmd) {
657 case TIOCSBRK:
658 SET(ch->ch_flags, CLMPCC_FLG_START_BREAK);
659 clmpcc_enable_transmitter(ch);
660 break;
661
662 case TIOCCBRK:
663 SET(ch->ch_flags, CLMPCC_FLG_END_BREAK);
664 clmpcc_enable_transmitter(ch);
665 break;
666
667 case TIOCSDTR:
668 clmpcc_modem_control(ch, TIOCM_DTR, DMBIS);
669 break;
670
671 case TIOCCDTR:
672 clmpcc_modem_control(ch, TIOCM_DTR, DMBIC);
673 break;
674
675 case TIOCMSET:
676 clmpcc_modem_control(ch, *((int *)data), DMSET);
677 break;
678
679 case TIOCMBIS:
680 clmpcc_modem_control(ch, *((int *)data), DMBIS);
681 break;
682
683 case TIOCMBIC:
684 clmpcc_modem_control(ch, *((int *)data), DMBIC);
685 break;
686
687 case TIOCMGET:
688 *((int *)data) = clmpcc_modem_control(ch, 0, DMGET);
689 break;
690
691 case TIOCGFLAGS:
692 *((int *)data) = ch->ch_openflags;
693 break;
694
695 case TIOCSFLAGS:
696 error = kauth_authorize_device_tty(l->l_cred,
697 KAUTH_DEVICE_TTY_PRIVSET, tp);
698 if ( error )
699 break;
700 ch->ch_openflags = *((int *)data) &
701 (TIOCFLAG_SOFTCAR | TIOCFLAG_CLOCAL |
702 TIOCFLAG_CRTSCTS | TIOCFLAG_MDMBUF);
703 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) )
704 SET(ch->ch_openflags, TIOCFLAG_SOFTCAR);
705 break;
706
707 default:
708 error = EPASSTHROUGH;
709 break;
710 }
711
712 return error;
713 }
714
715 int
clmpcc_modem_control(struct clmpcc_chan * ch,int bits,int howto)716 clmpcc_modem_control(struct clmpcc_chan *ch, int bits, int howto)
717 {
718 struct clmpcc_softc *sc = ch->ch_sc;
719 struct tty *tp = ch->ch_tty;
720 int oldch;
721 int msvr;
722 int rbits = 0;
723
724 oldch = clmpcc_select_channel(sc, ch->ch_car);
725
726 switch ( howto ) {
727 case DMGET:
728 msvr = clmpcc_rd_msvr(sc);
729
730 if ( sc->sc_swaprtsdtr ) {
731 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_DTR : 0;
732 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_RTS : 0;
733 } else {
734 rbits |= (msvr & CLMPCC_MSVR_RTS) ? TIOCM_RTS : 0;
735 rbits |= (msvr & CLMPCC_MSVR_DTR) ? TIOCM_DTR : 0;
736 }
737
738 rbits |= (msvr & CLMPCC_MSVR_CTS) ? TIOCM_CTS : 0;
739 rbits |= (msvr & CLMPCC_MSVR_CD) ? TIOCM_CD : 0;
740 rbits |= (msvr & CLMPCC_MSVR_DSR) ? TIOCM_DSR : 0;
741 break;
742
743 case DMSET:
744 if ( sc->sc_swaprtsdtr ) {
745 if ( ISCLR(tp->t_cflag, CRTSCTS) )
746 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
747 bits & TIOCM_RTS ? CLMPCC_MSVR_DTR : 0);
748 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
749 bits & TIOCM_DTR ? CLMPCC_MSVR_RTS : 0);
750 } else {
751 if ( ISCLR(tp->t_cflag, CRTSCTS) )
752 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS,
753 bits & TIOCM_RTS ? CLMPCC_MSVR_RTS : 0);
754 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR,
755 bits & TIOCM_DTR ? CLMPCC_MSVR_DTR : 0);
756 }
757 break;
758
759 case DMBIS:
760 if ( sc->sc_swaprtsdtr ) {
761 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
762 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
763 if ( ISSET(bits, TIOCM_DTR) )
764 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
765 } else {
766 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISSET(bits, TIOCM_RTS) )
767 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_RTS, CLMPCC_MSVR_RTS);
768 if ( ISSET(bits, TIOCM_DTR) )
769 clmpcc_wr_msvr(sc,CLMPCC_REG_MSVR_DTR, CLMPCC_MSVR_DTR);
770 }
771 break;
772
773 case DMBIC:
774 if ( sc->sc_swaprtsdtr ) {
775 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
776 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
777 if ( ISCLR(bits, TIOCM_DTR) )
778 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
779 } else {
780 if ( ISCLR(tp->t_cflag, CRTSCTS) && ISCLR(bits, TIOCM_RTS) )
781 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_RTS, 0);
782 if ( ISCLR(bits, TIOCM_DTR) )
783 clmpcc_wr_msvr(sc, CLMPCC_REG_MSVR_DTR, 0);
784 }
785 break;
786 }
787
788 clmpcc_select_channel(sc, oldch);
789
790 return rbits;
791 }
792
793 static int
clmpcc_param(struct tty * tp,struct termios * t)794 clmpcc_param(struct tty *tp, struct termios *t)
795 {
796 struct clmpcc_softc *sc =
797 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
798 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
799 u_char cor;
800 u_char oldch;
801 int oclk = 0, obpr = 0;
802 int iclk = 0, ibpr = 0;
803 int s;
804
805 /* Check requested parameters. */
806 if ( t->c_ospeed && clmpcc_speed(sc, t->c_ospeed, &oclk, &obpr) < 0 )
807 return EINVAL;
808
809 if ( t->c_ispeed && clmpcc_speed(sc, t->c_ispeed, &iclk, &ibpr) < 0 )
810 return EINVAL;
811
812 /*
813 * For the console, always force CLOCAL and !HUPCL, so that the port
814 * is always active.
815 */
816 if ( ISSET(ch->ch_openflags, TIOCFLAG_SOFTCAR) ||
817 ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) ) {
818 SET(t->c_cflag, CLOCAL);
819 CLR(t->c_cflag, HUPCL);
820 }
821
822 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
823
824 /* If ospeed it zero, hangup the line */
825 clmpcc_modem_control(ch, TIOCM_DTR, t->c_ospeed == 0 ? DMBIC : DMBIS);
826
827 if ( t->c_ospeed ) {
828 ch->ch_tcor = CLMPCC_TCOR_CLK(oclk);
829 ch->ch_tbpr = obpr;
830 } else {
831 ch->ch_tcor = 0;
832 ch->ch_tbpr = 0;
833 }
834
835 if ( t->c_ispeed ) {
836 ch->ch_rcor = CLMPCC_RCOR_CLK(iclk);
837 ch->ch_rbpr = ibpr;
838 } else {
839 ch->ch_rcor = 0;
840 ch->ch_rbpr = 0;
841 }
842
843 /* Work out value to use for COR1 */
844 cor = 0;
845 if ( ISSET(t->c_cflag, PARENB) ) {
846 cor |= CLMPCC_COR1_NORM_PARITY;
847 if ( ISSET(t->c_cflag, PARODD) )
848 cor |= CLMPCC_COR1_ODD_PARITY;
849 }
850
851 if ( ISCLR(t->c_cflag, INPCK) )
852 cor |= CLMPCC_COR1_IGNORE_PAR;
853
854 switch ( t->c_cflag & CSIZE ) {
855 case CS5:
856 cor |= CLMPCC_COR1_CHAR_5BITS;
857 break;
858
859 case CS6:
860 cor |= CLMPCC_COR1_CHAR_6BITS;
861 break;
862
863 case CS7:
864 cor |= CLMPCC_COR1_CHAR_7BITS;
865 break;
866
867 case CS8:
868 cor |= CLMPCC_COR1_CHAR_8BITS;
869 break;
870 }
871
872 ch->ch_cor1 = cor;
873
874 /*
875 * The only interesting bit in COR2 is 'CTS Automatic Enable'
876 * when hardware flow control is in effect.
877 */
878 ch->ch_cor2 = ISSET(t->c_cflag, CRTSCTS) ? CLMPCC_COR2_CtsAE : 0;
879
880 /* COR3 needs to be set to the number of stop bits... */
881 ch->ch_cor3 = ISSET(t->c_cflag, CSTOPB) ? CLMPCC_COR3_STOP_2 :
882 CLMPCC_COR3_STOP_1;
883
884 /*
885 * COR4 contains the FIFO threshold setting.
886 * We adjust the threshold depending on the input speed...
887 */
888 if ( t->c_ispeed <= 1200 )
889 ch->ch_cor4 = CLMPCC_COR4_FIFO_LOW;
890 else if ( t->c_ispeed <= 19200 )
891 ch->ch_cor4 = CLMPCC_COR4_FIFO_MED;
892 else
893 ch->ch_cor4 = CLMPCC_COR4_FIFO_HIGH;
894
895 /*
896 * If chip is used with CTS and DTR swapped, we can enable
897 * automatic hardware flow control.
898 */
899 if ( sc->sc_swaprtsdtr && ISSET(t->c_cflag, CRTSCTS) )
900 ch->ch_cor5 = CLMPCC_COR5_FLOW_NORM;
901 else
902 ch->ch_cor5 = 0;
903
904 s = splserial();
905 oldch = clmpcc_select_channel(sc, ch->ch_car);
906
907 /*
908 * COR2 needs to be set immediately otherwise we might never get
909 * a Tx EMPTY interrupt to change the other parameters.
910 */
911 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR2) != ch->ch_cor2 )
912 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
913
914 if ( ISCLR(ch->ch_tty->t_state, TS_BUSY) )
915 clmpcc_set_params(ch);
916 else
917 SET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
918
919 clmpcc_select_channel(sc, oldch);
920
921 splx(s);
922
923 return 0;
924 }
925
926 static void
clmpcc_set_params(struct clmpcc_chan * ch)927 clmpcc_set_params(struct clmpcc_chan *ch)
928 {
929 struct clmpcc_softc *sc = ch->ch_sc;
930 u_char r1;
931 u_char r2;
932
933 if ( ch->ch_tcor || ch->ch_tbpr ) {
934 r1 = clmpcc_rdreg(sc, CLMPCC_REG_TCOR);
935 r2 = clmpcc_rdreg(sc, CLMPCC_REG_TBPR);
936 /* Only write Tx rate if it really has changed */
937 if ( ch->ch_tcor != r1 || ch->ch_tbpr != r2 ) {
938 clmpcc_wrreg(sc, CLMPCC_REG_TCOR, ch->ch_tcor);
939 clmpcc_wrreg(sc, CLMPCC_REG_TBPR, ch->ch_tbpr);
940 }
941 }
942
943 if ( ch->ch_rcor || ch->ch_rbpr ) {
944 r1 = clmpcc_rdreg(sc, CLMPCC_REG_RCOR);
945 r2 = clmpcc_rdreg(sc, CLMPCC_REG_RBPR);
946 /* Only write Rx rate if it really has changed */
947 if ( ch->ch_rcor != r1 || ch->ch_rbpr != r2 ) {
948 clmpcc_wrreg(sc, CLMPCC_REG_RCOR, ch->ch_rcor);
949 clmpcc_wrreg(sc, CLMPCC_REG_RBPR, ch->ch_rbpr);
950 }
951 }
952
953 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR1) != ch->ch_cor1 ) {
954 clmpcc_wrreg(sc, CLMPCC_REG_COR1, ch->ch_cor1);
955 /* Any change to COR1 requires an INIT command */
956 SET(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
957 }
958
959 if ( clmpcc_rdreg(sc, CLMPCC_REG_COR3) != ch->ch_cor3 )
960 clmpcc_wrreg(sc, CLMPCC_REG_COR3, ch->ch_cor3);
961
962 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
963 if ( ch->ch_cor4 != (r1 & CLMPCC_COR4_FIFO_MASK) ) {
964 /*
965 * Note: If the FIFO has changed, we always set it to
966 * zero here and disable the Receive Timeout interrupt.
967 * It's up to the Rx Interrupt handler to pick the
968 * appropriate moment to write the new FIFO length.
969 */
970 clmpcc_wrreg(sc, CLMPCC_REG_COR4, r1 & ~CLMPCC_COR4_FIFO_MASK);
971 r1 = clmpcc_rdreg(sc, CLMPCC_REG_IER);
972 clmpcc_wrreg(sc, CLMPCC_REG_IER, r1 & ~CLMPCC_IER_RET);
973 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
974 }
975
976 r1 = clmpcc_rdreg(sc, CLMPCC_REG_COR5);
977 if ( ch->ch_cor5 != (r1 & CLMPCC_COR5_FLOW_MASK) ) {
978 r1 &= ~CLMPCC_COR5_FLOW_MASK;
979 clmpcc_wrreg(sc, CLMPCC_REG_COR5, r1 | ch->ch_cor5);
980 }
981 }
982
983 static void
clmpcc_start(struct tty * tp)984 clmpcc_start(struct tty *tp)
985 {
986 struct clmpcc_softc *sc =
987 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
988 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
989 u_int oldch;
990 int s;
991
992 s = spltty();
993
994 if ( ISCLR(tp->t_state, TS_TTSTOP | TS_TIMEOUT | TS_BUSY) ) {
995 ttypull(tp);
996 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK |
997 CLMPCC_FLG_END_BREAK) ||
998 tp->t_outq.c_cc > 0 ) {
999
1000 if ( ISCLR(ch->ch_flags, CLMPCC_FLG_START_BREAK |
1001 CLMPCC_FLG_END_BREAK) ) {
1002 ch->ch_obuf_addr = tp->t_outq.c_cf;
1003 ch->ch_obuf_size = ndqb(&tp->t_outq, 0);
1004 }
1005
1006 /* Enable TX empty interrupts */
1007 oldch = clmpcc_select_channel(ch->ch_sc, ch->ch_car);
1008 clmpcc_wrreg(ch->ch_sc, CLMPCC_REG_IER,
1009 clmpcc_rdreg(ch->ch_sc, CLMPCC_REG_IER) |
1010 CLMPCC_IER_TX_EMPTY);
1011 clmpcc_select_channel(ch->ch_sc, oldch);
1012 SET(tp->t_state, TS_BUSY);
1013 }
1014 }
1015
1016 splx(s);
1017 }
1018
1019 /*
1020 * Stop output on a line.
1021 */
1022 void
clmpccstop(struct tty * tp,int flag)1023 clmpccstop(struct tty *tp, int flag)
1024 {
1025 struct clmpcc_softc *sc =
1026 device_lookup_private(&clmpcc_cd, CLMPCCUNIT(tp->t_dev));
1027 struct clmpcc_chan *ch = &sc->sc_chans[CLMPCCCHAN(tp->t_dev)];
1028 int s;
1029
1030 s = splserial();
1031
1032 if ( ISSET(tp->t_state, TS_BUSY) ) {
1033 if ( ISCLR(tp->t_state, TS_TTSTOP) )
1034 SET(tp->t_state, TS_FLUSH);
1035 ch->ch_obuf_size = 0;
1036 }
1037 splx(s);
1038 }
1039
1040 /*
1041 * RX interrupt routine
1042 */
1043 int
clmpcc_rxintr(void * arg)1044 clmpcc_rxintr(void *arg)
1045 {
1046 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1047 struct clmpcc_chan *ch;
1048 u_int8_t *put, *end, rxd;
1049 u_char errstat;
1050 u_char fc, tc;
1051 u_char risr;
1052 u_char rir;
1053 #ifdef DDB
1054 int saw_break = 0;
1055 #endif
1056
1057 /* Receive interrupt active? */
1058 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1059
1060 /*
1061 * If we're using auto-vectored interrupts, we have to
1062 * verify if the chip is generating the interrupt.
1063 */
1064 if ( sc->sc_vector_base == 0 && (rir & CLMPCC_RIR_RACT) == 0 )
1065 return 0;
1066
1067 /* Get pointer to interrupting channel's data structure */
1068 ch = &sc->sc_chans[rir & CLMPCC_RIR_RCN_MASK];
1069
1070 /* Get the interrupt status register */
1071 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISRl);
1072 if ( risr & CLMPCC_RISR_TIMEOUT ) {
1073 u_char reg;
1074 /*
1075 * Set the FIFO threshold to zero, and disable
1076 * further receive timeout interrupts.
1077 */
1078 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1079 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg & ~CLMPCC_COR4_FIFO_MASK);
1080 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1081 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg & ~CLMPCC_IER_RET);
1082 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1083 SET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1084 return 1;
1085 }
1086
1087 /* How many bytes are waiting in the FIFO? */
1088 fc = tc = clmpcc_rdreg(sc, CLMPCC_REG_RFOC) & CLMPCC_RFOC_MASK;
1089
1090 #ifdef DDB
1091 /*
1092 * Allow BREAK on the console to drop to the debugger.
1093 */
1094 if ( ISSET(ch->ch_flags, CLMPCC_FLG_IS_CONSOLE) &&
1095 risr & CLMPCC_RISR_BREAK ) {
1096 saw_break = 1;
1097 }
1098 #endif
1099
1100 if ( ISCLR(ch->ch_tty->t_state, TS_ISOPEN) && fc ) {
1101 /* Just get rid of the data */
1102 while ( fc-- )
1103 (void) clmpcc_rd_rxdata(sc);
1104 goto rx_done;
1105 }
1106
1107 put = ch->ch_ibuf_wr;
1108 end = ch->ch_ibuf_end;
1109
1110 /*
1111 * Note: The chip is completely hosed WRT these error
1112 * conditions; there seems to be no way to associate
1113 * the error with the correct character in the FIFO.
1114 * We compromise by tagging the first character we read
1115 * with the error. Not perfect, but there's no other way.
1116 */
1117 errstat = 0;
1118 if ( risr & CLMPCC_RISR_PARITY )
1119 errstat |= TTY_PE;
1120 if ( risr & (CLMPCC_RISR_FRAMING | CLMPCC_RISR_BREAK) )
1121 errstat |= TTY_FE;
1122
1123 /*
1124 * As long as there are characters in the FIFO, and we
1125 * have space for them...
1126 */
1127 while ( fc > 0 ) {
1128
1129 *put++ = rxd = clmpcc_rd_rxdata(sc);
1130 *put++ = errstat;
1131
1132 if ( put >= end )
1133 put = ch->ch_ibuf;
1134
1135 if ( put == ch->ch_ibuf_rd ) {
1136 put -= 2;
1137 if ( put < ch->ch_ibuf )
1138 put = end - 2;
1139 }
1140
1141 errstat = 0;
1142 fc--;
1143 }
1144
1145 ch->ch_ibuf_wr = put;
1146
1147 #if 0
1148 if ( sc->sc_swaprtsdtr == 0 &&
1149 ISSET(cy->cy_tty->t_cflag, CRTSCTS) && cc < ch->ch_r_hiwat) {
1150 /*
1151 * If RTS/DTR are not physically swapped, we have to
1152 * do hardware flow control manually
1153 */
1154 clmpcc_wr_msvr(sc, CLMPCC_MSVR_RTS, 0);
1155 }
1156 #endif
1157
1158 rx_done:
1159 if ( fc != tc ) {
1160 if ( ISSET(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR) ) {
1161 u_char reg;
1162 /*
1163 * Set the FIFO threshold to the preset value,
1164 * and enable receive timeout interrupts.
1165 */
1166 reg = clmpcc_rdreg(sc, CLMPCC_REG_COR4);
1167 reg = (reg & ~CLMPCC_COR4_FIFO_MASK) | ch->ch_cor4;
1168 clmpcc_wrreg(sc, CLMPCC_REG_COR4, reg);
1169 reg = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1170 clmpcc_wrreg(sc, CLMPCC_REG_IER, reg | CLMPCC_IER_RET);
1171 CLR(ch->ch_flags, CLMPCC_FLG_FIFO_CLEAR);
1172 }
1173
1174 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1175 softint_schedule(sc->sc_softintr_cookie);
1176 } else
1177 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, CLMPCC_REOIR_NO_TRANS);
1178
1179 #ifdef DDB
1180 /*
1181 * Only =after= we write REOIR is it safe to drop to the debugger.
1182 */
1183 if ( saw_break )
1184 Debugger();
1185 #endif
1186
1187 return 1;
1188 }
1189
1190 /*
1191 * Tx interrupt routine
1192 */
1193 int
clmpcc_txintr(void * arg)1194 clmpcc_txintr(void *arg)
1195 {
1196 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1197 struct clmpcc_chan *ch;
1198 u_char ftc, oftc;
1199 u_char tir, teoir;
1200 int etcmode = 0;
1201
1202 /* Tx interrupt active? */
1203 tir = clmpcc_rdreg(sc, CLMPCC_REG_TIR);
1204
1205 /*
1206 * If we're using auto-vectored interrupts, we have to
1207 * verify if the chip is generating the interrupt.
1208 */
1209 if ( sc->sc_vector_base == 0 && (tir & CLMPCC_TIR_TACT) == 0 )
1210 return 0;
1211
1212 /* Get pointer to interrupting channel's data structure */
1213 ch = &sc->sc_chans[tir & CLMPCC_TIR_TCN_MASK];
1214
1215 /* Dummy read of the interrupt status register */
1216 (void) clmpcc_rdreg(sc, CLMPCC_REG_TISR);
1217
1218 /* Make sure embedded transmit commands are disabled */
1219 clmpcc_wrreg(sc, CLMPCC_REG_COR2, ch->ch_cor2);
1220
1221 ftc = oftc = clmpcc_rdreg(sc, CLMPCC_REG_TFTC);
1222
1223 /* Handle a delayed parameter change */
1224 if ( ISSET(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS) ) {
1225 CLR(ch->ch_flags, CLMPCC_FLG_UPDATE_PARMS);
1226 clmpcc_set_params(ch);
1227 }
1228
1229 if ( ch->ch_obuf_size > 0 ) {
1230 u_int n = uimin(ch->ch_obuf_size, ftc);
1231
1232 clmpcc_wrtx_multi(sc, ch->ch_obuf_addr, n);
1233
1234 ftc -= n;
1235 ch->ch_obuf_size -= n;
1236 ch->ch_obuf_addr += n;
1237
1238 } else {
1239 /*
1240 * Check if we should start/stop a break
1241 */
1242 if ( ISSET(ch->ch_flags, CLMPCC_FLG_START_BREAK) ) {
1243 CLR(ch->ch_flags, CLMPCC_FLG_START_BREAK);
1244 /* Enable embedded transmit commands */
1245 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1246 ch->ch_cor2 | CLMPCC_COR2_ETC);
1247 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1248 clmpcc_wr_txdata(sc, CLMPCC_ETC_SEND_BREAK);
1249 ftc -= 2;
1250 etcmode = 1;
1251 }
1252
1253 if ( ISSET(ch->ch_flags, CLMPCC_FLG_END_BREAK) ) {
1254 CLR(ch->ch_flags, CLMPCC_FLG_END_BREAK);
1255 /* Enable embedded transmit commands */
1256 clmpcc_wrreg(sc, CLMPCC_REG_COR2,
1257 ch->ch_cor2 | CLMPCC_COR2_ETC);
1258 clmpcc_wr_txdata(sc, CLMPCC_ETC_MAGIC);
1259 clmpcc_wr_txdata(sc, CLMPCC_ETC_STOP_BREAK);
1260 ftc -= 2;
1261 etcmode = 1;
1262 }
1263 }
1264
1265 tir = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1266
1267 if ( ftc != oftc ) {
1268 /*
1269 * Enable/disable the Tx FIFO threshold interrupt
1270 * according to how much data is in the FIFO.
1271 * However, always disable the FIFO threshold if
1272 * we've left the channel in 'Embedded Transmit
1273 * Command' mode.
1274 */
1275 if ( etcmode || ftc >= ch->ch_cor4 )
1276 tir &= ~CLMPCC_IER_TX_FIFO;
1277 else
1278 tir |= CLMPCC_IER_TX_FIFO;
1279 teoir = 0;
1280 } else {
1281 /*
1282 * No data was sent.
1283 * Disable transmit interrupt.
1284 */
1285 tir &= ~(CLMPCC_IER_TX_EMPTY|CLMPCC_IER_TX_FIFO);
1286 teoir = CLMPCC_TEOIR_NO_TRANS;
1287
1288 /*
1289 * Request Tx processing in the soft interrupt handler
1290 */
1291 ch->ch_tx_done = 1;
1292 softint_schedule(sc->sc_softintr_cookie);
1293 }
1294
1295 clmpcc_wrreg(sc, CLMPCC_REG_IER, tir);
1296 clmpcc_wrreg(sc, CLMPCC_REG_TEOIR, teoir);
1297
1298 return 1;
1299 }
1300
1301 /*
1302 * Modem change interrupt routine
1303 */
1304 int
clmpcc_mdintr(void * arg)1305 clmpcc_mdintr(void *arg)
1306 {
1307 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1308 u_char mir;
1309
1310 /* Modem status interrupt active? */
1311 mir = clmpcc_rdreg(sc, CLMPCC_REG_MIR);
1312
1313 /*
1314 * If we're using auto-vectored interrupts, we have to
1315 * verify if the chip is generating the interrupt.
1316 */
1317 if ( sc->sc_vector_base == 0 && (mir & CLMPCC_MIR_MACT) == 0 )
1318 return 0;
1319
1320 /* Dummy read of the interrupt status register */
1321 (void) clmpcc_rdreg(sc, CLMPCC_REG_MISR);
1322
1323 /* Retrieve current status of modem lines. */
1324 sc->sc_chans[mir & CLMPCC_MIR_MCN_MASK].ch_control |=
1325 clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1326
1327 clmpcc_wrreg(sc, CLMPCC_REG_MEOIR, 0);
1328 softint_schedule(sc->sc_softintr_cookie);
1329
1330 return 1;
1331 }
1332
1333 void
clmpcc_softintr(void * arg)1334 clmpcc_softintr(void *arg)
1335 {
1336 struct clmpcc_softc *sc = (struct clmpcc_softc *)arg;
1337 struct clmpcc_chan *ch;
1338 struct tty *tp;
1339 int (*rint)(int, struct tty *);
1340 u_char *get;
1341 u_char reg;
1342 u_int c;
1343 int chan;
1344
1345 /* Handle Modem state changes too... */
1346
1347 for (chan = 0; chan < CLMPCC_NUM_CHANS; chan++) {
1348 ch = &sc->sc_chans[chan];
1349 tp = ch->ch_tty;
1350
1351 get = ch->ch_ibuf_rd;
1352 rint = tp->t_linesw->l_rint;
1353
1354 /* Squirt buffered incoming data into the tty layer */
1355 while ( get != ch->ch_ibuf_wr ) {
1356 c = get[0];
1357 c |= ((u_int)get[1]) << 8;
1358 if ( (rint)(c, tp) == -1 ) {
1359 ch->ch_ibuf_rd = ch->ch_ibuf_wr;
1360 break;
1361 }
1362
1363 get += 2;
1364 if ( get == ch->ch_ibuf_end )
1365 get = ch->ch_ibuf;
1366
1367 ch->ch_ibuf_rd = get;
1368 }
1369
1370 /*
1371 * Is the transmitter idle and in need of attention?
1372 */
1373 if ( ch->ch_tx_done ) {
1374 ch->ch_tx_done = 0;
1375
1376 if ( ISSET(ch->ch_flags, CLMPCC_FLG_NEED_INIT) ) {
1377 clmpcc_channel_cmd(sc, ch->ch_car,
1378 CLMPCC_CCR_T0_INIT |
1379 CLMPCC_CCR_T0_RX_EN |
1380 CLMPCC_CCR_T0_TX_EN);
1381 CLR(ch->ch_flags, CLMPCC_FLG_NEED_INIT);
1382
1383 /*
1384 * Allow time for the channel to initialise.
1385 * (Empirically derived duration; there must
1386 * be another way to determine the command
1387 * has completed without busy-waiting...)
1388 */
1389 delay(800);
1390
1391 /*
1392 * Update the tty layer's idea of the carrier
1393 * bit, in case we changed CLOCAL or MDMBUF.
1394 * We don't hang up here; we only do that by
1395 * explicit request.
1396 */
1397 reg = clmpcc_rd_msvr(sc) & CLMPCC_MSVR_CD;
1398 (*tp->t_linesw->l_modem)(tp, reg != 0);
1399 }
1400
1401 CLR(tp->t_state, TS_BUSY);
1402 if ( ISSET(tp->t_state, TS_FLUSH) )
1403 CLR(tp->t_state, TS_FLUSH);
1404 else
1405 ndflush(&tp->t_outq,
1406 (int)(ch->ch_obuf_addr - tp->t_outq.c_cf));
1407
1408 (*tp->t_linesw->l_start)(tp);
1409 }
1410 }
1411 }
1412
1413
1414 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1415 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1416 /*XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX*/
1417 /*
1418 * Following are all routines needed for a cd240x channel to act as console
1419 */
1420 int
clmpcc_cnattach(struct clmpcc_softc * sc,int chan,int rate)1421 clmpcc_cnattach(struct clmpcc_softc *sc, int chan, int rate)
1422 {
1423 cons_sc = sc;
1424 cons_chan = chan;
1425 cons_rate = rate;
1426
1427 return (clmpcc_init(sc));
1428 }
1429
1430 /*
1431 * The following functions are polled getc and putc routines, for console use.
1432 */
1433 static int
clmpcc_common_getc(struct clmpcc_softc * sc,int chan)1434 clmpcc_common_getc(struct clmpcc_softc *sc, int chan)
1435 {
1436 u_char old_chan;
1437 u_char old_ier;
1438 u_char ch, rir, risr;
1439 int s;
1440
1441 s = splhigh();
1442
1443 /* Save the currently active channel */
1444 old_chan = clmpcc_select_channel(sc, chan);
1445
1446 /*
1447 * We have to put the channel into RX interrupt mode before
1448 * trying to read the Rx data register. So save the previous
1449 * interrupt mode.
1450 */
1451 old_ier = clmpcc_rdreg(sc, CLMPCC_REG_IER);
1452 clmpcc_wrreg(sc, CLMPCC_REG_IER, CLMPCC_IER_RX_FIFO);
1453
1454 /* Loop until we get a character */
1455 for (;;) {
1456 /*
1457 * The REN bit will be set in the Receive Interrupt Register
1458 * when the CD240x has a character to process. Remember,
1459 * the RACT bit won't be set until we generate an interrupt
1460 * acknowledge cycle via the MD front-end.
1461 */
1462 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1463 if ( (rir & CLMPCC_RIR_REN) == 0 )
1464 continue;
1465
1466 /* Acknowledge the request */
1467 if ( sc->sc_iackhook )
1468 (sc->sc_iackhook)(sc, CLMPCC_IACK_RX);
1469
1470 /*
1471 * Determine if the interrupt is for the required channel
1472 * and if valid data is available.
1473 */
1474 rir = clmpcc_rdreg(sc, CLMPCC_REG_RIR);
1475 risr = clmpcc_rdreg(sc, CLMPCC_REG_RISR);
1476 if ( (rir & CLMPCC_RIR_RCN_MASK) != chan ||
1477 risr != 0 ) {
1478 /* Rx error, or BREAK */
1479 clmpcc_wrreg(sc, CLMPCC_REG_REOIR,
1480 CLMPCC_REOIR_NO_TRANS);
1481 } else {
1482 /* Dummy read of the FIFO count register */
1483 (void) clmpcc_rdreg(sc, CLMPCC_REG_RFOC);
1484
1485 /* Fetch the received character */
1486 ch = clmpcc_rd_rxdata(sc);
1487
1488 clmpcc_wrreg(sc, CLMPCC_REG_REOIR, 0);
1489 break;
1490 }
1491 }
1492
1493 /* Restore the original IER and CAR register contents */
1494 clmpcc_wrreg(sc, CLMPCC_REG_IER, old_ier);
1495 clmpcc_select_channel(sc, old_chan);
1496
1497 splx(s);
1498 return ch;
1499 }
1500
1501
1502 static void
clmpcc_common_putc(struct clmpcc_softc * sc,int chan,int c)1503 clmpcc_common_putc(struct clmpcc_softc *sc, int chan, int c)
1504 {
1505 u_char old_chan;
1506 int s = splhigh();
1507
1508 /* Save the currently active channel */
1509 old_chan = clmpcc_select_channel(sc, chan);
1510
1511 /*
1512 * Since we can only access the Tx Data register from within
1513 * the interrupt handler, the easiest way to get console data
1514 * onto the wire is using one of the Special Transmit Character
1515 * registers.
1516 */
1517 clmpcc_wrreg(sc, CLMPCC_REG_SCHR4, c);
1518 clmpcc_wrreg(sc, CLMPCC_REG_STCR, CLMPCC_STCR_SSPC(4) |
1519 CLMPCC_STCR_SND_SPC);
1520
1521 /* Wait until the "Send Special Character" command is accepted */
1522 while ( clmpcc_rdreg(sc, CLMPCC_REG_STCR) != 0 )
1523 ;
1524
1525 /* Restore the previous channel selected */
1526 clmpcc_select_channel(sc, old_chan);
1527
1528 splx(s);
1529 }
1530
1531 int
clmpcccngetc(dev_t dev)1532 clmpcccngetc(dev_t dev)
1533 {
1534 return clmpcc_common_getc(cons_sc, cons_chan);
1535 }
1536
1537 /*
1538 * Console kernel output character routine.
1539 */
1540 void
clmpcccnputc(dev_t dev,int c)1541 clmpcccnputc(dev_t dev, int c)
1542 {
1543 if ( c == '\n' )
1544 clmpcc_common_putc(cons_sc, cons_chan, '\r');
1545
1546 clmpcc_common_putc(cons_sc, cons_chan, c);
1547 }
1548